\r
**/\r
\r
-\r
#ifndef _EFI_PCI_BUS_H_\r
#define _EFI_PCI_BUS_H_\r
\r
#include <IndustryStandard/PeImage.h>\r
#include <IndustryStandard/Acpi.h>\r
\r
-typedef struct _PCI_IO_DEVICE PCI_IO_DEVICE;\r
-typedef struct _PCI_BAR PCI_BAR;\r
+typedef struct _PCI_IO_DEVICE PCI_IO_DEVICE;\r
+typedef struct _PCI_BAR PCI_BAR;\r
\r
#define EFI_PCI_RID(Bus, Device, Function) (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)\r
#define EFI_PCI_BUS_OF_RID(RID) ((UINT32)RID >> 8)\r
\r
-#define EFI_PCI_IOV_POLICY_ARI 0x0001\r
-#define EFI_PCI_IOV_POLICY_SRIOV 0x0002\r
-#define EFI_PCI_IOV_POLICY_MRIOV 0x0004\r
+#define EFI_PCI_IOV_POLICY_ARI 0x0001\r
+#define EFI_PCI_IOV_POLICY_SRIOV 0x0002\r
+#define EFI_PCI_IOV_POLICY_MRIOV 0x0004\r
\r
typedef enum {\r
PciBarTypeUnknown = 0,\r
#include "PciHotPlugSupport.h"\r
#include "PciLib.h"\r
\r
-#define VGABASE1 0x3B0\r
-#define VGALIMIT1 0x3BB\r
+#define VGABASE1 0x3B0\r
+#define VGALIMIT1 0x3BB\r
\r
-#define VGABASE2 0x3C0\r
-#define VGALIMIT2 0x3DF\r
+#define VGABASE2 0x3C0\r
+#define VGALIMIT2 0x3DF\r
\r
#define ISABASE 0x100\r
#define ISALIMIT 0x3FF\r
// PCI BAR parameters\r
//\r
struct _PCI_BAR {\r
- UINT64 BaseAddress;\r
- UINT64 Length;\r
- UINT64 Alignment;\r
- PCI_BAR_TYPE BarType;\r
- BOOLEAN BarTypeFixed;\r
- UINT16 Offset;\r
+ UINT64 BaseAddress;\r
+ UINT64 Length;\r
+ UINT64 Alignment;\r
+ PCI_BAR_TYPE BarType;\r
+ BOOLEAN BarTypeFixed;\r
+ UINT16 Offset;\r
};\r
\r
//\r
// defined in PCI Card Specification, 8.0\r
//\r
-#define PCI_CARD_MEMORY_BASE_0 0x1C\r
-#define PCI_CARD_MEMORY_LIMIT_0 0x20\r
-#define PCI_CARD_MEMORY_BASE_1 0x24\r
-#define PCI_CARD_MEMORY_LIMIT_1 0x28\r
-#define PCI_CARD_IO_BASE_0_LOWER 0x2C\r
-#define PCI_CARD_IO_BASE_0_UPPER 0x2E\r
-#define PCI_CARD_IO_LIMIT_0_LOWER 0x30\r
-#define PCI_CARD_IO_LIMIT_0_UPPER 0x32\r
-#define PCI_CARD_IO_BASE_1_LOWER 0x34\r
-#define PCI_CARD_IO_BASE_1_UPPER 0x36\r
-#define PCI_CARD_IO_LIMIT_1_LOWER 0x38\r
-#define PCI_CARD_IO_LIMIT_1_UPPER 0x3A\r
-#define PCI_CARD_BRIDGE_CONTROL 0x3E\r
-\r
-#define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8\r
-#define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9\r
-\r
-#define RB_IO_RANGE 1\r
-#define RB_MEM32_RANGE 2\r
-#define RB_PMEM32_RANGE 3\r
-#define RB_MEM64_RANGE 4\r
-#define RB_PMEM64_RANGE 5\r
-\r
-#define PPB_BAR_0 0\r
-#define PPB_BAR_1 1\r
-#define PPB_IO_RANGE 2\r
-#define PPB_MEM32_RANGE 3\r
-#define PPB_PMEM32_RANGE 4\r
-#define PPB_PMEM64_RANGE 5\r
-#define PPB_MEM64_RANGE 0xFF\r
-\r
-#define P2C_BAR_0 0\r
-#define P2C_MEM_1 1\r
-#define P2C_MEM_2 2\r
-#define P2C_IO_1 3\r
-#define P2C_IO_2 4\r
-\r
-#define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001\r
-#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002\r
-#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004\r
-#define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008\r
-#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010\r
-#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020\r
-#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040\r
-\r
-#define PCI_MAX_HOST_BRIDGE_NUM 0x0010\r
+#define PCI_CARD_MEMORY_BASE_0 0x1C\r
+#define PCI_CARD_MEMORY_LIMIT_0 0x20\r
+#define PCI_CARD_MEMORY_BASE_1 0x24\r
+#define PCI_CARD_MEMORY_LIMIT_1 0x28\r
+#define PCI_CARD_IO_BASE_0_LOWER 0x2C\r
+#define PCI_CARD_IO_BASE_0_UPPER 0x2E\r
+#define PCI_CARD_IO_LIMIT_0_LOWER 0x30\r
+#define PCI_CARD_IO_LIMIT_0_UPPER 0x32\r
+#define PCI_CARD_IO_BASE_1_LOWER 0x34\r
+#define PCI_CARD_IO_BASE_1_UPPER 0x36\r
+#define PCI_CARD_IO_LIMIT_1_LOWER 0x38\r
+#define PCI_CARD_IO_LIMIT_1_UPPER 0x3A\r
+#define PCI_CARD_BRIDGE_CONTROL 0x3E\r
+\r
+#define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8\r
+#define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9\r
+\r
+#define RB_IO_RANGE 1\r
+#define RB_MEM32_RANGE 2\r
+#define RB_PMEM32_RANGE 3\r
+#define RB_MEM64_RANGE 4\r
+#define RB_PMEM64_RANGE 5\r
+\r
+#define PPB_BAR_0 0\r
+#define PPB_BAR_1 1\r
+#define PPB_IO_RANGE 2\r
+#define PPB_MEM32_RANGE 3\r
+#define PPB_PMEM32_RANGE 4\r
+#define PPB_PMEM64_RANGE 5\r
+#define PPB_MEM64_RANGE 0xFF\r
+\r
+#define P2C_BAR_0 0\r
+#define P2C_MEM_1 1\r
+#define P2C_MEM_2 2\r
+#define P2C_IO_1 3\r
+#define P2C_IO_2 4\r
+\r
+#define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001\r
+#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002\r
+#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004\r
+#define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008\r
+#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010\r
+#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020\r
+#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040\r
+\r
+#define PCI_MAX_HOST_BRIDGE_NUM 0x0010\r
\r
//\r
// Define option for attribute\r
#define EFI_SET_SUPPORTS 0\r
#define EFI_SET_ATTRIBUTES 1\r
\r
-#define PCI_IO_DEVICE_SIGNATURE SIGNATURE_32 ('p', 'c', 'i', 'o')\r
+#define PCI_IO_DEVICE_SIGNATURE SIGNATURE_32 ('p', 'c', 'i', 'o')\r
\r
struct _PCI_IO_DEVICE {\r
- UINT32 Signature;\r
- EFI_HANDLE Handle;\r
- EFI_PCI_IO_PROTOCOL PciIo;\r
- LIST_ENTRY Link;\r
+ UINT32 Signature;\r
+ EFI_HANDLE Handle;\r
+ EFI_PCI_IO_PROTOCOL PciIo;\r
+ LIST_ENTRY Link;\r
\r
- EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;\r
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
- EFI_LOAD_FILE2_PROTOCOL LoadFile2;\r
+ EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;\r
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
+ EFI_LOAD_FILE2_PROTOCOL LoadFile2;\r
\r
//\r
// PCI configuration space header type\r
//\r
- PCI_TYPE00 Pci;\r
+ PCI_TYPE00 Pci;\r
\r
//\r
// Bus number, Device number, Function number\r
//\r
- UINT8 BusNumber;\r
- UINT8 DeviceNumber;\r
- UINT8 FunctionNumber;\r
+ UINT8 BusNumber;\r
+ UINT8 DeviceNumber;\r
+ UINT8 FunctionNumber;\r
\r
//\r
// BAR for this PCI Device\r
//\r
- PCI_BAR PciBar[PCI_MAX_BAR];\r
+ PCI_BAR PciBar[PCI_MAX_BAR];\r
\r
//\r
// The bridge device this pci device is subject to\r
//\r
- PCI_IO_DEVICE *Parent;\r
+ PCI_IO_DEVICE *Parent;\r
\r
//\r
// A linked list for children Pci Device if it is bridge device\r
//\r
- LIST_ENTRY ChildList;\r
+ LIST_ENTRY ChildList;\r
\r
//\r
// TRUE if the PCI bus driver creates the handle for this PCI device\r
//\r
- BOOLEAN Registered;\r
+ BOOLEAN Registered;\r
\r
//\r
// TRUE if the PCI bus driver successfully allocates the resource required by\r
// this PCI device\r
//\r
- BOOLEAN Allocated;\r
+ BOOLEAN Allocated;\r
\r
//\r
// The attribute this PCI device currently set\r
//\r
- UINT64 Attributes;\r
+ UINT64 Attributes;\r
\r
//\r
// The attributes this PCI device actually supports\r
//\r
- UINT64 Supports;\r
+ UINT64 Supports;\r
\r
//\r
// The resource decode the bridge supports\r
//\r
- UINT32 Decodes;\r
+ UINT32 Decodes;\r
\r
//\r
// TRUE if the ROM image is from the PCI Option ROM BAR\r
//\r
- BOOLEAN EmbeddedRom;\r
+ BOOLEAN EmbeddedRom;\r
\r
//\r
// The OptionRom Size\r
//\r
- UINT32 RomSize;\r
+ UINT32 RomSize;\r
\r
//\r
// TRUE if all OpROM (in device or in platform specific position) have been processed\r
//\r
- BOOLEAN AllOpRomProcessed;\r
+ BOOLEAN AllOpRomProcessed;\r
\r
//\r
// TRUE if there is any EFI driver in the OptionRom\r
//\r
- BOOLEAN BusOverride;\r
+ BOOLEAN BusOverride;\r
\r
//\r
// A list tracking reserved resource on a bridge device\r
//\r
- LIST_ENTRY ReservedResourceList;\r
+ LIST_ENTRY ReservedResourceList;\r
\r
//\r
// A list tracking image handle of platform specific overriding driver\r
//\r
- LIST_ENTRY OptionRomDriverList;\r
+ LIST_ENTRY OptionRomDriverList;\r
\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ResourcePaddingDescriptors;\r
- EFI_HPC_PADDING_ATTRIBUTES PaddingAttributes;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ResourcePaddingDescriptors;\r
+ EFI_HPC_PADDING_ATTRIBUTES PaddingAttributes;\r
\r
//\r
// Bus number ranges for a PCI Root Bridge device\r
//\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *BusNumberRanges;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *BusNumberRanges;\r
\r
- BOOLEAN IsPciExp;\r
+ BOOLEAN IsPciExp;\r
//\r
// For SR-IOV\r
//\r
- UINT8 PciExpressCapabilityOffset;\r
- UINT32 AriCapabilityOffset;\r
- UINT32 SrIovCapabilityOffset;\r
- UINT32 MrIovCapabilityOffset;\r
- PCI_BAR VfPciBar[PCI_MAX_BAR];\r
- UINT32 SystemPageSize;\r
- UINT16 InitialVFs;\r
- UINT16 ReservedBusNum;\r
+ UINT8 PciExpressCapabilityOffset;\r
+ UINT32 AriCapabilityOffset;\r
+ UINT32 SrIovCapabilityOffset;\r
+ UINT32 MrIovCapabilityOffset;\r
+ PCI_BAR VfPciBar[PCI_MAX_BAR];\r
+ UINT32 SystemPageSize;\r
+ UINT16 InitialVFs;\r
+ UINT16 ReservedBusNum;\r
//\r
// Per PCI to PCI Bridge spec, I/O window is 4K aligned,\r
// but some chipsets support non-standard I/O window alignments less than 4K.\r
// This field is used to support this case.\r
//\r
- UINT16 BridgeIoAlignment;\r
- UINT32 ResizableBarOffset;\r
- UINT32 ResizableBarNumber;\r
+ UINT16 BridgeIoAlignment;\r
+ UINT32 ResizableBarOffset;\r
+ UINT32 ResizableBarNumber;\r
};\r
\r
#define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \\r
#define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \\r
CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)\r
\r
-\r
-\r
//\r
// Global Variables\r
//\r
-extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gIncompatiblePciDeviceSupport;\r
-extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;\r
-extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;\r
-extern EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2;\r
-extern BOOLEAN gFullEnumeration;\r
-extern UINTN gPciHostBridgeNumber;\r
-extern EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];\r
-extern UINT64 gAllOne;\r
-extern UINT64 gAllZero;\r
-extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;\r
-extern EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol;\r
-extern BOOLEAN mReserveIsaAliases;\r
-extern BOOLEAN mReserveVgaAliases;\r
+extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gIncompatiblePciDeviceSupport;\r
+extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;\r
+extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;\r
+extern EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2;\r
+extern BOOLEAN gFullEnumeration;\r
+extern UINTN gPciHostBridgeNumber;\r
+extern EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];\r
+extern UINT64 gAllOne;\r
+extern UINT64 gAllZero;\r
+extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;\r
+extern EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol;\r
+extern BOOLEAN mReserveIsaAliases;\r
+extern BOOLEAN mReserveVgaAliases;\r
\r
/**\r
Macro that checks whether device is a GFX device.\r
@retval FALSE Device is not a GFX device.\r
\r
**/\r
-#define IS_PCI_GFX(_p) IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)\r
+#define IS_PCI_GFX(_p) IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)\r
\r
/**\r
Test to see if this driver supports ControllerHandle. Any ControllerHandle\r
EFI_STATUS\r
EFIAPI\r
PciBusDriverBindingSupported (\r
- IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
- IN EFI_HANDLE Controller,\r
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
+ IN EFI_HANDLE Controller,\r
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
PciBusDriverBindingStart (\r
- IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
- IN EFI_HANDLE Controller,\r
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
+ IN EFI_HANDLE Controller,\r
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
PciBusDriverBindingStop (\r
- IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
- IN EFI_HANDLE Controller,\r
- IN UINTN NumberOfChildren,\r
- IN EFI_HANDLE *ChildHandleBuffer\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
+ IN EFI_HANDLE Controller,\r
+ IN UINTN NumberOfChildren,\r
+ IN EFI_HANDLE *ChildHandleBuffer\r
);\r
\r
#endif\r
projects / mirror_edk2.git / blobdiff