/** @file\r
PCI command register operations supporting functions implementation for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution. The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
-\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
**/\r
EFI_STATUS\r
PciOperateRegister (\r
- IN PCI_IO_DEVICE *PciIoDevice,\r
- IN UINT16 Command,\r
- IN UINT8 Offset,\r
- IN UINT8 Operation,\r
- OUT UINT16 *PtrCommand\r
+ IN PCI_IO_DEVICE *PciIoDevice,\r
+ IN UINT16 Command,\r
+ IN UINT8 Offset,\r
+ IN UINT8 Operation,\r
+ OUT UINT16 *PtrCommand\r
)\r
{\r
- UINT16 OldCommand;\r
- EFI_STATUS Status;\r
- EFI_PCI_IO_PROTOCOL *PciIo;\r
+ UINT16 OldCommand;\r
+ EFI_STATUS Status;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
\r
- OldCommand = 0;\r
- PciIo = &PciIoDevice->PciIo;\r
+ OldCommand = 0;\r
+ PciIo = &PciIoDevice->PciIo;\r
\r
if (Operation != EFI_SET_REGISTER) {\r
Status = PciIo->Pci.Read (\r
}\r
\r
if (Operation == EFI_ENABLE_REGISTER) {\r
- OldCommand = (UINT16) (OldCommand | Command);\r
+ OldCommand = (UINT16)(OldCommand | Command);\r
} else if (Operation == EFI_DISABLE_REGISTER) {\r
- OldCommand = (UINT16) (OldCommand & ~(Command));\r
+ OldCommand = (UINT16)(OldCommand & ~(Command));\r
} else {\r
OldCommand = Command;\r
}\r
}\r
\r
/**\r
- Check the cpability supporting by given device.\r
+ Check the capability supporting by given device.\r
\r
@param PciIoDevice Pointer to instance of PCI_IO_DEVICE.\r
\r
- @retval TRUE Cpability supportted.\r
- @retval FALSE Cpability not supportted.\r
+ @retval TRUE Capability supported.\r
+ @retval FALSE Capability not supported.\r
\r
**/\r
BOOLEAN\r
@param Offset A pointer to the offset returned.\r
@param NextRegBlock A pointer to the next block returned.\r
\r
- @retval EFI_SUCCESS Successfuly located capability register block.\r
+ @retval EFI_SUCCESS Successfully located capability register block.\r
@retval EFI_UNSUPPORTED Pci device does not support capability.\r
@retval EFI_NOT_FOUND Pci device support but can not find register block.\r
\r
UINT8 CapabilityID;\r
\r
//\r
- // To check the cpability of this device supports\r
+ // To check the capability of this device supports\r
//\r
if (!PciCapabilitySupport (PciIoDevice)) {\r
return EFI_UNSUPPORTED;\r
if (*Offset != 0) {\r
CapabilityPtr = *Offset;\r
} else {\r
-\r
CapabilityPtr = 0;\r
if (IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {\r
-\r
PciIoDevice->PciIo.Pci.Read (\r
&PciIoDevice->PciIo,\r
EfiPciIoWidthUint8,\r
&CapabilityPtr\r
);\r
} else {\r
-\r
PciIoDevice->PciIo.Pci.Read (\r
&PciIoDevice->PciIo,\r
EfiPciIoWidthUint8,\r
&CapabilityEntry\r
);\r
\r
- CapabilityID = (UINT8) CapabilityEntry;\r
+ CapabilityID = (UINT8)CapabilityEntry;\r
\r
if (CapabilityID == CapId) {\r
*Offset = CapabilityPtr;\r
if (NextRegBlock != NULL) {\r
- *NextRegBlock = (UINT8) (CapabilityEntry >> 8);\r
+ *NextRegBlock = (UINT8)(CapabilityEntry >> 8);\r
}\r
\r
return EFI_SUCCESS;\r
}\r
\r
- CapabilityPtr = (UINT8) (CapabilityEntry >> 8);\r
+ //\r
+ // Certain PCI device may incorrectly have capability pointing to itself,\r
+ // break to avoid dead loop.\r
+ //\r
+ if (CapabilityPtr == (UINT8)(CapabilityEntry >> 8)) {\r
+ break;\r
+ }\r
+\r
+ CapabilityPtr = (UINT8)(CapabilityEntry >> 8);\r
}\r
\r
return EFI_NOT_FOUND;\r
@param Offset A pointer to the offset returned.\r
@param NextRegBlock A pointer to the next block returned.\r
\r
- @retval EFI_SUCCESS Successfuly located capability register block.\r
+ @retval EFI_SUCCESS Successfully located capability register block.\r
@retval EFI_UNSUPPORTED Pci device does not support capability.\r
@retval EFI_NOT_FOUND Pci device support but can not find register block.\r
\r
**/\r
EFI_STATUS\r
LocatePciExpressCapabilityRegBlock (\r
- IN PCI_IO_DEVICE *PciIoDevice,\r
- IN UINT16 CapId,\r
- IN OUT UINT32 *Offset,\r
- OUT UINT32 *NextRegBlock OPTIONAL\r
+ IN PCI_IO_DEVICE *PciIoDevice,\r
+ IN UINT16 CapId,\r
+ IN OUT UINT32 *Offset,\r
+ OUT UINT32 *NextRegBlock OPTIONAL\r
)\r
{\r
- UINT32 CapabilityPtr;\r
- UINT32 CapabilityEntry;\r
- UINT16 CapabilityID;\r
+ EFI_STATUS Status;\r
+ UINT32 CapabilityPtr;\r
+ UINT32 CapabilityEntry;\r
+ UINT16 CapabilityID;\r
\r
//\r
// To check the capability of this device supports\r
// Mask it to DWORD alignment per PCI spec\r
//\r
CapabilityPtr &= 0xFFC;\r
- PciIoDevice->PciIo.Pci.Read (\r
- &PciIoDevice->PciIo,\r
- EfiPciIoWidthUint32,\r
- CapabilityPtr,\r
- 1,\r
- &CapabilityEntry\r
- );\r
+ Status = PciIoDevice->PciIo.Pci.Read (\r
+ &PciIoDevice->PciIo,\r
+ EfiPciIoWidthUint32,\r
+ CapabilityPtr,\r
+ 1,\r
+ &CapabilityEntry\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ break;\r
+ }\r
+\r
+ if (CapabilityEntry == MAX_UINT32) {\r
+ DEBUG ((\r
+ DEBUG_WARN,\r
+ "%a: [%02x|%02x|%02x] failed to access config space at offset 0x%x\n",\r
+ __FUNCTION__,\r
+ PciIoDevice->BusNumber,\r
+ PciIoDevice->DeviceNumber,\r
+ PciIoDevice->FunctionNumber,\r
+ CapabilityPtr\r
+ ));\r
+ break;\r
+ }\r
\r
- CapabilityID = (UINT16) CapabilityEntry;\r
+ CapabilityID = (UINT16)CapabilityEntry;\r
\r
if (CapabilityID == CapId) {\r
*Offset = CapabilityPtr;\r
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