1) Add type cast for better coding style.

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / PciBusDxe / PciEnumeratorSupport.c

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
index ccec37b2870cf29766d0b1bc27e3bd98e06a53f5..9e7ac74eb70c331f56c57f035953435fce8b877f 100644 (file)
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
@@ -1,7 +1,7 @@
 /** @file\r
   PCI emumeration support functions implementation for PCI Bus module.\r
 \r
-Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -334,7 +334,7 @@ DumpPciBars (
 \r
     DEBUG ((\r
       EFI_D_INFO,\r
-      "   BAR[%d]: Type = %s; Alignment = 0x%x;\tLength = 0x%x;\tOffset = 0x%02x\n",\r
+      "   BAR[%d]: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx;\tOffset = 0x%02x\n",\r
       Index, mBarTypeStr[MIN (PciIoDevice->PciBar[Index].BarType, PciBarTypeMaxType)],\r
       PciIoDevice->PciBar[Index].Alignment, PciIoDevice->PciBar[Index].Length, PciIoDevice->PciBar[Index].Offset\r
       ));\r
@@ -347,7 +347,7 @@ DumpPciBars (
 \r
     DEBUG ((\r
       EFI_D_INFO,\r
-      " VFBAR[%d]: Type = %s; Alignment = 0x%x;\tLength = 0x%x;\tOffset = 0x%02x\n",\r
+      " VFBAR[%d]: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx;\tOffset = 0x%02x\n",\r
       Index, mBarTypeStr[MIN (PciIoDevice->VfPciBar[Index].BarType, PciBarTypeMaxType)],\r
       PciIoDevice->VfPciBar[Index].Alignment, PciIoDevice->VfPciBar[Index].Length, PciIoDevice->VfPciBar[Index].Offset\r
       ));\r
@@ -392,14 +392,6 @@ GatherDeviceInfo (
     return NULL;\r
   }\r
 \r
-  //\r
-  // Create a device path for this PCI device and store it into its private data\r
-  //\r
-  CreatePciDevicePath (\r
-    Bridge->DevicePath,\r
-    PciIoDevice\r
-    );\r
-\r
   //\r
   // If it is a full enumeration, disconnect the device in advance\r
   //\r
@@ -459,6 +451,9 @@ GatherPpbInfo (
   UINT8                           Value;\r
   EFI_PCI_IO_PROTOCOL             *PciIo;\r
   UINT8                           Temp;\r
+  UINT32                          PMemBaseLimit;\r
+  UINT16                          PrefetchableMemoryBase;\r
+  UINT16                          PrefetchableMemoryLimit;\r
 \r
   PciIoDevice = CreatePciIoDevice (\r
                   Bridge,\r
@@ -472,14 +467,6 @@ GatherPpbInfo (
     return NULL;\r
   }\r
 \r
-  //\r
-  // Create a device path for this PCI device and store it into its private data\r
-  //\r
-  CreatePciDevicePath (\r
-    Bridge->DevicePath,\r
-    PciIoDevice\r
-    );\r
-\r
   if (gFullEnumeration) {\r
     PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);\r
 \r
@@ -552,14 +539,22 @@ GatherPpbInfo (
             PciIoDevice,\r
             0x24,\r
             NULL,\r
-            NULL\r
+            &PMemBaseLimit\r
             );\r
 \r
   //\r
   // Test if it supports 64 memory or not\r
   //\r
-  if (!EFI_ERROR (Status)) {\r
-\r
+  // The bottom 4 bits of both the Prefetchable Memory Base and Prefetchable Memory Limit\r
+  // registers:\r
+  //   0 - the bridge supports only 32 bit addresses.\r
+  //   1 - the bridge supports 64-bit addresses.\r
+  //\r
+  PrefetchableMemoryBase = (UINT16)(PMemBaseLimit & 0xffff);\r
+  PrefetchableMemoryLimit = (UINT16)(PMemBaseLimit >> 16);\r
+  if (!EFI_ERROR (Status) &&\r
+      (PrefetchableMemoryBase & 0x000f) == 0x0001 &&\r
+      (PrefetchableMemoryLimit & 0x000f) == 0x0001) {\r
     Status = BarExisted (\r
               PciIoDevice,\r
               0x28,\r
@@ -623,14 +618,6 @@ GatherP2CInfo (
     return NULL;\r
   }\r
 \r
-  //\r
-  // Create a device path for this PCI device and store it into its private data\r
-  //\r
-  CreatePciDevicePath (\r
-    Bridge->DevicePath,\r
-    PciIoDevice\r
-    );\r
-\r
   if (gFullEnumeration) {\r
     PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);\r
 \r
@@ -960,17 +947,17 @@ PciSetDeviceAttribute (
 \r
   if (Option == EFI_SET_SUPPORTS) {\r
 \r
-    Attributes |= EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE |\r
+    Attributes |= (UINT64) (EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE |\r
                   EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED        |\r
                   EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE       |\r
                   EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE      |\r
                   EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM         |\r
-                  EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE;\r
+                  EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE);\r
 \r
     if (IS_PCI_LPC (&PciIoDevice->Pci)) {\r
         Attributes |= EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO;\r
-        Attributes |= (mReserveIsaAliases ? EFI_PCI_IO_ATTRIBUTE_ISA_IO : \\r
-                                            EFI_PCI_IO_ATTRIBUTE_ISA_IO_16);\r
+        Attributes |= (mReserveIsaAliases ? (UINT64) EFI_PCI_IO_ATTRIBUTE_ISA_IO : \\r
+                                            (UINT64) EFI_PCI_IO_ATTRIBUTE_ISA_IO_16);\r
     }\r
 \r
     if (IS_PCI_BRIDGE (&PciIoDevice->Pci) || IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {\r
@@ -996,8 +983,8 @@ PciSetDeviceAttribute (
 \r
       if (IS_PCI_VGA (&PciIoDevice->Pci)) {\r
         Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY;\r
-        Attributes |= (mReserveVgaAliases ? EFI_PCI_IO_ATTRIBUTE_VGA_IO : \\r
-                                            EFI_PCI_IO_ATTRIBUTE_VGA_IO_16);\r
+        Attributes |= (mReserveVgaAliases ? (UINT64) EFI_PCI_IO_ATTRIBUTE_VGA_IO : \\r
+                                            (UINT64) EFI_PCI_IO_ATTRIBUTE_VGA_IO_16);\r
       }\r
     }\r
 \r
@@ -1133,7 +1120,7 @@ DetermineDeviceAttribute (
     //\r
     // Assume the PCI Root Bridge supports DAC\r
     //\r
-    PciIoDevice->Supports |= (EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE |\r
+    PciIoDevice->Supports |= (UINT64)(EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE |\r
                               EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM |\r
                               EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE);\r
 \r
@@ -1462,8 +1449,6 @@ PciIovParseVfBar (
   UINT32      Value;\r
   UINT32      OriginalValue;\r
   UINT32      Mask;\r
-  UINT32      Data;\r
-  UINT8       Index;\r
   EFI_STATUS  Status;\r
 \r
   //\r
@@ -1581,12 +1566,7 @@ PciIovParseVfBar (
       //\r
       // Fix the length to support some spefic 64 bit BAR\r
       //\r
-      Data  = Value;\r
-      Index = 0;\r
-      for (Data = Value; Data != 0; Data >>= 1) {\r
-       Index ++;\r
-      }\r
-      Value |= ((UINT32)(-1) << Index); \r
+      Value |= ((UINT32) -1 << HighBitSet32 (Value));\r
 \r
       //\r
       // Calculate the size of 64bit bar\r
@@ -1661,8 +1641,6 @@ PciParseBar (
   UINT32      Value;\r
   UINT32      OriginalValue;\r
   UINT32      Mask;\r
-  UINT32      Data;\r
-  UINT8       Index;\r
   EFI_STATUS  Status;\r
 \r
   OriginalValue = 0;\r
@@ -1799,12 +1777,7 @@ PciParseBar (
       //\r
       // Fix the length to support some spefic 64 bit BAR\r
       //\r
-      Data  = Value;\r
-      Index = 0;\r
-      for (Data = Value; Data != 0; Data >>= 1) {\r
-        Index ++;\r
-      }\r
-      Value |= ((UINT32)(-1) << Index);\r
+      Value |= ((UINT32)(-1) << HighBitSet32 (Value));\r
 \r
       //\r
       // Calculate the size of 64bit bar\r
@@ -2031,6 +2004,14 @@ CreatePciIoDevice (
   InitializePciLoadFile2 (PciIoDevice);\r
   PciIo = &PciIoDevice->PciIo;\r
 \r
+  //\r
+  // Create a device path for this PCI device and store it into its private data\r
+  //\r
+  CreatePciDevicePath (\r
+    Bridge->DevicePath,\r
+    PciIoDevice\r
+    );\r
+\r
   //\r
   // Detect if PCI Express Device\r
   //\r