MdeModulePkg: Clean up source files

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / PciBusDxe / PciIo.c

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
index 190f4b0dc7ededab935a0b617327298608e42999..87b0b9884adfb71408525cd5c10e125379704b94 100644 (file)
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
@@ -1,7 +1,7 @@
 /** @file\r
   EFI PCI IO protocol functions implementation for PCI Bus module.\r
 \r
-Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -232,7 +232,7 @@ PciIoPollMem (
 \r
   //\r
   // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
-  //  \r
+  //\r
   if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
     if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
       Status  = PciIoMemRead (This, Width, BarIndex, Offset, 1, Result);\r
@@ -262,7 +262,7 @@ PciIoPollMem (
       } while (TRUE);\r
     }\r
   }\r
-  \r
+\r
   Status = PciIoDevice->PciRootBridgeIo->PollMem (\r
                                            PciIoDevice->PciRootBridgeIo,\r
                                            (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
@@ -335,7 +335,7 @@ PciIoPollIo (
 \r
   //\r
   // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
-  //  \r
+  //\r
   if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
     if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
       Status  = PciIoIoRead (This, Width, BarIndex, Offset, 1, Result);\r
@@ -365,7 +365,7 @@ PciIoPollIo (
       } while (TRUE);\r
     }\r
   }\r
-  \r
+\r
   Status = PciIoDevice->PciRootBridgeIo->PollIo (\r
                                            PciIoDevice->PciRootBridgeIo,\r
                                            (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
@@ -438,14 +438,14 @@ PciIoMemRead (
 \r
   //\r
   // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
-  //  \r
+  //\r
   if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
     if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
       Count *=  (UINTN)(1 << (Width & 0x03));\r
       Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r
     }\r
-  }  \r
-  \r
+  }\r
+\r
 \r
   Status = PciIoDevice->PciRootBridgeIo->Mem.Read (\r
                                               PciIoDevice->PciRootBridgeIo,\r
@@ -517,7 +517,7 @@ PciIoMemWrite (
 \r
   //\r
   // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
-  //  \r
+  //\r
   if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
     if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
       Count *=  (UINTN)(1 << (Width & 0x03));\r
@@ -595,13 +595,13 @@ PciIoIoRead (
 \r
   //\r
   // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
-  //  \r
+  //\r
   if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
     if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
       Count *=  (UINTN)(1 << (Width & 0x03));\r
       Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r
     }\r
-  }    \r
+  }\r
 \r
   Status = PciIoDevice->PciRootBridgeIo->Io.Read (\r
                                               PciIoDevice->PciRootBridgeIo,\r
@@ -673,13 +673,13 @@ PciIoIoWrite (
 \r
   //\r
   // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
-  //  \r
+  //\r
   if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
     if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
       Count *=  (UINTN)(1 << (Width & 0x03));\r
       Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r
     }\r
-  }  \r
+  }\r
 \r
   Status = PciIoDevice->PciRootBridgeIo->Io.Write (\r
                                               PciIoDevice->PciRootBridgeIo,\r
@@ -739,16 +739,16 @@ PciIoConfigRead (
   if (EFI_ERROR (Status)) {\r
     return Status;\r
   }\r
-  \r
+\r
   //\r
   // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
-  //  \r
+  //\r
   if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
     if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
       Count *=  (UINTN)(1 << (Width & 0x03));\r
       Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r
     }\r
-  }    \r
+  }\r
 \r
   Status = PciIoDevice->PciRootBridgeIo->Pci.Read (\r
                                                PciIoDevice->PciRootBridgeIo,\r
@@ -811,14 +811,14 @@ PciIoConfigWrite (
 \r
   //\r
   // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
-  //  \r
+  //\r
   if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
     if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
       Count *=  (UINTN)(1 << (Width & 0x03));\r
       Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r
     }\r
-  }  \r
-  \r
+  }\r
+\r
   Status = PciIoDevice->PciRootBridgeIo->Pci.Write (\r
                                               PciIoDevice->PciRootBridgeIo,\r
                                               (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
@@ -910,13 +910,13 @@ PciIoCopyMem (
 \r
   //\r
   // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
-  //  \r
+  //\r
   if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
     if ((SrcOffset & ((1 << (Width & 0x03)) - 1)) != 0 || (DestOffset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
       Count *=  (UINTN)(1 << (Width & 0x03));\r
       Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r
     }\r
-  }  \r
+  }\r
 \r
   Status = PciIoDevice->PciRootBridgeIo->CopyMem (\r
                                           PciIoDevice->PciRootBridgeIo,\r
@@ -1790,7 +1790,7 @@ PciIoAttributes (
   @param AddrRangeMin    The base address of the MMIO.\r
   @param AddrLen         The length of the MMIO.\r
 \r
-  @retval The AddrTranslationOffset from RootBridgeIo for the \r
+  @retval The AddrTranslationOffset from RootBridgeIo for the\r
           specified range, or (UINT64) -1 if the range is not\r
           found in RootBridgeIo.\r
 **/\r
@@ -1812,10 +1812,14 @@ GetMmioAddressTranslationOffset (
     return (UINT64) -1;\r
   }\r
 \r
+  // According to UEFI 2.7, EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL::Configuration()\r
+  // returns host address instead of device address, while AddrTranslationOffset\r
+  // is not zero, and device address = host address + AddrTranslationOffset, so\r
+  // we convert host address to device address for range compare.\r
   while (Configuration->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {\r
     if ((Configuration->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) &&\r
-        (Configuration->AddrRangeMin <= AddrRangeMin) &&\r
-        (Configuration->AddrRangeMin + Configuration->AddrLen >= AddrRangeMin + AddrLen)\r
+        (Configuration->AddrRangeMin + Configuration->AddrTranslationOffset <= AddrRangeMin) &&\r
+        (Configuration->AddrRangeMin + Configuration->AddrLen + Configuration->AddrTranslationOffset >= AddrRangeMin + AddrLen)\r
         ) {\r
       return Configuration->AddrTranslationOffset;\r
     }\r
@@ -1968,6 +1972,10 @@ PciIoGetBarAttributes (
         return EFI_UNSUPPORTED;\r
       }\r
     }\r
+\r
+    // According to UEFI spec 2.7, we need return host address for\r
+    // PciIo->GetBarAttributes, and host address = device address - translation.\r
+    Descriptor->AddrRangeMin -= Descriptor->AddrTranslationOffset;\r
   }\r
 \r
   return EFI_SUCCESS;\r