MdeModulePkg/Pci: Add DeviceSecurity support.

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / PciBusDxe / PciLib.c

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c
index 7255bcfbbcea2d06f95deaeafdc4817386b13ded..72690ab6476acc46408e12552c0bc891bd751b9c 100644 (file)
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c
@@ -1,15 +1,9 @@
 /** @file\r
   Internal library implementation for PCI Bus module.\r
 \r
-Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
 (C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>\r
-This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution.  The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
-\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
 \r
@@ -415,7 +409,7 @@ PciHostBridgeResourceAllocator (
   UINT64                                         PMem32ResStatus;\r
   UINT64                                         Mem64ResStatus;\r
   UINT64                                         PMem64ResStatus;\r
-  UINT64                                         MaxOptionRomSize;\r
+  UINT32                                         MaxOptionRomSize;\r
   PCI_RESOURCE_NODE                              *IoBridge;\r
   PCI_RESOURCE_NODE                              *Mem32Bridge;\r
   PCI_RESOURCE_NODE                              *PMem32Bridge;\r
@@ -515,10 +509,12 @@ PciHostBridgeResourceAllocator (
       // All devices' Option ROM share the same MEM32 resource.\r
       //\r
       MaxOptionRomSize = GetMaxOptionRomSize (RootBridgeDev);\r
-      RootBridgeDev->PciBar[0].BarType   = PciBarTypeOpRom;\r
-      RootBridgeDev->PciBar[0].Length    = MaxOptionRomSize;\r
-      RootBridgeDev->PciBar[0].Alignment = MaxOptionRomSize - 1;\r
-      GetResourceFromDevice (RootBridgeDev, IoBridge, Mem32Bridge, PMem32Bridge, Mem64Bridge, PMem64Bridge);\r
+      if (MaxOptionRomSize != 0) {\r
+        RootBridgeDev->PciBar[0].BarType   = PciBarTypeOpRom;\r
+        RootBridgeDev->PciBar[0].Length    = MaxOptionRomSize;\r
+        RootBridgeDev->PciBar[0].Alignment = MaxOptionRomSize - 1;\r
+        GetResourceFromDevice (RootBridgeDev, IoBridge, Mem32Bridge, PMem32Bridge, Mem64Bridge, PMem64Bridge);\r
+      }\r
 \r
       //\r
       // Create resourcemap by going through all the devices subject to this root bridge\r
@@ -1058,7 +1054,9 @@ PciScanBus (
                 &PciDevice\r
                 );\r
 \r
-      ASSERT (!EFI_ERROR (Status));\r
+      if (EFI_ERROR (Status)) {\r
+        continue;\r
+      }\r
 \r
       PciAddress = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0);\r
 \r
@@ -1118,24 +1116,7 @@ PciScanBus (
         //\r
         // For PPB\r
         //\r
-        if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
-          //\r
-          // If Hot Plug is not supported,\r
-          // get the bridge information\r
-          //\r
-          Status = PciSearchDevice (\r
-                    Bridge,\r
-                    &Pci,\r
-                    StartBusNumber,\r
-                    Device,\r
-                    Func,\r
-                    &PciDevice\r
-                    );\r
-\r
-          if (EFI_ERROR (Status)) {\r
-            return Status;\r
-          }\r
-        } else {\r
+        if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
           //\r
           // If Hot Plug is supported,\r
           // Get the bridge information\r