\r
It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.\r
\r
- Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
/**\r
Software reset the specified SD/MMC host controller and enable all interrupts.\r
\r
- @param[in] PciIo The PCI IO protocol instance.\r
+ @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r
@param[in] Slot The slot number of the SD card to send the command to.\r
\r
@retval EFI_SUCCESS The software reset executes successfully.\r
**/\r
EFI_STATUS\r
SdMmcHcReset (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN SD_MMC_HC_PRIVATE_DATA *Private,\r
IN UINT8 Slot\r
)\r
{\r
EFI_STATUS Status;\r
UINT8 SwReset;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
+\r
+ //\r
+ // Notify the SD/MMC override protocol that we are about to reset\r
+ // the SD/MMC host controller.\r
+ //\r
+ if (mOverride != NULL && mOverride->NotifyPhase != NULL) {\r
+ Status = mOverride->NotifyPhase (\r
+ Private->ControllerHandle,\r
+ Slot,\r
+ EdkiiSdMmcResetPre);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_WARN,\r
+ "%a: SD/MMC pre reset notifier callback failed - %r\n",\r
+ __FUNCTION__, Status));\r
+ return Status;\r
+ }\r
+ }\r
\r
- SwReset = 0xFF;\r
- Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_SW_RST, FALSE, sizeof (SwReset), &SwReset);\r
+ PciIo = Private->PciIo;\r
+ SwReset = BIT0;\r
+ Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_SW_RST, sizeof (SwReset), &SwReset);\r
\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_ERROR, "SdMmcHcReset: write full 1 fails: %r\n", Status));\r
+ DEBUG ((DEBUG_ERROR, "SdMmcHcReset: write SW Reset for All fails: %r\n", Status));\r
return Status;\r
}\r
\r
Slot,\r
SD_MMC_HC_SW_RST,\r
sizeof (SwReset),\r
- 0xFF,\r
+ BIT0,\r
0x00,\r
SD_MMC_HC_GENERIC_TIMEOUT\r
);\r
DEBUG ((DEBUG_INFO, "SdMmcHcReset: reset done with %r\n", Status));\r
return Status;\r
}\r
+\r
//\r
// Enable all interrupt after reset all.\r
//\r
Status = SdMmcHcEnableInterrupt (PciIo, Slot);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_INFO, "SdMmcHcReset: SdMmcHcEnableInterrupt done with %r\n",\r
+ Status));\r
+ return Status;\r
+ }\r
+\r
+ //\r
+ // Notify the SD/MMC override protocol that we have just reset\r
+ // the SD/MMC host controller.\r
+ //\r
+ if (mOverride != NULL && mOverride->NotifyPhase != NULL) {\r
+ Status = mOverride->NotifyPhase (\r
+ Private->ControllerHandle,\r
+ Slot,\r
+ EdkiiSdMmcResetPost);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_WARN,\r
+ "%a: SD/MMC post reset notifier callback failed - %r\n",\r
+ __FUNCTION__, Status));\r
+ }\r
+ }\r
\r
return Status;\r
}\r
//\r
// Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.\r
//\r
- if ((ControllerVer & 0xFF) == 2) {\r
+ if (((ControllerVer & 0xFF) >= SD_MMC_HC_CTRL_VER_300) &&\r
+ ((ControllerVer & 0xFF) <= SD_MMC_HC_CTRL_VER_420)) {\r
ASSERT (Divisor <= 0x3FF);\r
ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);\r
} else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) {\r
Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value\r
at initialization.\r
\r
- @param[in] PciIo The PCI IO protocol instance.\r
+ @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.\r
@param[in] Slot The slot number of the SD card to send the command to.\r
- @param[in] Capability The capability of the slot.\r
\r
@retval EFI_SUCCESS The host controller is initialized successfully.\r
@retval Others The host controller isn't initialized successfully.\r
**/\r
EFI_STATUS\r
SdMmcHcInitHost (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN UINT8 Slot,\r
- IN SD_MMC_HC_SLOT_CAP Capability\r
+ IN SD_MMC_HC_PRIVATE_DATA *Private,\r
+ IN UINT8 Slot\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
+ SD_MMC_HC_SLOT_CAP Capability;\r
+\r
+ //\r
+ // Notify the SD/MMC override protocol that we are about to initialize\r
+ // the SD/MMC host controller.\r
+ //\r
+ if (mOverride != NULL && mOverride->NotifyPhase != NULL) {\r
+ Status = mOverride->NotifyPhase (\r
+ Private->ControllerHandle,\r
+ Slot,\r
+ EdkiiSdMmcInitHostPre);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_WARN,\r
+ "%a: SD/MMC pre init notifier callback failed - %r\n",\r
+ __FUNCTION__, Status));\r
+ return Status;\r
+ }\r
+ }\r
+\r
+ PciIo = Private->PciIo;\r
+ Capability = Private->Capability[Slot];\r
\r
Status = SdMmcHcInitClockFreq (PciIo, Slot, Capability);\r
if (EFI_ERROR (Status)) {\r
}\r
\r
Status = SdMmcHcInitTimeoutCtrl (PciIo, Slot);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ //\r
+ // Notify the SD/MMC override protocol that we are have just initialized\r
+ // the SD/MMC host controller.\r
+ //\r
+ if (mOverride != NULL && mOverride->NotifyPhase != NULL) {\r
+ Status = mOverride->NotifyPhase (\r
+ Private->ControllerHandle,\r
+ Slot,\r
+ EdkiiSdMmcInitHostPost);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_WARN,\r
+ "%a: SD/MMC post init notifier callback failed - %r\n",\r
+ __FUNCTION__, Status));\r
+ }\r
+ }\r
return Status;\r
}\r
\r
goto Error;\r
}\r
\r
- if (Trb->DataLen < Trb->BlockSize) {\r
+ if ((Trb->DataLen != 0) && (Trb->DataLen < Trb->BlockSize)) {\r
Trb->BlockSize = (UINT16)Trb->DataLen;\r
}\r
\r
projects / mirror_edk2.git / blobdiff