\r
Provides some data structure definitions used by the SD/MMC host controller driver.\r
\r
+Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.\r
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution. The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
-\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#define SD_MMC_HC_CTRL_MMC_HS200 0x0003\r
#define SD_MMC_HC_CTRL_MMC_HS400 0x0005\r
\r
+#define SD_MMC_HC_CTRL_DRIVER_STRENGTH_MASK 0x0030\r
+\r
//\r
// The transfer modes supported by SD Host Controller\r
-// Simplified Spec 3.0 Table 1-2\r
//\r
typedef enum {\r
SdMmcNoData,\r
SdMmcPioMode,\r
SdMmcSdmaMode,\r
- SdMmcAdmaMode\r
+ SdMmcAdma32bMode,\r
+ SdMmcAdma64bV3Mode,\r
+ SdMmcAdma64bV4Mode\r
} SD_MMC_HC_TRANSFER_MODE;\r
\r
+//\r
+// The ADMA transfer lengths supported by SD Host Controller\r
+//\r
+typedef enum {\r
+ SdMmcAdmaLen16b,\r
+ SdMmcAdmaLen26b\r
+} SD_MMC_HC_ADMA_LENGTH_MODE;\r
+\r
//\r
// The maximum data length of each descriptor line\r
//\r
-#define ADMA_MAX_DATA_PER_LINE 0x10000\r
+#define ADMA_MAX_DATA_PER_LINE_16B SIZE_64KB\r
+#define ADMA_MAX_DATA_PER_LINE_26B SIZE_64MB\r
\r
+//\r
+// ADMA descriptor for 32b addressing.\r
+//\r
typedef struct {\r
UINT32 Valid:1;\r
UINT32 End:1;\r
UINT32 Int:1;\r
UINT32 Reserved:1;\r
UINT32 Act:2;\r
- UINT32 Reserved1:10;\r
- UINT32 Length:16;\r
+ UINT32 UpperLength:10;\r
+ UINT32 LowerLength:16;\r
UINT32 Address;\r
-} SD_MMC_HC_ADMA_DESC_LINE;\r
+} SD_MMC_HC_ADMA_32_DESC_LINE;\r
+\r
+//\r
+// ADMA descriptor for 64b addressing.\r
+//\r
+typedef struct {\r
+ UINT32 Valid:1;\r
+ UINT32 End:1;\r
+ UINT32 Int:1;\r
+ UINT32 Reserved:1;\r
+ UINT32 Act:2;\r
+ UINT32 UpperLength:10;\r
+ UINT32 LowerLength:16;\r
+ UINT32 LowerAddress;\r
+ UINT32 UpperAddress;\r
+} SD_MMC_HC_ADMA_64_V3_DESC_LINE;\r
+\r
+typedef struct {\r
+ UINT32 Valid:1;\r
+ UINT32 End:1;\r
+ UINT32 Int:1;\r
+ UINT32 Reserved:1;\r
+ UINT32 Act:2;\r
+ UINT32 UpperLength:10;\r
+ UINT32 LowerLength:16;\r
+ UINT32 LowerAddress;\r
+ UINT32 UpperAddress;\r
+ UINT32 Reserved1;\r
+} SD_MMC_HC_ADMA_64_V4_DESC_LINE;\r
\r
#define SD_MMC_SDMA_BOUNDARY 512 * 1024\r
#define SD_MMC_SDMA_ROUND_UP(x, n) (((x) + n) & ~(n - 1))\r
UINT32 Voltage33:1; // bit 24\r
UINT32 Voltage30:1; // bit 25\r
UINT32 Voltage18:1; // bit 26\r
- UINT32 Reserved3:1; // bit 27\r
- UINT32 SysBus64:1; // bit 28\r
+ UINT32 SysBus64V4:1; // bit 27\r
+ UINT32 SysBus64V3:1; // bit 28\r
UINT32 AsyncInt:1; // bit 29\r
UINT32 SlotType:2; // bit 30:31\r
UINT32 Sdr50:1; // bit 32\r
UINT32 Sdr104:1; // bit 33\r
UINT32 Ddr50:1; // bit 34\r
- UINT32 Reserved4:1; // bit 35\r
+ UINT32 Reserved3:1; // bit 35\r
UINT32 DriverTypeA:1; // bit 36\r
UINT32 DriverTypeC:1; // bit 37\r
UINT32 DriverTypeD:1; // bit 38\r
UINT32 DriverType4:1; // bit 39\r
UINT32 TimerCount:4; // bit 40:43\r
- UINT32 Reserved5:1; // bit 44\r
+ UINT32 Reserved4:1; // bit 44\r
UINT32 TuningSDR50:1; // bit 45\r
UINT32 RetuningMod:2; // bit 46:47\r
UINT32 ClkMultiplier:8; // bit 48:55\r
- UINT32 Reserved6:7; // bit 56:62\r
+ UINT32 Reserved5:7; // bit 56:62\r
UINT32 Hs400:1; // bit 63\r
} SD_MMC_HC_SLOT_CAP;\r
\r
//\r
// SD Host controller version\r
//\r
-#define SD_MMC_HC_CTRL_VER_100 0x00\r
-#define SD_MMC_HC_CTRL_VER_200 0x01\r
-#define SD_MMC_HC_CTRL_VER_300 0x02\r
-#define SD_MMC_HC_CTRL_VER_400 0x03\r
-#define SD_MMC_HC_CTRL_VER_410 0x04\r
-#define SD_MMC_HC_CTRL_VER_420 0x05\r
+#define SD_MMC_HC_CTRL_VER_100 0x00\r
+#define SD_MMC_HC_CTRL_VER_200 0x01\r
+#define SD_MMC_HC_CTRL_VER_300 0x02\r
+#define SD_MMC_HC_CTRL_VER_400 0x03\r
+#define SD_MMC_HC_CTRL_VER_410 0x04\r
+#define SD_MMC_HC_CTRL_VER_420 0x05\r
+\r
+//\r
+// SD Host controller V4 enhancements\r
+//\r
+#define SD_MMC_HC_V4_EN BIT12\r
+#define SD_MMC_HC_64_ADDR_EN BIT13\r
+#define SD_MMC_HC_26_DATA_LEN_ADMA_EN BIT10\r
\r
/**\r
Dump the content of SD/MMC host controller's Capability Register.\r
IN UINT64 Timeout\r
);\r
\r
+/**\r
+ Get the controller version information from the specified slot.\r
+\r
+ @param[in] PciIo The PCI IO protocol instance.\r
+ @param[in] Slot The slot number of the SD card to send the command to.\r
+ @param[out] Version The buffer to store the version information.\r
+\r
+ @retval EFI_SUCCESS The operation executes successfully.\r
+ @retval Others The operation fails.\r
+\r
+**/\r
+EFI_STATUS\r
+SdMmcHcGetControllerVersion (\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN UINT8 Slot,\r
+ OUT UINT16 *Version\r
+ );\r
+\r
/**\r
Set all interrupt status bits in Normal and Error Interrupt Status Enable\r
register.\r
@param[in] PciIo The PCI IO protocol instance.\r
@param[in] Slot The slot number of the SD card to send the command to.\r
@param[in] ClockFreq The max clock frequency to be set. The unit is KHz.\r
- @param[in] Capability The capability of the slot.\r
+ @param[in] BaseClkFreq The base clock frequency of host controller in MHz.\r
+ @param[in] ControllerVer The version of host controller.\r
\r
@retval EFI_SUCCESS The clock is supplied successfully.\r
@retval Others The clock isn't supplied successfully.\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
IN UINT8 Slot,\r
IN UINT64 ClockFreq,\r
- IN SD_MMC_HC_SLOT_CAP Capability\r
+ IN UINT32 BaseClkFreq,\r
+ IN UINT16 ControllerVer\r
);\r
\r
/**\r
\r
@param[in] PciIo The PCI IO protocol instance.\r
@param[in] Slot The slot number of the SD card to send the command to.\r
- @param[in] Capability The capability of the slot.\r
+ @param[in] BaseClkFreq The base clock frequency of host controller in MHz.\r
+ @param[in] ControllerVer The version of host controller.\r
\r
@retval EFI_SUCCESS The clock is supplied successfully.\r
@retval Others The clock isn't supplied successfully.\r
SdMmcHcInitClockFreq (\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
IN UINT8 Slot,\r
- IN SD_MMC_HC_SLOT_CAP Capability\r
+ IN UINT32 BaseClkFreq,\r
+ IN UINT16 ControllerVer\r
);\r
\r
/**\r
IN SD_MMC_BUS_MODE Timing\r
);\r
\r
+/**\r
+ Set driver strength in host controller.\r
+\r
+ @param[in] PciIo The PCI IO protocol instance.\r
+ @param[in] SlotIndex The slot index of the card.\r
+ @param[in] DriverStrength DriverStrength to set in the controller.\r
+\r
+ @retval EFI_SUCCESS Driver strength programmed successfully.\r
+ @retval Others Failed to set driver strength.\r
+**/\r
+EFI_STATUS\r
+SdMmcSetDriverStrength (\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN UINT8 SlotIndex,\r
+ IN SD_DRIVER_STRENGTH_TYPE DriverStrength\r
+ );\r
+\r
#endif\r
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