MdeModulePkg: Apply uncrustify changes

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / SdMmcPciHcPei / SdMmcPciHcPei.c

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcPei/SdMmcPciHcPei.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcPei/SdMmcPciHcPei.c
index 9c18e6fddc03a27ddfb49a188997e2ed24c309c0..89e0a1b6a416abadff2e25ec5e4e09341b7364bb 100644 (file)
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcPei/SdMmcPciHcPei.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcPei/SdMmcPciHcPei.c
@@ -11,7 +11,7 @@
 \r
 EDKII_SD_MMC_HOST_CONTROLLER_PPI  mSdMmcHostControllerPpi = { GetSdMmcHcMmioBar };\r
 \r
-EFI_PEI_PPI_DESCRIPTOR   mPpiList = {\r
+EFI_PEI_PPI_DESCRIPTOR  mPpiList = {\r
   (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
   &gEdkiiPeiSdMmcHostControllerPpiGuid,\r
   &mSdMmcHostControllerPpi\r
@@ -34,10 +34,10 @@ EFI_PEI_PPI_DESCRIPTOR   mPpiList = {
 EFI_STATUS\r
 EFIAPI\r
 GetSdMmcHcMmioBar (\r
-  IN     EDKII_SD_MMC_HOST_CONTROLLER_PPI *This,\r
-  IN     UINT8                            ControllerId,\r
-  IN OUT UINTN                            **MmioBar,\r
-     OUT UINT8                            *BarNum\r
+  IN     EDKII_SD_MMC_HOST_CONTROLLER_PPI  *This,\r
+  IN     UINT8                             ControllerId,\r
+  IN OUT UINTN                             **MmioBar,\r
+  OUT UINT8                                *BarNum\r
   )\r
 {\r
   SD_MMC_HC_PEI_PRIVATE_DATA  *Private;\r
@@ -70,26 +70,26 @@ GetSdMmcHcMmioBar (
 EFI_STATUS\r
 EFIAPI\r
 InitializeSdMmcHcPeim (\r
-  IN EFI_PEI_FILE_HANDLE       FileHandle,\r
-  IN CONST EFI_PEI_SERVICES    **PeiServices\r
+  IN EFI_PEI_FILE_HANDLE     FileHandle,\r
+  IN CONST EFI_PEI_SERVICES  **PeiServices\r
   )\r
 {\r
-  EFI_BOOT_MODE                BootMode;\r
-  EFI_STATUS                   Status;\r
-  UINT16                       Bus;\r
-  UINT16                       Device;\r
-  UINT16                       Function;\r
-  UINT32                       Size;\r
-  UINT64                       MmioSize;\r
-  UINT8                        SubClass;\r
-  UINT8                        BaseClass;\r
-  UINT8                        SlotInfo;\r
-  UINT8                        SlotNum;\r
-  UINT8                        FirstBar;\r
-  UINT8                        Index;\r
-  UINT8                        Slot;\r
-  UINT32                       BarAddr;\r
-  SD_MMC_HC_PEI_PRIVATE_DATA   *Private;\r
+  EFI_BOOT_MODE               BootMode;\r
+  EFI_STATUS                  Status;\r
+  UINT16                      Bus;\r
+  UINT16                      Device;\r
+  UINT16                      Function;\r
+  UINT32                      Size;\r
+  UINT64                      MmioSize;\r
+  UINT8                       SubClass;\r
+  UINT8                       BaseClass;\r
+  UINT8                       SlotInfo;\r
+  UINT8                       SlotNum;\r
+  UINT8                       FirstBar;\r
+  UINT8                       Index;\r
+  UINT8                       Slot;\r
+  UINT32                      BarAddr;\r
+  SD_MMC_HC_PEI_PRIVATE_DATA  *Private;\r
 \r
   //\r
   // Shadow this PEIM to run from memory\r
@@ -106,7 +106,7 @@ InitializeSdMmcHcPeim (
     return EFI_SUCCESS;\r
   }\r
 \r
-  Private = (SD_MMC_HC_PEI_PRIVATE_DATA *) AllocateZeroPool (sizeof (SD_MMC_HC_PEI_PRIVATE_DATA));\r
+  Private = (SD_MMC_HC_PEI_PRIVATE_DATA *)AllocateZeroPool (sizeof (SD_MMC_HC_PEI_PRIVATE_DATA));\r
   if (Private == NULL) {\r
     DEBUG ((DEBUG_ERROR, "Failed to allocate memory for SD_MMC_HC_PEI_PRIVATE_DATA! \n"));\r
     return EFI_OUT_OF_RESOURCES;\r
@@ -129,15 +129,15 @@ InitializeSdMmcHcPeim (
           // Get the SD/MMC Pci host controller's Slot Info.\r
           //\r
           SlotInfo = PciRead8 (PCI_LIB_ADDRESS (Bus, Device, Function, SD_MMC_HC_PEI_SLOT_OFFSET));\r
-          FirstBar = (*(SD_MMC_HC_PEI_SLOT_INFO*)&SlotInfo).FirstBar;\r
-          SlotNum  = (*(SD_MMC_HC_PEI_SLOT_INFO*)&SlotInfo).SlotNum + 1;\r
+          FirstBar = (*(SD_MMC_HC_PEI_SLOT_INFO *)&SlotInfo).FirstBar;\r
+          SlotNum  = (*(SD_MMC_HC_PEI_SLOT_INFO *)&SlotInfo).SlotNum + 1;\r
           ASSERT ((FirstBar + SlotNum) < MAX_SD_MMC_SLOTS);\r
 \r
           for (Index = 0, Slot = FirstBar; Slot < (FirstBar + SlotNum); Index++, Slot++) {\r
             //\r
             // Get the SD/MMC Pci host controller's MMIO region size.\r
             //\r
-            PciAnd16 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OFFSET), (UINT16)~(EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE));\r
+            PciAnd16 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OFFSET), (UINT16) ~(EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE));\r
             PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4 * Slot), 0xFFFFFFFF);\r
             Size = PciRead32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4 * Slot));\r
 \r
@@ -153,8 +153,8 @@ InitializeSdMmcHcPeim (
                 // Memory space: anywhere in 64 bit address space\r
                 //\r
                 MmioSize = Size & 0xFFFFFFF0;\r
-                PciWrite32 (PCI_LIB_ADDRESS(Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4), 0xFFFFFFFF);\r
-                Size = PciRead32 (PCI_LIB_ADDRESS(Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4));\r
+                PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4), 0xFFFFFFFF);\r
+                Size = PciRead32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4));\r
                 //\r
                 // Fix the length to support some spefic 64 bit BAR\r
                 //\r
@@ -162,7 +162,7 @@ InitializeSdMmcHcPeim (
                 //\r
                 // Calculate the size of 64bit bar\r
                 //\r
-                MmioSize  |= LShiftU64 ((UINT64) Size, 32);\r
+                MmioSize |= LShiftU64 ((UINT64)Size, 32);\r
                 MmioSize  = (~(MmioSize)) + 1;\r
                 //\r
                 // Clean the high 32bits of this 64bit BAR to 0 as we only allow a 32bit BAR.\r
@@ -175,7 +175,8 @@ InitializeSdMmcHcPeim (
                 //\r
                 ASSERT (FALSE);\r
                 continue;\r
-            };\r
+            }\r
+\r
             //\r
             // Assign resource to the SdMmc Pci host controller's MMIO BAR.\r
             // Enable the SdMmc Pci host controller by setting BME and MSE bits of PCI_CMD register.\r
@@ -187,8 +188,9 @@ InitializeSdMmcHcPeim (
             //\r
             Private->MmioBar[Private->TotalSdMmcHcs].SlotNum++;\r
             Private->MmioBar[Private->TotalSdMmcHcs].MmioBarAddr[Index] = BarAddr;\r
-            BarAddr += (UINT32)MmioSize;\r
+            BarAddr                                                    += (UINT32)MmioSize;\r
           }\r
+\r
           Private->TotalSdMmcHcs++;\r
           ASSERT (Private->TotalSdMmcHcs < MAX_SD_MMC_HCS);\r
         }\r