Fix bug: The lower 2 bits of Width and stripped, Count will always be multiplied...

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / UhciDxe / Uhci.h

diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.h b/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.h
index c32b5b7ec8f6044067240dc3195bf57038304d41..71b7a531a1a6efa6afcd55b839435f2ed922434a 100644 (file)
--- a/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.h
+++ b/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.h
@@ -2,8 +2,8 @@
 \r
   The definition for UHCI driver model and HC protocol routines.\r
 \r
-Copyright (c) 2004 - 2007, Intel Corporation\r
-All rights reserved. This program and the accompanying materials\r
+Copyright (c) 2004 - 2010, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
 http://opensource.org/licenses/bsd-license.php\r
@@ -23,6 +23,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #include <Protocol/UsbHostController.h>\r
 #include <Protocol/PciIo.h>\r
 \r
+#include <Guid/EventGroup.h>\r
+\r
 #include <Library/DebugLib.h>\r
 #include <Library/BaseMemoryLib.h>\r
 #include <Library/UefiDriverEntryPoint.h>\r
@@ -32,7 +34,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #include <Library/MemoryAllocationLib.h>\r
 #include <Library/PcdLib.h>\r
 \r
-#include <IndustryStandard/Pci22.h>\r
+#include <IndustryStandard/Pci.h>\r
 \r
 typedef struct _USB_HC_DEV  USB_HC_DEV;\r
 \r
@@ -43,38 +45,39 @@ typedef struct _USB_HC_DEV  USB_HC_DEV;
 #include "UhciDebug.h"\r
 #include "ComponentName.h"\r
 \r
-typedef enum {\r
-  UHC_1_MICROSECOND             = 1,\r
-  UHC_1_MILLISECOND             = 1000 * UHC_1_MICROSECOND,\r
-  UHC_1_SECOND                  = 1000 * UHC_1_MILLISECOND,\r
+//\r
+// UHC timeout experience values\r
+//\r
 \r
-  //\r
-  // UHCI register operation timeout, set by experience\r
-  //\r
-  UHC_GENERIC_TIMEOUT           = UHC_1_SECOND,\r
+#define UHC_1_MICROSECOND             1\r
+#define UHC_1_MILLISECOND             (1000 * UHC_1_MICROSECOND)\r
+#define UHC_1_SECOND                  (1000 * UHC_1_MILLISECOND)\r
 \r
-  //\r
-  // Wait for force global resume(FGR) complete, refers to\r
-  // specification[UHCI11-2.1.1]\r
-  //\r
-  UHC_FORCE_GLOBAL_RESUME_STALL = 20 * UHC_1_MILLISECOND,\r
+//\r
+// UHCI register operation timeout, set by experience\r
+//\r
+#define UHC_GENERIC_TIMEOUT           UHC_1_SECOND\r
 \r
-  //\r
-  // Wait for roothub port reset and recovery, reset stall\r
-  // is set by experience, and recovery stall refers to\r
-  // specification[UHCI11-2.1.1]\r
-  //\r
-  UHC_ROOT_PORT_RESET_STALL     = 50 * UHC_1_MILLISECOND,\r
-  UHC_ROOT_PORT_RECOVERY_STALL  = 10 * UHC_1_MILLISECOND,\r
+//\r
+// Wait for force global resume(FGR) complete, refers to\r
+// specification[UHCI11-2.1.1]\r
+//\r
+#define UHC_FORCE_GLOBAL_RESUME_STALL (20 * UHC_1_MILLISECOND)\r
 \r
-  //\r
-  // Sync and Async transfer polling interval, set by experience,\r
-  // and the unit of Async is 100us.\r
-  //\r
-  UHC_SYNC_POLL_INTERVAL        = 50 * UHC_1_MICROSECOND,\r
-  UHC_ASYNC_POLL_INTERVAL       = 50 * 10000UL\r
-}UHC_TIMEOUT_EXPERIENCE_VALUE;\r
+//\r
+// Wait for roothub port reset and recovery, reset stall\r
+// is set by experience, and recovery stall refers to\r
+// specification[UHCI11-2.1.1]\r
+//\r
+#define UHC_ROOT_PORT_RESET_STALL     (50 * UHC_1_MILLISECOND)\r
+#define UHC_ROOT_PORT_RECOVERY_STALL  (10 * UHC_1_MILLISECOND)\r
 \r
+//\r
+// Sync and Async transfer polling interval, set by experience,\r
+// and the unit of Async is 100us.\r
+//\r
+#define UHC_SYNC_POLL_INTERVAL        (1 * UHC_1_MILLISECOND)\r
+#define UHC_ASYNC_POLL_INTERVAL       (50 * 10000UL)\r
 \r
 //\r
 // UHC raises TPL to TPL_NOTIFY to serialize all its operations\r
@@ -82,11 +85,11 @@ typedef enum {
 //\r
 #define  UHCI_TPL                     TPL_NOTIFY\r
 \r
-#define  USB_HC_DEV_SIGNATURE         EFI_SIGNATURE_32 ('u', 'h', 'c', 'i')\r
+#define  USB_HC_DEV_SIGNATURE         SIGNATURE_32 ('u', 'h', 'c', 'i')\r
 \r
 #pragma pack(1)\r
 typedef struct {\r
-  UINT8               PI;\r
+  UINT8               ProgInterface;\r
   UINT8               SubClassCode;\r
   UINT8               BaseCode;\r
 } USB_CLASSC;\r
@@ -114,7 +117,8 @@ struct _USB_HC_DEV {
   //\r
   // Schedule data structures\r
   //\r
-  UINT32                    *FrameBase;\r
+  UINT32                    *FrameBase; // the buffer pointed by this pointer is used to store pci bus address of the QH descriptor.\r
+  UINT32                    *FrameBaseHostAddr; // the buffer pointed by this pointer is used to store host memory address of the QH descriptor.\r
   UHCI_QH_SW                *SyncIntQh;\r
   UHCI_QH_SW                *CtrlQh;\r
   UHCI_QH_SW                *BulkQh;\r
@@ -137,6 +141,12 @@ struct _USB_HC_DEV {
   USBHC_MEM_POOL            *MemPool;\r
   EFI_UNICODE_STRING_TABLE  *CtrlNameTable;\r
   VOID                      *FrameMapping;\r
+\r
+  //\r
+  // ExitBootServicesEvent is used to stop the EHC DMA operation \r
+  // after exit boot service.\r
+  //\r
+  EFI_EVENT                 ExitBootServiceEvent;\r
 };\r
 \r
 extern EFI_DRIVER_BINDING_PROTOCOL   gUhciDriverBinding;\r