\r
#include "Uhci.h"\r
\r
-\r
/**\r
Read a UHCI register.\r
\r
**/\r
UINT16\r
UhciReadReg (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN UINT32 Offset\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN UINT32 Offset\r
)\r
{\r
UINT16 Data;\r
EFI_STATUS Status;\r
\r
Status = PciIo->Io.Read (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- USB_BAR_INDEX,\r
- Offset,\r
- 1,\r
- &Data\r
- );\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ USB_BAR_INDEX,\r
+ Offset,\r
+ 1,\r
+ &Data\r
+ );\r
\r
if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "UhciReadReg: PciIo Io.Read error: %r at offset %d\n", Status, Offset));\r
return Data;\r
}\r
\r
-\r
/**\r
Write data to UHCI register.\r
\r
**/\r
VOID\r
UhciWriteReg (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN UINT32 Offset,\r
- IN UINT16 Data\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN UINT32 Offset,\r
+ IN UINT16 Data\r
)\r
{\r
EFI_STATUS Status;\r
\r
Status = PciIo->Io.Write (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- USB_BAR_INDEX,\r
- Offset,\r
- 1,\r
- &Data\r
- );\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ USB_BAR_INDEX,\r
+ Offset,\r
+ 1,\r
+ &Data\r
+ );\r
\r
if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "UhciWriteReg: PciIo Io.Write error: %r at offset %d\n", Status, Offset));\r
}\r
}\r
\r
-\r
/**\r
Set a bit of the UHCI Register.\r
\r
**/\r
VOID\r
UhciSetRegBit (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN UINT32 Offset,\r
- IN UINT16 Bit\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN UINT32 Offset,\r
+ IN UINT16 Bit\r
)\r
{\r
UINT16 Data;\r
\r
Data = UhciReadReg (PciIo, Offset);\r
- Data = (UINT16) (Data |Bit);\r
+ Data = (UINT16)(Data |Bit);\r
UhciWriteReg (PciIo, Offset, Data);\r
}\r
\r
-\r
/**\r
Clear a bit of the UHCI Register.\r
\r
**/\r
VOID\r
UhciClearRegBit (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN UINT32 Offset,\r
- IN UINT16 Bit\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN UINT32 Offset,\r
+ IN UINT16 Bit\r
)\r
{\r
UINT16 Data;\r
\r
Data = UhciReadReg (PciIo, Offset);\r
- Data = (UINT16) (Data & ~Bit);\r
+ Data = (UINT16)(Data & ~Bit);\r
UhciWriteReg (PciIo, Offset, Data);\r
}\r
\r
-\r
/**\r
Clear all the interrutp status bits, these bits\r
are Write-Clean.\r
**/\r
VOID\r
UhciAckAllInterrupt (\r
- IN USB_HC_DEV *Uhc\r
+ IN USB_HC_DEV *Uhc\r
)\r
{\r
UhciWriteReg (Uhc->PciIo, USBSTS_OFFSET, 0x3F);\r
}\r
}\r
\r
-\r
/**\r
Stop the host controller.\r
\r
**/\r
EFI_STATUS\r
UhciStopHc (\r
- IN USB_HC_DEV *Uhc,\r
- IN UINTN Timeout\r
+ IN USB_HC_DEV *Uhc,\r
+ IN UINTN Timeout\r
)\r
{\r
- UINT16 UsbSts;\r
- UINTN Index;\r
+ UINT16 UsbSts;\r
+ UINTN Index;\r
\r
UhciClearRegBit (Uhc->PciIo, USBCMD_OFFSET, USBCMD_RS);\r
\r
return EFI_TIMEOUT;\r
}\r
\r
-\r
/**\r
Check whether the host controller operates well.\r
\r
**/\r
BOOLEAN\r
UhciIsHcWorking (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo\r
)\r
{\r
- UINT16 UsbSts;\r
+ UINT16 UsbSts;\r
\r
UsbSts = UhciReadReg (PciIo, USBSTS_OFFSET);\r
\r
return TRUE;\r
}\r
\r
-\r
/**\r
Set the UHCI frame list base address. It can't use\r
UhciWriteReg which access memory in UINT16.\r
**/\r
VOID\r
UhciSetFrameListBaseAddr (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN VOID *Addr\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN VOID *Addr\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT32 Data;\r
+ EFI_STATUS Status;\r
+ UINT32 Data;\r
\r
- Data = (UINT32) ((UINTN) Addr & 0xFFFFF000);\r
+ Data = (UINT32)((UINTN)Addr & 0xFFFFF000);\r
\r
Status = PciIo->Io.Write (\r
PciIo,\r
EfiPciIoWidthUint32,\r
USB_BAR_INDEX,\r
- (UINT64) USB_FRAME_BASE_OFFSET,\r
+ (UINT64)USB_FRAME_BASE_OFFSET,\r
1,\r
&Data\r
);\r
}\r
}\r
\r
-\r
/**\r
Disable USB Emulation.\r
\r
**/\r
VOID\r
UhciTurnOffUsbEmulation (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo\r
)\r
{\r
- UINT16 Command;\r
+ UINT16 Command;\r
\r
Command = 0;\r
\r