// UHCI register offset\r
//\r
\r
-#define UHCI_FRAME_NUM 1024\r
+#define UHCI_FRAME_NUM 1024\r
\r
//\r
// Register offset and PCI related staff\r
//\r
-#define USB_BAR_INDEX 4\r
+#define USB_BAR_INDEX 4\r
\r
-#define USBCMD_OFFSET 0\r
-#define USBSTS_OFFSET 2\r
-#define USBINTR_OFFSET 4\r
-#define USBPORTSC_OFFSET 0x10\r
-#define USB_FRAME_NO_OFFSET 6\r
-#define USB_FRAME_BASE_OFFSET 8\r
-#define USB_EMULATION_OFFSET 0xC0\r
+#define USBCMD_OFFSET 0\r
+#define USBSTS_OFFSET 2\r
+#define USBINTR_OFFSET 4\r
+#define USBPORTSC_OFFSET 0x10\r
+#define USB_FRAME_NO_OFFSET 6\r
+#define USB_FRAME_BASE_OFFSET 8\r
+#define USB_EMULATION_OFFSET 0xC0\r
\r
//\r
// Packet IDs\r
//\r
-#define SETUP_PACKET_ID 0x2D\r
-#define INPUT_PACKET_ID 0x69\r
-#define OUTPUT_PACKET_ID 0xE1\r
-#define ERROR_PACKET_ID 0x55\r
+#define SETUP_PACKET_ID 0x2D\r
+#define INPUT_PACKET_ID 0x69\r
+#define OUTPUT_PACKET_ID 0xE1\r
+#define ERROR_PACKET_ID 0x55\r
\r
//\r
// USB port status and control bit definition.\r
//\r
-#define USBPORTSC_CCS BIT0 // Current Connect Status\r
-#define USBPORTSC_CSC BIT1 // Connect Status Change\r
-#define USBPORTSC_PED BIT2 // Port Enable / Disable\r
-#define USBPORTSC_PEDC BIT3 // Port Enable / Disable Change\r
-#define USBPORTSC_LSL BIT4 // Line Status Low BIT\r
-#define USBPORTSC_LSH BIT5 // Line Status High BIT\r
-#define USBPORTSC_RD BIT6 // Resume Detect\r
-#define USBPORTSC_LSDA BIT8 // Low Speed Device Attached\r
-#define USBPORTSC_PR BIT9 // Port Reset\r
-#define USBPORTSC_SUSP BIT12 // Suspend\r
+#define USBPORTSC_CCS BIT0 // Current Connect Status\r
+#define USBPORTSC_CSC BIT1 // Connect Status Change\r
+#define USBPORTSC_PED BIT2 // Port Enable / Disable\r
+#define USBPORTSC_PEDC BIT3 // Port Enable / Disable Change\r
+#define USBPORTSC_LSL BIT4 // Line Status Low BIT\r
+#define USBPORTSC_LSH BIT5 // Line Status High BIT\r
+#define USBPORTSC_RD BIT6 // Resume Detect\r
+#define USBPORTSC_LSDA BIT8 // Low Speed Device Attached\r
+#define USBPORTSC_PR BIT9 // Port Reset\r
+#define USBPORTSC_SUSP BIT12 // Suspend\r
\r
//\r
// UHCI Spec said it must implement 2 ports each host at least,\r
//\r
// Command register bit definitions\r
//\r
-#define USBCMD_RS BIT0 // Run/Stop\r
-#define USBCMD_HCRESET BIT1 // Host reset\r
-#define USBCMD_GRESET BIT2 // Global reset\r
-#define USBCMD_EGSM BIT3 // Global Suspend Mode\r
-#define USBCMD_FGR BIT4 // Force Global Resume\r
-#define USBCMD_SWDBG BIT5 // SW Debug mode\r
-#define USBCMD_CF BIT6 // Config Flag (sw only)\r
-#define USBCMD_MAXP BIT7 // Max Packet (0 = 32, 1 = 64)\r
+#define USBCMD_RS BIT0 // Run/Stop\r
+#define USBCMD_HCRESET BIT1 // Host reset\r
+#define USBCMD_GRESET BIT2 // Global reset\r
+#define USBCMD_EGSM BIT3 // Global Suspend Mode\r
+#define USBCMD_FGR BIT4 // Force Global Resume\r
+#define USBCMD_SWDBG BIT5 // SW Debug mode\r
+#define USBCMD_CF BIT6 // Config Flag (sw only)\r
+#define USBCMD_MAXP BIT7 // Max Packet (0 = 32, 1 = 64)\r
\r
//\r
// USB Status register bit definitions\r
//\r
-#define USBSTS_USBINT BIT0 // Interrupt due to IOC\r
-#define USBSTS_ERROR BIT1 // Interrupt due to error\r
-#define USBSTS_RD BIT2 // Resume Detect\r
-#define USBSTS_HSE BIT3 // Host System Error\r
-#define USBSTS_HCPE BIT4 // Host Controller Process Error\r
-#define USBSTS_HCH BIT5 // HC Halted\r
-\r
-#define USBTD_ACTIVE BIT7 // TD is still active\r
-#define USBTD_STALLED BIT6 // TD is stalled\r
-#define USBTD_BUFFERR BIT5 // Buffer underflow or overflow\r
-#define USBTD_BABBLE BIT4 // Babble condition\r
-#define USBTD_NAK BIT3 // NAK is received\r
-#define USBTD_CRC BIT2 // CRC/Time out error\r
-#define USBTD_BITSTUFF BIT1 // Bit stuff error\r
-\r
+#define USBSTS_USBINT BIT0 // Interrupt due to IOC\r
+#define USBSTS_ERROR BIT1 // Interrupt due to error\r
+#define USBSTS_RD BIT2 // Resume Detect\r
+#define USBSTS_HSE BIT3 // Host System Error\r
+#define USBSTS_HCPE BIT4 // Host Controller Process Error\r
+#define USBSTS_HCH BIT5 // HC Halted\r
+\r
+#define USBTD_ACTIVE BIT7 // TD is still active\r
+#define USBTD_STALLED BIT6 // TD is stalled\r
+#define USBTD_BUFFERR BIT5 // Buffer underflow or overflow\r
+#define USBTD_BABBLE BIT4 // Babble condition\r
+#define USBTD_NAK BIT3 // NAK is received\r
+#define USBTD_CRC BIT2 // CRC/Time out error\r
+#define USBTD_BITSTUFF BIT1 // Bit stuff error\r
\r
/**\r
Read a UHCI register.\r
**/\r
UINT16\r
UhciReadReg (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN UINT32 Offset\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN UINT32 Offset\r
);\r
\r
-\r
-\r
/**\r
Write data to UHCI register.\r
\r
**/\r
VOID\r
UhciWriteReg (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN UINT32 Offset,\r
- IN UINT16 Data\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN UINT32 Offset,\r
+ IN UINT16 Data\r
);\r
\r
-\r
-\r
/**\r
Set a bit of the UHCI Register.\r
\r
**/\r
VOID\r
UhciSetRegBit (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN UINT32 Offset,\r
- IN UINT16 Bit\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN UINT32 Offset,\r
+ IN UINT16 Bit\r
);\r
\r
-\r
-\r
/**\r
Clear a bit of the UHCI Register.\r
\r
**/\r
VOID\r
UhciClearRegBit (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN UINT32 Offset,\r
- IN UINT16 Bit\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN UINT32 Offset,\r
+ IN UINT16 Bit\r
);\r
\r
-\r
/**\r
Clear all the interrutp status bits, these bits\r
are Write-Clean.\r
**/\r
VOID\r
UhciAckAllInterrupt (\r
- IN USB_HC_DEV *Uhc\r
+ IN USB_HC_DEV *Uhc\r
);\r
\r
-\r
/**\r
Stop the host controller.\r
\r
**/\r
EFI_STATUS\r
UhciStopHc (\r
- IN USB_HC_DEV *Uhc,\r
- IN UINTN Timeout\r
+ IN USB_HC_DEV *Uhc,\r
+ IN UINTN Timeout\r
);\r
\r
-\r
-\r
/**\r
Check whether the host controller operates well.\r
\r
**/\r
BOOLEAN\r
UhciIsHcWorking (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo\r
);\r
\r
-\r
/**\r
Set the UHCI frame list base address. It can't use\r
UhciWriteReg which access memory in UINT16.\r
**/\r
VOID\r
UhciSetFrameListBaseAddr (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN VOID *Addr\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN VOID *Addr\r
);\r
\r
-\r
/**\r
Disable USB Emulation.\r
\r
**/\r
VOID\r
UhciTurnOffUsbEmulation (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo\r
);\r
+\r
#endif\r