/** @file\r
\r
-Copyright (c) 2007 - 2008, Intel Corporation\r
-All rights reserved. This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution. The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
-\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-Module Name:\r
-\r
- UhciReg.h\r
-\r
-Abstract:\r
-\r
The definition for UHCI register operation routines.\r
\r
-Revision History\r
-\r
+Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef _EFI_UHCI_REG_H_\r
#define _EFI_UHCI_REG_H_\r
\r
-#define BIT(a) (1 << (a))\r
-\r
-enum {\r
- UHCI_FRAME_NUM = 1024,\r
-\r
- //\r
- // Register offset and PCI related staff\r
- //\r
- CLASSC_OFFSET = 0x09,\r
- USBBASE_OFFSET = 0x20,\r
- USB_BAR_INDEX = 4,\r
- PCI_CLASSC_PI_UHCI = 0x00,\r
-\r
- USBCMD_OFFSET = 0,\r
- USBSTS_OFFSET = 2,\r
- USBINTR_OFFSET = 4,\r
- USBPORTSC_OFFSET = 0x10,\r
- USB_FRAME_NO_OFFSET = 6,\r
- USB_FRAME_BASE_OFFSET = 8,\r
- USB_EMULATION_OFFSET = 0xC0,\r
-\r
- //\r
- // Packet IDs\r
- //\r
- SETUP_PACKET_ID = 0x2D,\r
- INPUT_PACKET_ID = 0x69,\r
- OUTPUT_PACKET_ID = 0xE1,\r
- ERROR_PACKET_ID = 0x55,\r
-\r
- //\r
- // USB port status and control bit definition.\r
- //\r
- USBPORTSC_CCS = BIT(0), // Current Connect Status\r
- USBPORTSC_CSC = BIT(1), // Connect Status Change\r
- USBPORTSC_PED = BIT(2), // Port Enable / Disable\r
- USBPORTSC_PEDC = BIT(3), // Port Enable / Disable Change\r
- USBPORTSC_LSL = BIT(4), // Line Status Low BIT\r
- USBPORTSC_LSH = BIT(5), // Line Status High BIT\r
- USBPORTSC_RD = BIT(6), // Resume Detect\r
- USBPORTSC_LSDA = BIT(8), // Low Speed Device Attached\r
- USBPORTSC_PR = BIT(9), // Port Reset\r
- USBPORTSC_SUSP = BIT(12), // Suspend\r
-\r
- //\r
- // UHCI Spec said it must implement 2 ports each host at least,\r
- // and if more, check whether the bit7 of PORTSC is always 1.\r
- // So here assume the max of port number each host is 16.\r
- //\r
- USB_MAX_ROOTHUB_PORT = 0x0F,\r
- \r
- //\r
- // Command register bit definitions\r
- //\r
- USBCMD_RS = BIT(0), // Run/Stop\r
- USBCMD_HCRESET = BIT(1), // Host reset\r
- USBCMD_GRESET = BIT(2), // Global reset\r
- USBCMD_EGSM = BIT(3), // Global Suspend Mode\r
- USBCMD_FGR = BIT(4), // Force Global Resume\r
- USBCMD_SWDBG = BIT(5), // SW Debug mode\r
- USBCMD_CF = BIT(6), // Config Flag (sw only)\r
- USBCMD_MAXP = BIT(7), // Max Packet (0 = 32, 1 = 64)\r
-\r
- //\r
- // USB Status register bit definitions\r
- //\r
- USBSTS_USBINT = BIT(0), // Interrupt due to IOC\r
- USBSTS_ERROR = BIT(1), // Interrupt due to error\r
- USBSTS_RD = BIT(2), // Resume Detect\r
- USBSTS_HSE = BIT(3), // Host System Error\r
- USBSTS_HCPE = BIT(4), // Host Controller Process Error\r
- USBSTS_HCH = BIT(5), // HC Halted\r
-\r
- USBTD_ACTIVE = BIT(7), // TD is still active\r
- USBTD_STALLED = BIT(6), // TD is stalled\r
- USBTD_BUFFERR = BIT(5), // Buffer underflow or overflow\r
- USBTD_BABBLE = BIT(4), // Babble condition\r
- USBTD_NAK = BIT(3), // NAK is received\r
- USBTD_CRC = BIT(2), // CRC/Time out error\r
- USBTD_BITSTUFF = BIT(1) // Bit stuff error\r
-};\r
+//\r
+// UHCI register offset\r
+//\r
+\r
+#define UHCI_FRAME_NUM 1024\r
+\r
+//\r
+// Register offset and PCI related staff\r
+//\r
+#define USB_BAR_INDEX 4\r
+\r
+#define USBCMD_OFFSET 0\r
+#define USBSTS_OFFSET 2\r
+#define USBINTR_OFFSET 4\r
+#define USBPORTSC_OFFSET 0x10\r
+#define USB_FRAME_NO_OFFSET 6\r
+#define USB_FRAME_BASE_OFFSET 8\r
+#define USB_EMULATION_OFFSET 0xC0\r
+\r
+//\r
+// Packet IDs\r
+//\r
+#define SETUP_PACKET_ID 0x2D\r
+#define INPUT_PACKET_ID 0x69\r
+#define OUTPUT_PACKET_ID 0xE1\r
+#define ERROR_PACKET_ID 0x55\r
+\r
+//\r
+// USB port status and control bit definition.\r
+//\r
+#define USBPORTSC_CCS BIT0 // Current Connect Status\r
+#define USBPORTSC_CSC BIT1 // Connect Status Change\r
+#define USBPORTSC_PED BIT2 // Port Enable / Disable\r
+#define USBPORTSC_PEDC BIT3 // Port Enable / Disable Change\r
+#define USBPORTSC_LSL BIT4 // Line Status Low BIT\r
+#define USBPORTSC_LSH BIT5 // Line Status High BIT\r
+#define USBPORTSC_RD BIT6 // Resume Detect\r
+#define USBPORTSC_LSDA BIT8 // Low Speed Device Attached\r
+#define USBPORTSC_PR BIT9 // Port Reset\r
+#define USBPORTSC_SUSP BIT12 // Suspend\r
+\r
+//\r
+// UHCI Spec said it must implement 2 ports each host at least,\r
+// and if more, check whether the bit7 of PORTSC is always 1.\r
+// So here assume the max of port number each host is 16.\r
+//\r
+#define USB_MAX_ROOTHUB_PORT 0x0F\r
+\r
+//\r
+// Command register bit definitions\r
+//\r
+#define USBCMD_RS BIT0 // Run/Stop\r
+#define USBCMD_HCRESET BIT1 // Host reset\r
+#define USBCMD_GRESET BIT2 // Global reset\r
+#define USBCMD_EGSM BIT3 // Global Suspend Mode\r
+#define USBCMD_FGR BIT4 // Force Global Resume\r
+#define USBCMD_SWDBG BIT5 // SW Debug mode\r
+#define USBCMD_CF BIT6 // Config Flag (sw only)\r
+#define USBCMD_MAXP BIT7 // Max Packet (0 = 32, 1 = 64)\r
+\r
+//\r
+// USB Status register bit definitions\r
+//\r
+#define USBSTS_USBINT BIT0 // Interrupt due to IOC\r
+#define USBSTS_ERROR BIT1 // Interrupt due to error\r
+#define USBSTS_RD BIT2 // Resume Detect\r
+#define USBSTS_HSE BIT3 // Host System Error\r
+#define USBSTS_HCPE BIT4 // Host Controller Process Error\r
+#define USBSTS_HCH BIT5 // HC Halted\r
+\r
+#define USBTD_ACTIVE BIT7 // TD is still active\r
+#define USBTD_STALLED BIT6 // TD is stalled\r
+#define USBTD_BUFFERR BIT5 // Buffer underflow or overflow\r
+#define USBTD_BABBLE BIT4 // Babble condition\r
+#define USBTD_NAK BIT3 // NAK is received\r
+#define USBTD_CRC BIT2 // CRC/Time out error\r
+#define USBTD_BITSTUFF BIT1 // Bit stuff error\r
\r
\r
/**\r
- Read a UHCI register\r
+ Read a UHCI register.\r
\r
- @param PciIo The EFI_PCI_IO_PROTOCOL to use\r
- @param Offset Register offset to USB_BAR_INDEX\r
+ @param PciIo The EFI_PCI_IO_PROTOCOL to use.\r
+ @param Offset Register offset to USB_BAR_INDEX.\r
\r
- @return Content of register\r
+ @return Content of register.\r
\r
**/\r
UINT16\r
UhciReadReg (\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
IN UINT32 Offset\r
- )\r
-;\r
+ );\r
\r
\r
\r
/**\r
- Write data to UHCI register\r
+ Write data to UHCI register.\r
\r
- @param PciIo The EFI_PCI_IO_PROTOCOL to use\r
- @param Offset Register offset to USB_BAR_INDEX\r
- @param Data Data to write\r
+ @param PciIo The EFI_PCI_IO_PROTOCOL to use.\r
+ @param Offset Register offset to USB_BAR_INDEX.\r
+ @param Data Data to write.\r
\r
- @return VOID\r
+ @return None.\r
\r
**/\r
VOID\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
IN UINT32 Offset,\r
IN UINT16 Data\r
- )\r
-;\r
+ );\r
\r
\r
\r
/**\r
- Set a bit of the UHCI Register\r
+ Set a bit of the UHCI Register.\r
\r
- @param PciIo The EFI_PCI_IO_PROTOCOL to use\r
- @param Offset Register offset to USB_BAR_INDEX\r
- @param Bit The bit to set\r
+ @param PciIo The EFI_PCI_IO_PROTOCOL to use.\r
+ @param Offset Register offset to USB_BAR_INDEX.\r
+ @param Bit The bit to set.\r
\r
- @return None\r
+ @return None.\r
\r
**/\r
VOID\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
IN UINT32 Offset,\r
IN UINT16 Bit\r
- )\r
-;\r
+ );\r
\r
\r
\r
/**\r
- Clear a bit of the UHCI Register\r
+ Clear a bit of the UHCI Register.\r
\r
- @param PciIo The PCI_IO protocol to access the PCI\r
- @param Offset Register offset to USB_BAR_INDEX\r
- @param Bit The bit to clear\r
+ @param PciIo The PCI_IO protocol to access the PCI.\r
+ @param Offset Register offset to USB_BAR_INDEX.\r
+ @param Bit The bit to clear.\r
\r
- @return None\r
+ @return None.\r
\r
**/\r
VOID\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
IN UINT32 Offset,\r
IN UINT16 Bit\r
- )\r
-;\r
+ );\r
\r
\r
/**\r
Clear all the interrutp status bits, these bits\r
- are Write-Clean\r
+ are Write-Clean.\r
\r
- @param Uhc The UHCI device\r
+ @param Uhc The UHCI device.\r
\r
- @return None\r
+ @return None.\r
\r
**/\r
VOID\r
UhciAckAllInterrupt (\r
IN USB_HC_DEV *Uhc\r
- )\r
-;\r
+ );\r
\r
\r
/**\r
- Stop the host controller\r
+ Stop the host controller.\r
\r
- @param Uhc The UHCI device\r
- @param Timeout Max time allowed\r
+ @param Uhc The UHCI device.\r
+ @param Timeout Max time allowed.\r
\r
- @retval EFI_SUCCESS The host controller is stopped\r
- @retval EFI_TIMEOUT Failed to stop the host controller\r
+ @retval EFI_SUCCESS The host controller is stopped.\r
+ @retval EFI_TIMEOUT Failed to stop the host controller.\r
\r
**/\r
EFI_STATUS\r
UhciStopHc (\r
IN USB_HC_DEV *Uhc,\r
IN UINTN Timeout\r
- )\r
-;\r
+ );\r
\r
\r
\r
/**\r
- Check whether the host controller operates well\r
+ Check whether the host controller operates well.\r
\r
- @param PciIo The PCI_IO protocol to use\r
+ @param PciIo The PCI_IO protocol to use.\r
\r
- @retval TRUE Host controller is working\r
- @retval FALSE Host controller is halted or system error\r
+ @retval TRUE Host controller is working.\r
+ @retval FALSE Host controller is halted or system error.\r
\r
**/\r
BOOLEAN\r
UhciIsHcWorking (\r
IN EFI_PCI_IO_PROTOCOL *PciIo\r
- )\r
-;\r
+ );\r
\r
\r
/**\r
Set the UHCI frame list base address. It can't use\r
UhciWriteReg which access memory in UINT16.\r
\r
- @param PciIo The EFI_PCI_IO_PROTOCOL to use\r
- @param Addr Address to set\r
+ @param PciIo The EFI_PCI_IO_PROTOCOL to use.\r
+ @param Addr Address to set.\r
\r
- @return VOID\r
+ @return None.\r
\r
**/\r
VOID\r
UhciSetFrameListBaseAddr (\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
IN VOID *Addr\r
- )\r
-;\r
+ );\r
\r
\r
/**\r
- Disable USB Emulation\r
+ Disable USB Emulation.\r
\r
- @param PciIo The EFI_PCI_IO_PROTOCOL protocol to use\r
+ @param PciIo The EFI_PCI_IO_PROTOCOL protocol to use.\r
\r
- @return VOID\r
+ @return None.\r
\r
**/\r
VOID\r
UhciTurnOffUsbEmulation (\r
IN EFI_PCI_IO_PROTOCOL *PciIo\r
- )\r
-;\r
+ );\r
#endif\r
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