MdeModulePkg/Usb: Make sure data from HW is no more than expected

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / UhciDxe / UhciSched.c

diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c b/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c
index 90f010c9985ba0d9b8559f889be9e94d60529135..f7510f3ec0ebd8ad868c836de54090121fdb101d 100644 (file)
--- a/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c
+++ b/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c
@@ -2,7 +2,7 @@
 \r
   The EHCI register operation routines.\r
 \r
-Copyright (c) 2007 - 2013, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -1001,11 +1001,12 @@ UhciMonitorAsyncReqList (
 \r
     //\r
     // Copy the data to temporary buffer if there are some\r
-    // data transferred. We may have zero-length packet\r
+    // data transferred. We may have zero-length packet.\r
+    // Make sure the data received from HW is no more than expected.\r
     //\r
     Data = NULL;\r
 \r
-    if (QhResult.Complete != 0) {\r
+    if ((QhResult.Complete != 0) && (QhResult.Complete <= AsyncReq->DataLen)) {\r
       Data = AllocatePool (QhResult.Complete);\r
 \r
       if (Data == NULL) {\r