**/\r
EFI_STATUS\r
UhciStopHc (\r
- IN USB_UHC_DEV *Uhc,\r
- IN UINTN Timeout\r
+ IN USB_UHC_DEV *Uhc,\r
+ IN UINTN Timeout\r
)\r
{\r
- UINT16 CommandContent;\r
- UINT16 UsbSts;\r
- UINTN Index;\r
+ UINT16 CommandContent;\r
+ UINT16 UsbSts;\r
+ UINTN Index;\r
\r
- CommandContent = USBReadPortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBCMD);\r
+ CommandContent = USBReadPortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBCMD);\r
CommandContent &= USBCMD_RS;\r
USBWritePortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBCMD, CommandContent);\r
\r
IN VOID *Ppi\r
)\r
{\r
- USB_UHC_DEV *Uhc;\r
+ USB_UHC_DEV *Uhc;\r
\r
Uhc = PEI_RECOVERY_USB_UHC_DEV_FROM_THIS_NOTIFY (NotifyDescriptor);\r
\r
EFI_STATUS\r
EFIAPI\r
UhcPeimEntry (\r
- IN EFI_PEI_FILE_HANDLE FileHandle,\r
- IN CONST EFI_PEI_SERVICES **PeiServices\r
+ IN EFI_PEI_FILE_HANDLE FileHandle,\r
+ IN CONST EFI_PEI_SERVICES **PeiServices\r
)\r
{\r
- PEI_USB_CONTROLLER_PPI *ChipSetUsbControllerPpi;\r
- EFI_STATUS Status;\r
- UINT8 Index;\r
- UINTN ControllerType;\r
- UINTN BaseAddress;\r
- UINTN MemPages;\r
- USB_UHC_DEV *UhcDev;\r
- EFI_PHYSICAL_ADDRESS TempPtr;\r
+ PEI_USB_CONTROLLER_PPI *ChipSetUsbControllerPpi;\r
+ EFI_STATUS Status;\r
+ UINT8 Index;\r
+ UINTN ControllerType;\r
+ UINTN BaseAddress;\r
+ UINTN MemPages;\r
+ USB_UHC_DEV *UhcDev;\r
+ EFI_PHYSICAL_ADDRESS TempPtr;\r
\r
//\r
// Shadow this PEIM to run from memory\r
&gPeiUsbControllerPpiGuid,\r
0,\r
NULL,\r
- (VOID **) &ChipSetUsbControllerPpi\r
+ (VOID **)&ChipSetUsbControllerPpi\r
);\r
//\r
// If failed to locate, it is a bug in dispather as depex has gPeiUsbControllerPpiGuid.\r
Index = 0;\r
while (TRUE) {\r
Status = ChipSetUsbControllerPpi->GetUsbController (\r
- (EFI_PEI_SERVICES **) PeiServices,\r
+ (EFI_PEI_SERVICES **)PeiServices,\r
ChipSetUsbControllerPpi,\r
Index,\r
&ControllerType,\r
return EFI_OUT_OF_RESOURCES;\r
}\r
\r
- UhcDev = (USB_UHC_DEV *) ((UINTN) TempPtr);\r
- UhcDev->Signature = USB_UHC_DEV_SIGNATURE;\r
+ UhcDev = (USB_UHC_DEV *)((UINTN)TempPtr);\r
+ UhcDev->Signature = USB_UHC_DEV_SIGNATURE;\r
IoMmuInit (&UhcDev->IoMmu);\r
- UhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress;\r
+ UhcDev->UsbHostControllerBaseAddress = (UINT32)BaseAddress;\r
\r
//\r
// Init local memory management service\r
return Status;\r
}\r
\r
- UhcDev->UsbHostControllerPpi.ControlTransfer = UhcControlTransfer;\r
- UhcDev->UsbHostControllerPpi.BulkTransfer = UhcBulkTransfer;\r
- UhcDev->UsbHostControllerPpi.GetRootHubPortNumber = UhcGetRootHubPortNumber;\r
- UhcDev->UsbHostControllerPpi.GetRootHubPortStatus = UhcGetRootHubPortStatus;\r
- UhcDev->UsbHostControllerPpi.SetRootHubPortFeature = UhcSetRootHubPortFeature;\r
- UhcDev->UsbHostControllerPpi.ClearRootHubPortFeature = UhcClearRootHubPortFeature;\r
+ UhcDev->UsbHostControllerPpi.ControlTransfer = UhcControlTransfer;\r
+ UhcDev->UsbHostControllerPpi.BulkTransfer = UhcBulkTransfer;\r
+ UhcDev->UsbHostControllerPpi.GetRootHubPortNumber = UhcGetRootHubPortNumber;\r
+ UhcDev->UsbHostControllerPpi.GetRootHubPortStatus = UhcGetRootHubPortStatus;\r
+ UhcDev->UsbHostControllerPpi.SetRootHubPortFeature = UhcSetRootHubPortFeature;\r
+ UhcDev->UsbHostControllerPpi.ClearRootHubPortFeature = UhcClearRootHubPortFeature;\r
\r
UhcDev->PpiDescriptor.Flags = (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);\r
UhcDev->PpiDescriptor.Guid = &gPeiUsbHostControllerPpiGuid;\r
continue;\r
}\r
\r
- UhcDev->EndOfPeiNotifyList.Flags = (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);\r
- UhcDev->EndOfPeiNotifyList.Guid = &gEfiEndOfPeiSignalPpiGuid;\r
+ UhcDev->EndOfPeiNotifyList.Flags = (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);\r
+ UhcDev->EndOfPeiNotifyList.Guid = &gEfiEndOfPeiSignalPpiGuid;\r
UhcDev->EndOfPeiNotifyList.Notify = UhcEndOfPei;\r
\r
PeiServicesNotifyPpi (&UhcDev->EndOfPeiNotifyList);\r
EFI_STATUS\r
EFIAPI\r
UhcControlTransfer (\r
- IN EFI_PEI_SERVICES **PeiServices,\r
- IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
- IN UINT8 DeviceAddress,\r
- IN UINT8 DeviceSpeed,\r
- IN UINT8 MaximumPacketLength,\r
- IN EFI_USB_DEVICE_REQUEST *Request,\r
- IN EFI_USB_DATA_DIRECTION TransferDirection,\r
- IN OUT VOID *Data OPTIONAL,\r
- IN OUT UINTN *DataLength OPTIONAL,\r
- IN UINTN TimeOut,\r
- OUT UINT32 *TransferResult\r
- )\r
-{\r
- USB_UHC_DEV *UhcDev;\r
- UINT32 StatusReg;\r
- UINT8 PktID;\r
- QH_STRUCT *PtrQH;\r
- TD_STRUCT *PtrTD;\r
- TD_STRUCT *PtrPreTD;\r
- TD_STRUCT *PtrSetupTD;\r
- TD_STRUCT *PtrStatusTD;\r
- EFI_STATUS Status;\r
- UINT32 DataLen;\r
- UINT8 DataToggle;\r
- UINT8 *RequestPhy;\r
- VOID *RequestMap;\r
- UINT8 *DataPhy;\r
- VOID *DataMap;\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
+ IN UINT8 DeviceAddress,\r
+ IN UINT8 DeviceSpeed,\r
+ IN UINT8 MaximumPacketLength,\r
+ IN EFI_USB_DEVICE_REQUEST *Request,\r
+ IN EFI_USB_DATA_DIRECTION TransferDirection,\r
+ IN OUT VOID *Data OPTIONAL,\r
+ IN OUT UINTN *DataLength OPTIONAL,\r
+ IN UINTN TimeOut,\r
+ OUT UINT32 *TransferResult\r
+ )\r
+{\r
+ USB_UHC_DEV *UhcDev;\r
+ UINT32 StatusReg;\r
+ UINT8 PktID;\r
+ QH_STRUCT *PtrQH;\r
+ TD_STRUCT *PtrTD;\r
+ TD_STRUCT *PtrPreTD;\r
+ TD_STRUCT *PtrSetupTD;\r
+ TD_STRUCT *PtrStatusTD;\r
+ EFI_STATUS Status;\r
+ UINT32 DataLen;\r
+ UINT8 DataToggle;\r
+ UINT8 *RequestPhy;\r
+ VOID *RequestMap;\r
+ UINT8 *DataPhy;\r
+ VOID *DataMap;\r
\r
- UhcDev = PEI_RECOVERY_USB_UHC_DEV_FROM_UHCI_THIS (This);\r
+ UhcDev = PEI_RECOVERY_USB_UHC_DEV_FROM_UHCI_THIS (This);\r
\r
- StatusReg = UhcDev->UsbHostControllerBaseAddress + USBSTS;\r
+ StatusReg = UhcDev->UsbHostControllerBaseAddress + USBSTS;\r
\r
- PktID = INPUT_PACKET_ID;\r
+ PktID = INPUT_PACKET_ID;\r
\r
- RequestMap = NULL;\r
+ RequestMap = NULL;\r
\r
- if (Request == NULL || TransferResult == NULL) {\r
+ if ((Request == NULL) || (TransferResult == NULL)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
+\r
//\r
// if errors exist that cause host controller halt,\r
// then return EFI_DEVICE_ERROR.\r
if (RequestMap != NULL) {\r
IoMmuUnmap (UhcDev->IoMmu, RequestMap);\r
}\r
+\r
return Status;\r
}\r
\r
DeviceAddress,\r
0,\r
DeviceSpeed,\r
- (UINT8 *) Request,\r
+ (UINT8 *)Request,\r
RequestPhy,\r
- (UINT8) sizeof (EFI_USB_DEVICE_REQUEST),\r
+ (UINT8)sizeof (EFI_USB_DEVICE_REQUEST),\r
&PtrSetupTD\r
);\r
\r
if (TransferDirection == EfiUsbNoData) {\r
DataLen = 0;\r
} else {\r
- DataLen = (UINT32) *DataLength;\r
+ DataLen = (UINT32)*DataLength;\r
}\r
\r
- DataToggle = 1;\r
+ DataToggle = 1;\r
\r
- PtrTD = PtrSetupTD;\r
+ PtrTD = PtrSetupTD;\r
while (DataLen > 0) {\r
//\r
// create TD structures and link together\r
//\r
- UINT8 PacketSize;\r
+ UINT8 PacketSize;\r
\r
//\r
// PacketSize is the data load size of each TD carries.\r
//\r
- PacketSize = (UINT8) DataLen;\r
+ PacketSize = (UINT8)DataLen;\r
if (DataLen > MaximumPacketLength) {\r
PacketSize = MaximumPacketLength;\r
}\r
PtrPreTD = PtrTD;\r
\r
DataToggle ^= 1;\r
- Data = (VOID *) ((UINT8 *) Data + PacketSize);\r
- DataPhy += PacketSize;\r
- DataLen -= PacketSize;\r
+ Data = (VOID *)((UINT8 *)Data + PacketSize);\r
+ DataPhy += PacketSize;\r
+ DataLen -= PacketSize;\r
}\r
\r
//\r
} else {\r
PktID = OUTPUT_PACKET_ID;\r
}\r
+\r
//\r
// create Status Stage TD structure\r
//\r
// detail status is returned\r
//\r
Status = ExecuteControlTransfer (\r
- UhcDev,\r
- PtrSetupTD,\r
- DataLength,\r
- TimeOut,\r
- TransferResult\r
- );\r
+ UhcDev,\r
+ PtrSetupTD,\r
+ DataLength,\r
+ TimeOut,\r
+ TransferResult\r
+ );\r
\r
//\r
// TRUE means must search other framelistindex\r
//\r
- SetQHVerticalValidorInvalid(PtrQH, FALSE);\r
+ SetQHVerticalValidorInvalid (PtrQH, FALSE);\r
DeleteQueuedTDs (UhcDev, PtrSetupTD);\r
\r
//\r
//\r
if (!IsStatusOK (UhcDev, StatusReg)) {\r
*TransferResult |= EFI_USB_ERR_SYSTEM;\r
- Status = EFI_DEVICE_ERROR;\r
+ Status = EFI_DEVICE_ERROR;\r
}\r
\r
ClearStatusReg (UhcDev, StatusReg);\r
if (DataMap != NULL) {\r
IoMmuUnmap (UhcDev->IoMmu, DataMap);\r
}\r
+\r
if (RequestMap != NULL) {\r
IoMmuUnmap (UhcDev->IoMmu, RequestMap);\r
}\r
EFI_STATUS\r
EFIAPI\r
UhcBulkTransfer (\r
- IN EFI_PEI_SERVICES **PeiServices,\r
- IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
- IN UINT8 DeviceAddress,\r
- IN UINT8 EndPointAddress,\r
- IN UINT8 MaximumPacketLength,\r
- IN OUT VOID *Data,\r
- IN OUT UINTN *DataLength,\r
- IN OUT UINT8 *DataToggle,\r
- IN UINTN TimeOut,\r
- OUT UINT32 *TransferResult\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
+ IN UINT8 DeviceAddress,\r
+ IN UINT8 EndPointAddress,\r
+ IN UINT8 MaximumPacketLength,\r
+ IN OUT VOID *Data,\r
+ IN OUT UINTN *DataLength,\r
+ IN OUT UINT8 *DataToggle,\r
+ IN UINTN TimeOut,\r
+ OUT UINT32 *TransferResult\r
)\r
{\r
- USB_UHC_DEV *UhcDev;\r
- UINT32 StatusReg;\r
+ USB_UHC_DEV *UhcDev;\r
+ UINT32 StatusReg;\r
\r
- UINT32 DataLen;\r
+ UINT32 DataLen;\r
\r
- QH_STRUCT *PtrQH;\r
- TD_STRUCT *PtrFirstTD;\r
- TD_STRUCT *PtrTD;\r
- TD_STRUCT *PtrPreTD;\r
+ QH_STRUCT *PtrQH;\r
+ TD_STRUCT *PtrFirstTD;\r
+ TD_STRUCT *PtrTD;\r
+ TD_STRUCT *PtrPreTD;\r
\r
- UINT8 PktID;\r
+ UINT8 PktID;\r
\r
- BOOLEAN IsFirstTD;\r
+ BOOLEAN IsFirstTD;\r
\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
EFI_USB_DATA_DIRECTION TransferDirection;\r
\r
- BOOLEAN ShortPacketEnable;\r
+ BOOLEAN ShortPacketEnable;\r
\r
- UINT16 CommandContent;\r
+ UINT16 CommandContent;\r
\r
- UINT8 *DataPhy;\r
- VOID *DataMap;\r
+ UINT8 *DataPhy;\r
+ VOID *DataMap;\r
\r
UhcDev = PEI_RECOVERY_USB_UHC_DEV_FROM_UHCI_THIS (This);\r
\r
USBWritePortW (UhcDev, UhcDev->UsbHostControllerBaseAddress + USBCMD, CommandContent);\r
}\r
\r
- StatusReg = UhcDev->UsbHostControllerBaseAddress + USBSTS;\r
+ StatusReg = UhcDev->UsbHostControllerBaseAddress + USBSTS;\r
\r
//\r
// these code lines are added here per complier's strict demand\r
//\r
- PktID = INPUT_PACKET_ID;\r
- PtrTD = NULL;\r
- PtrFirstTD = NULL;\r
- PtrPreTD = NULL;\r
- DataLen = 0;\r
+ PktID = INPUT_PACKET_ID;\r
+ PtrTD = NULL;\r
+ PtrFirstTD = NULL;\r
+ PtrPreTD = NULL;\r
+ DataLen = 0;\r
\r
ShortPacketEnable = FALSE;\r
\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- if (MaximumPacketLength != 8 && MaximumPacketLength != 16\r
- && MaximumPacketLength != 32 && MaximumPacketLength != 64) {\r
+ if ( (MaximumPacketLength != 8) && (MaximumPacketLength != 16)\r
+ && (MaximumPacketLength != 32) && (MaximumPacketLength != 64))\r
+ {\r
return EFI_INVALID_PARAMETER;\r
}\r
+\r
//\r
// if has errors that cause host controller halt, then return EFI_DEVICE_ERROR directly.\r
//\r
if (!IsStatusOK (UhcDev, StatusReg)) {\r
-\r
ClearStatusReg (UhcDev, StatusReg);\r
*TransferResult = EFI_USB_ERR_SYSTEM;\r
return EFI_DEVICE_ERROR;\r
return Status;\r
}\r
\r
- DataLen = (UINT32) *DataLength;\r
+ DataLen = (UINT32)*DataLength;\r
\r
PtrQH = UhcDev->BulkQH;\r
\r
//\r
// create TD structures and link together\r
//\r
- UINT8 PacketSize;\r
+ UINT8 PacketSize;\r
\r
- PacketSize = (UINT8) DataLen;\r
+ PacketSize = (UINT8)DataLen;\r
if (DataLen > MaximumPacketLength) {\r
PacketSize = MaximumPacketLength;\r
}\r
PtrPreTD = PtrTD;\r
\r
*DataToggle ^= 1;\r
- Data = (VOID *) ((UINT8 *) Data + PacketSize);\r
- DataPhy += PacketSize;\r
- DataLen -= PacketSize;\r
+ Data = (VOID *)((UINT8 *)Data + PacketSize);\r
+ DataPhy += PacketSize;\r
+ DataLen -= PacketSize;\r
}\r
+\r
//\r
// link TD structures to QH structure\r
//\r
// of the last successful TD\r
//\r
Status = ExecBulkTransfer (\r
- UhcDev,\r
- PtrFirstTD,\r
- DataLength,\r
- DataToggle,\r
- TimeOut,\r
- TransferResult\r
- );\r
+ UhcDev,\r
+ PtrFirstTD,\r
+ DataLength,\r
+ DataToggle,\r
+ TimeOut,\r
+ TransferResult\r
+ );\r
\r
//\r
// Delete Bulk transfer TD structure\r
//\r
if (!IsStatusOK (UhcDev, StatusReg)) {\r
*TransferResult |= EFI_USB_ERR_SYSTEM;\r
- Status = EFI_DEVICE_ERROR;\r
+ Status = EFI_DEVICE_ERROR;\r
}\r
\r
ClearStatusReg (UhcDev, StatusReg);\r
EFI_STATUS\r
EFIAPI\r
UhcGetRootHubPortNumber (\r
- IN EFI_PEI_SERVICES **PeiServices,\r
- IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
- OUT UINT8 *PortNumber\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
+ OUT UINT8 *PortNumber\r
)\r
{\r
- USB_UHC_DEV *UhcDev;\r
- UINT32 PSAddr;\r
- UINT16 RHPortControl;\r
- UINT32 Index;\r
+ USB_UHC_DEV *UhcDev;\r
+ UINT32 PSAddr;\r
+ UINT16 RHPortControl;\r
+ UINT32 Index;\r
\r
UhcDev = PEI_RECOVERY_USB_UHC_DEV_FROM_UHCI_THIS (This);\r
\r
*PortNumber = 0;\r
\r
for (Index = 0; Index < 2; Index++) {\r
- PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + Index * 2;\r
+ PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + Index * 2;\r
RHPortControl = USBReadPortW (UhcDev, PSAddr);\r
//\r
// Port Register content is valid\r
EFI_STATUS\r
EFIAPI\r
UhcGetRootHubPortStatus (\r
- IN EFI_PEI_SERVICES **PeiServices,\r
- IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
- IN UINT8 PortNumber,\r
- OUT EFI_USB_PORT_STATUS *PortStatus\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
+ IN UINT8 PortNumber,\r
+ OUT EFI_USB_PORT_STATUS *PortStatus\r
)\r
{\r
- USB_UHC_DEV *UhcDev;\r
- UINT32 PSAddr;\r
- UINT16 RHPortStatus;\r
- UINT8 TotalPortNumber;\r
+ USB_UHC_DEV *UhcDev;\r
+ UINT32 PSAddr;\r
+ UINT16 RHPortStatus;\r
+ UINT8 TotalPortNumber;\r
\r
if (PortStatus == NULL) {\r
return EFI_INVALID_PARAMETER;\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- UhcDev = PEI_RECOVERY_USB_UHC_DEV_FROM_UHCI_THIS (This);\r
- PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + PortNumber * 2;\r
+ UhcDev = PEI_RECOVERY_USB_UHC_DEV_FROM_UHCI_THIS (This);\r
+ PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + PortNumber * 2;\r
\r
- PortStatus->PortStatus = 0;\r
- PortStatus->PortChangeStatus = 0;\r
+ PortStatus->PortStatus = 0;\r
+ PortStatus->PortChangeStatus = 0;\r
\r
RHPortStatus = USBReadPortW (UhcDev, PSAddr);\r
\r
if ((RHPortStatus & USBPORTSC_CCS) != 0) {\r
PortStatus->PortStatus |= USB_PORT_STAT_CONNECTION;\r
}\r
+\r
//\r
// Port Enabled/Disabled\r
//\r
if ((RHPortStatus & USBPORTSC_PED) != 0) {\r
PortStatus->PortStatus |= USB_PORT_STAT_ENABLE;\r
}\r
+\r
//\r
// Port Suspend\r
//\r
if ((RHPortStatus & USBPORTSC_SUSP) != 0) {\r
PortStatus->PortStatus |= USB_PORT_STAT_SUSPEND;\r
}\r
+\r
//\r
// Port Reset\r
//\r
if ((RHPortStatus & USBPORTSC_PR) != 0) {\r
PortStatus->PortStatus |= USB_PORT_STAT_RESET;\r
}\r
+\r
//\r
// Low Speed Device Attached\r
//\r
if ((RHPortStatus & USBPORTSC_LSDA) != 0) {\r
PortStatus->PortStatus |= USB_PORT_STAT_LOW_SPEED;\r
}\r
+\r
//\r
// Fill Port Status Change bits\r
//\r
if ((RHPortStatus & USBPORTSC_CSC) != 0) {\r
PortStatus->PortChangeStatus |= USB_PORT_STAT_C_CONNECTION;\r
}\r
+\r
//\r
// Port Enabled/Disabled Change\r
//\r
EFI_STATUS\r
EFIAPI\r
UhcSetRootHubPortFeature (\r
- IN EFI_PEI_SERVICES **PeiServices,\r
- IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
- IN UINT8 PortNumber,\r
- IN EFI_USB_PORT_FEATURE PortFeature\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
+ IN UINT8 PortNumber,\r
+ IN EFI_USB_PORT_FEATURE PortFeature\r
)\r
{\r
- USB_UHC_DEV *UhcDev;\r
- UINT32 PSAddr;\r
- UINT32 CommandRegAddr;\r
- UINT16 RHPortControl;\r
- UINT8 TotalPortNumber;\r
+ USB_UHC_DEV *UhcDev;\r
+ UINT32 PSAddr;\r
+ UINT32 CommandRegAddr;\r
+ UINT16 RHPortControl;\r
+ UINT8 TotalPortNumber;\r
\r
UhcGetRootHubPortNumber (PeiServices, This, &TotalPortNumber);\r
if (PortNumber > TotalPortNumber) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- UhcDev = PEI_RECOVERY_USB_UHC_DEV_FROM_UHCI_THIS (This);\r
- PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + PortNumber * 2;\r
- CommandRegAddr = UhcDev->UsbHostControllerBaseAddress + USBCMD;\r
+ UhcDev = PEI_RECOVERY_USB_UHC_DEV_FROM_UHCI_THIS (This);\r
+ PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + PortNumber * 2;\r
+ CommandRegAddr = UhcDev->UsbHostControllerBaseAddress + USBCMD;\r
\r
RHPortControl = USBReadPortW (UhcDev, PSAddr);\r
\r
switch (PortFeature) {\r
+ case EfiUsbPortSuspend:\r
+ if ((USBReadPortW (UhcDev, CommandRegAddr) & USBCMD_EGSM) == 0) {\r
+ //\r
+ // if global suspend is not active, can set port suspend\r
+ //\r
+ RHPortControl &= 0xfff5;\r
+ RHPortControl |= USBPORTSC_SUSP;\r
+ }\r
\r
- case EfiUsbPortSuspend:\r
- if ((USBReadPortW (UhcDev, CommandRegAddr) & USBCMD_EGSM) == 0) {\r
+ break;\r
+\r
+ case EfiUsbPortReset:\r
+ RHPortControl &= 0xfff5;\r
+ RHPortControl |= USBPORTSC_PR;\r
//\r
- // if global suspend is not active, can set port suspend\r
+ // Set the reset bit\r
//\r
- RHPortControl &= 0xfff5;\r
- RHPortControl |= USBPORTSC_SUSP;\r
- }\r
- break;\r
-\r
- case EfiUsbPortReset:\r
- RHPortControl &= 0xfff5;\r
- RHPortControl |= USBPORTSC_PR;\r
- //\r
- // Set the reset bit\r
- //\r
- break;\r
+ break;\r
\r
- case EfiUsbPortPower:\r
- break;\r
+ case EfiUsbPortPower:\r
+ break;\r
\r
- case EfiUsbPortEnable:\r
- RHPortControl &= 0xfff5;\r
- RHPortControl |= USBPORTSC_PED;\r
- break;\r
+ case EfiUsbPortEnable:\r
+ RHPortControl &= 0xfff5;\r
+ RHPortControl |= USBPORTSC_PED;\r
+ break;\r
\r
- default:\r
- return EFI_INVALID_PARAMETER;\r
+ default:\r
+ return EFI_INVALID_PARAMETER;\r
}\r
\r
USBWritePortW (UhcDev, PSAddr, RHPortControl);\r
EFI_STATUS\r
EFIAPI\r
UhcClearRootHubPortFeature (\r
- IN EFI_PEI_SERVICES **PeiServices,\r
- IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
- IN UINT8 PortNumber,\r
- IN EFI_USB_PORT_FEATURE PortFeature\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
+ IN UINT8 PortNumber,\r
+ IN EFI_USB_PORT_FEATURE PortFeature\r
)\r
{\r
- USB_UHC_DEV *UhcDev;\r
- UINT32 PSAddr;\r
- UINT16 RHPortControl;\r
- UINT8 TotalPortNumber;\r
+ USB_UHC_DEV *UhcDev;\r
+ UINT32 PSAddr;\r
+ UINT16 RHPortControl;\r
+ UINT8 TotalPortNumber;\r
\r
UhcGetRootHubPortNumber (PeiServices, This, &TotalPortNumber);\r
\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- UhcDev = PEI_RECOVERY_USB_UHC_DEV_FROM_UHCI_THIS (This);\r
- PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + PortNumber * 2;\r
+ UhcDev = PEI_RECOVERY_USB_UHC_DEV_FROM_UHCI_THIS (This);\r
+ PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + PortNumber * 2;\r
\r
RHPortControl = USBReadPortW (UhcDev, PSAddr);\r
\r
switch (PortFeature) {\r
- //\r
- // clear PORT_ENABLE feature means disable port.\r
- //\r
- case EfiUsbPortEnable:\r
- RHPortControl &= 0xfff5;\r
- RHPortControl &= ~USBPORTSC_PED;\r
- break;\r
+ //\r
+ // clear PORT_ENABLE feature means disable port.\r
+ //\r
+ case EfiUsbPortEnable:\r
+ RHPortControl &= 0xfff5;\r
+ RHPortControl &= ~USBPORTSC_PED;\r
+ break;\r
\r
- //\r
- // clear PORT_SUSPEND feature means resume the port.\r
- // (cause a resume on the specified port if in suspend mode)\r
- //\r
- case EfiUsbPortSuspend:\r
- RHPortControl &= 0xfff5;\r
- RHPortControl &= ~USBPORTSC_SUSP;\r
- break;\r
+ //\r
+ // clear PORT_SUSPEND feature means resume the port.\r
+ // (cause a resume on the specified port if in suspend mode)\r
+ //\r
+ case EfiUsbPortSuspend:\r
+ RHPortControl &= 0xfff5;\r
+ RHPortControl &= ~USBPORTSC_SUSP;\r
+ break;\r
\r
- //\r
- // no operation\r
- //\r
- case EfiUsbPortPower:\r
- break;\r
+ //\r
+ // no operation\r
+ //\r
+ case EfiUsbPortPower:\r
+ break;\r
\r
- //\r
- // clear PORT_RESET means clear the reset signal.\r
- //\r
- case EfiUsbPortReset:\r
- RHPortControl &= 0xfff5;\r
- RHPortControl &= ~USBPORTSC_PR;\r
- break;\r
+ //\r
+ // clear PORT_RESET means clear the reset signal.\r
+ //\r
+ case EfiUsbPortReset:\r
+ RHPortControl &= 0xfff5;\r
+ RHPortControl &= ~USBPORTSC_PR;\r
+ break;\r
\r
- //\r
- // clear connect status change\r
- //\r
- case EfiUsbPortConnectChange:\r
- RHPortControl &= 0xfff5;\r
- RHPortControl |= USBPORTSC_CSC;\r
- break;\r
+ //\r
+ // clear connect status change\r
+ //\r
+ case EfiUsbPortConnectChange:\r
+ RHPortControl &= 0xfff5;\r
+ RHPortControl |= USBPORTSC_CSC;\r
+ break;\r
\r
- //\r
- // clear enable/disable status change\r
- //\r
- case EfiUsbPortEnableChange:\r
- RHPortControl &= 0xfff5;\r
- RHPortControl |= USBPORTSC_PEDC;\r
- break;\r
+ //\r
+ // clear enable/disable status change\r
+ //\r
+ case EfiUsbPortEnableChange:\r
+ RHPortControl &= 0xfff5;\r
+ RHPortControl |= USBPORTSC_PEDC;\r
+ break;\r
\r
- //\r
- // root hub does not support this request\r
- //\r
- case EfiUsbPortSuspendChange:\r
- break;\r
+ //\r
+ // root hub does not support this request\r
+ //\r
+ case EfiUsbPortSuspendChange:\r
+ break;\r
\r
- //\r
- // root hub does not support this request\r
- //\r
- case EfiUsbPortOverCurrentChange:\r
- break;\r
+ //\r
+ // root hub does not support this request\r
+ //\r
+ case EfiUsbPortOverCurrentChange:\r
+ break;\r
\r
- //\r
- // root hub does not support this request\r
- //\r
- case EfiUsbPortResetChange:\r
- break;\r
+ //\r
+ // root hub does not support this request\r
+ //\r
+ case EfiUsbPortResetChange:\r
+ break;\r
\r
- default:\r
- return EFI_INVALID_PARAMETER;\r
+ default:\r
+ return EFI_INVALID_PARAMETER;\r
}\r
\r
USBWritePortW (UhcDev, PSAddr, RHPortControl);\r
**/\r
EFI_STATUS\r
InitializeUsbHC (\r
- IN USB_UHC_DEV *UhcDev\r
+ IN USB_UHC_DEV *UhcDev\r
)\r
{\r
EFI_STATUS Status;\r
return Status;\r
}\r
\r
- FrameListBaseAddrReg = UhcDev->UsbHostControllerBaseAddress + USBFLBASEADD;\r
- CommandReg = UhcDev->UsbHostControllerBaseAddress + USBCMD;\r
+ FrameListBaseAddrReg = UhcDev->UsbHostControllerBaseAddress + USBFLBASEADD;\r
+ CommandReg = UhcDev->UsbHostControllerBaseAddress + USBCMD;\r
\r
//\r
// Set Frame List Base Address to the specific register to inform the hardware.\r
//\r
- SetFrameListBaseAddress (UhcDev, FrameListBaseAddrReg, (UINT32) (UINTN) (UhcDev->FrameListEntry));\r
+ SetFrameListBaseAddress (UhcDev, FrameListBaseAddrReg, (UINT32)(UINTN)(UhcDev->FrameListEntry));\r
\r
- Command = USBReadPortW (UhcDev, CommandReg);\r
+ Command = USBReadPortW (UhcDev, CommandReg);\r
Command |= USBCMD_GRESET;\r
USBWritePortW (UhcDev, CommandReg, Command);\r
\r
MicroSecondDelay (50 * 1000);\r
\r
-\r
Command &= ~USBCMD_GRESET;\r
\r
USBWritePortW (UhcDev, CommandReg, Command);\r
\r
//\r
- //UHCI spec page120 reset recovery time\r
+ // UHCI spec page120 reset recovery time\r
//\r
MicroSecondDelay (20 * 1000);\r
\r
//\r
// Set Run/Stop bit to 1.\r
//\r
- Command = USBReadPortW (UhcDev, CommandReg);\r
+ Command = USBReadPortW (UhcDev, CommandReg);\r
Command |= USBCMD_RS | USBCMD_MAXP;\r
USBWritePortW (UhcDev, CommandReg, Command);\r
\r
**/\r
EFI_STATUS\r
CreateFrameList (\r
- USB_UHC_DEV *UhcDev\r
+ USB_UHC_DEV *UhcDev\r
)\r
{\r
EFI_STATUS Status;\r
}\r
\r
//\r
- //Create Control QH and Bulk QH and link them into Framelist Entry\r
+ // Create Control QH and Bulk QH and link them into Framelist Entry\r
//\r
- Status = CreateQH(UhcDev, &UhcDev->ConfigQH);\r
+ Status = CreateQH (UhcDev, &UhcDev->ConfigQH);\r
if (Status != EFI_SUCCESS) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
+\r
ASSERT (UhcDev->ConfigQH != NULL);\r
\r
- Status = CreateQH(UhcDev, &UhcDev->BulkQH);\r
+ Status = CreateQH (UhcDev, &UhcDev->BulkQH);\r
if (Status != EFI_SUCCESS) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
+\r
ASSERT (UhcDev->BulkQH != NULL);\r
\r
//\r
- //Set the corresponding QH pointer\r
+ // Set the corresponding QH pointer\r
//\r
- SetQHHorizontalLinkPtr(UhcDev->ConfigQH, UhcDev->BulkQH);\r
+ SetQHHorizontalLinkPtr (UhcDev->ConfigQH, UhcDev->BulkQH);\r
SetQHHorizontalQHorTDSelect (UhcDev->ConfigQH, TRUE);\r
SetQHHorizontalValidorInvalid (UhcDev->ConfigQH, TRUE);\r
\r
- UhcDev->FrameListEntry = (FRAMELIST_ENTRY *) ((UINTN) FrameListBaseAddr);\r
+ UhcDev->FrameListEntry = (FRAMELIST_ENTRY *)((UINTN)FrameListBaseAddr);\r
\r
FrameListPtr = UhcDev->FrameListEntry;\r
\r
FrameListPtr->FrameListPtr = (UINT32)(UINTN)UhcDev->ConfigQH >> 4;\r
FrameListPtr->FrameListPtrQSelect = 1;\r
FrameListPtr->FrameListRsvd = 0;\r
- FrameListPtr ++;\r
+ FrameListPtr++;\r
}\r
\r
return EFI_SUCCESS;\r
**/\r
UINT16\r
USBReadPortW (\r
- IN USB_UHC_DEV *UhcDev,\r
- IN UINT32 Port\r
+ IN USB_UHC_DEV *UhcDev,\r
+ IN UINT32 Port\r
)\r
{\r
return IoRead16 (Port);\r
**/\r
VOID\r
USBWritePortW (\r
- IN USB_UHC_DEV *UhcDev,\r
- IN UINT32 Port,\r
- IN UINT16 Data\r
+ IN USB_UHC_DEV *UhcDev,\r
+ IN UINT32 Port,\r
+ IN UINT16 Data\r
)\r
{\r
IoWrite16 (Port, Data);\r
**/\r
VOID\r
USBWritePortDW (\r
- IN USB_UHC_DEV *UhcDev,\r
- IN UINT32 Port,\r
- IN UINT32 Data\r
+ IN USB_UHC_DEV *UhcDev,\r
+ IN UINT32 Port,\r
+ IN UINT32 Data\r
)\r
{\r
IoWrite32 (Port, Data);\r
**/\r
VOID\r
ClearStatusReg (\r
- IN USB_UHC_DEV *UhcDev,\r
- IN UINT32 StatusAddr\r
+ IN USB_UHC_DEV *UhcDev,\r
+ IN UINT32 StatusAddr\r
)\r
{\r
//\r
**/\r
BOOLEAN\r
IsStatusOK (\r
- IN USB_UHC_DEV *UhcDev,\r
- IN UINT32 StatusRegAddr\r
+ IN USB_UHC_DEV *UhcDev,\r
+ IN UINT32 StatusRegAddr\r
)\r
{\r
UINT16 StatusValue;\r
}\r
}\r
\r
-\r
-\r
/**\r
Set Frame List Base Address.\r
\r
**/\r
VOID\r
SetFrameListBaseAddress (\r
- IN USB_UHC_DEV *UhcDev,\r
- IN UINT32 FrameListRegAddr,\r
- IN UINT32 Addr\r
+ IN USB_UHC_DEV *UhcDev,\r
+ IN UINT32 FrameListRegAddr,\r
+ IN UINT32 Addr\r
)\r
{\r
//\r
// Sets value in the USB Frame List Base Address register.\r
//\r
- USBWritePortDW (UhcDev, FrameListRegAddr, (UINT32) (Addr & 0xFFFFF000));\r
+ USBWritePortDW (UhcDev, FrameListRegAddr, (UINT32)(Addr & 0xFFFFF000));\r
}\r
\r
/**\r
**/\r
EFI_STATUS\r
CreateQH (\r
- IN USB_UHC_DEV *UhcDev,\r
- OUT QH_STRUCT **PtrQH\r
+ IN USB_UHC_DEV *UhcDev,\r
+ OUT QH_STRUCT **PtrQH\r
)\r
{\r
EFI_STATUS Status;\r
//\r
// allocate align memory for QH_STRUCT\r
//\r
- Status = AllocateTDorQHStruct (UhcDev, sizeof(QH_STRUCT), (void **)PtrQH);\r
+ Status = AllocateTDorQHStruct (UhcDev, sizeof (QH_STRUCT), (void **)PtrQH);\r
if (EFI_ERROR (Status)) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
+\r
//\r
// init each field of the QH_STRUCT\r
//\r
// Only the highest 28bit of the address is valid\r
// (take 32bit address as an example).\r
//\r
- PtrQH->QueueHead.QHHorizontalPtr = (UINT32) (UINTN) PtrNext >> 4;\r
+ PtrQH->QueueHead.QHHorizontalPtr = (UINT32)(UINTN)PtrNext >> 4;\r
}\r
\r
-\r
-\r
/**\r
Set a QH or TD horizontally to be connected with a specific QH.\r
\r
// Only the highest 28bit of the address is valid\r
// (take 32bit address as an example).\r
//\r
- PtrQH->QueueHead.QHVerticalPtr = (UINT32) (UINTN) PtrNext >> 4;\r
+ PtrQH->QueueHead.QHVerticalPtr = (UINT32)(UINTN)PtrNext >> 4;\r
}\r
\r
/**\r
PtrQH->QueueHead.QHVerticalTerminate = IsValid ? 0 : 1;\r
}\r
\r
-\r
-\r
/**\r
Allocate TD or QH Struct.\r
\r
**/\r
EFI_STATUS\r
AllocateTDorQHStruct (\r
- IN USB_UHC_DEV *UhcDev,\r
- IN UINT32 Size,\r
- OUT VOID **PtrStruct\r
+ IN USB_UHC_DEV *UhcDev,\r
+ IN UINT32 Size,\r
+ OUT VOID **PtrStruct\r
)\r
{\r
EFI_STATUS Status;\r
\r
- Status = EFI_SUCCESS;\r
- *PtrStruct = NULL;\r
+ Status = EFI_SUCCESS;\r
+ *PtrStruct = NULL;\r
\r
Status = UhcAllocatePool (\r
- UhcDev,\r
- (UINT8 **) PtrStruct,\r
- Size\r
- );\r
+ UhcDev,\r
+ (UINT8 **)PtrStruct,\r
+ Size\r
+ );\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
**/\r
EFI_STATUS\r
CreateTD (\r
- IN USB_UHC_DEV *UhcDev,\r
- OUT TD_STRUCT **PtrTD\r
+ IN USB_UHC_DEV *UhcDev,\r
+ OUT TD_STRUCT **PtrTD\r
)\r
{\r
EFI_STATUS Status;\r
+\r
//\r
// create memory for TD_STRUCT, and align the memory.\r
//\r
- Status = AllocateTDorQHStruct (UhcDev, sizeof(TD_STRUCT), (void **)PtrTD);\r
+ Status = AllocateTDorQHStruct (UhcDev, sizeof (TD_STRUCT), (void **)PtrTD);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
**/\r
EFI_STATUS\r
GenSetupStageTD (\r
- IN USB_UHC_DEV *UhcDev,\r
- IN UINT8 DevAddr,\r
- IN UINT8 Endpoint,\r
- IN UINT8 DeviceSpeed,\r
- IN UINT8 *DevRequest,\r
- IN UINT8 *RequestPhy,\r
- IN UINT8 RequestLen,\r
- OUT TD_STRUCT **PtrTD\r
+ IN USB_UHC_DEV *UhcDev,\r
+ IN UINT8 DevAddr,\r
+ IN UINT8 Endpoint,\r
+ IN UINT8 DeviceSpeed,\r
+ IN UINT8 *DevRequest,\r
+ IN UINT8 *RequestPhy,\r
+ IN UINT8 RequestLen,\r
+ OUT TD_STRUCT **PtrTD\r
)\r
{\r
TD_STRUCT *TdStruct;\r
// (TRUE - Slow Device; FALSE - Full Speed Device)\r
//\r
switch (DeviceSpeed) {\r
- case USB_SLOW_SPEED_DEVICE:\r
- SetTDLoworFullSpeedDevice (TdStruct, TRUE);\r
- break;\r
+ case USB_SLOW_SPEED_DEVICE:\r
+ SetTDLoworFullSpeedDevice (TdStruct, TRUE);\r
+ break;\r
\r
- case USB_FULL_SPEED_DEVICE:\r
- SetTDLoworFullSpeedDevice (TdStruct, FALSE);\r
- break;\r
+ case USB_FULL_SPEED_DEVICE:\r
+ SetTDLoworFullSpeedDevice (TdStruct, FALSE);\r
+ break;\r
}\r
+\r
//\r
// Non isochronous transfer TD\r
//\r
\r
SetTDTokenPacketID (TdStruct, SETUP_PACKET_ID);\r
\r
- TdStruct->PtrTDBuffer = (UINT8 *) DevRequest;\r
+ TdStruct->PtrTDBuffer = (UINT8 *)DevRequest;\r
TdStruct->TDBufferLength = RequestLen;\r
//\r
// Set the beginning address of the buffer that will be used\r
// during the transaction.\r
//\r
- TdStruct->TDData.TDBufferPtr = (UINT32) (UINTN) RequestPhy;\r
+ TdStruct->TDData.TDBufferPtr = (UINT32)(UINTN)RequestPhy;\r
\r
*PtrTD = TdStruct;\r
\r
**/\r
EFI_STATUS\r
GenDataTD (\r
- IN USB_UHC_DEV *UhcDev,\r
- IN UINT8 DevAddr,\r
- IN UINT8 Endpoint,\r
- IN UINT8 *PtrData,\r
- IN UINT8 *DataPhy,\r
- IN UINT8 Len,\r
- IN UINT8 PktID,\r
- IN UINT8 Toggle,\r
- IN UINT8 DeviceSpeed,\r
- OUT TD_STRUCT **PtrTD\r
+ IN USB_UHC_DEV *UhcDev,\r
+ IN UINT8 DevAddr,\r
+ IN UINT8 Endpoint,\r
+ IN UINT8 *PtrData,\r
+ IN UINT8 *DataPhy,\r
+ IN UINT8 Len,\r
+ IN UINT8 PktID,\r
+ IN UINT8 Toggle,\r
+ IN UINT8 DeviceSpeed,\r
+ OUT TD_STRUCT **PtrTD\r
)\r
{\r
TD_STRUCT *TdStruct;\r
// (TRUE - Slow Device; FALSE - Full Speed Device)\r
//\r
switch (DeviceSpeed) {\r
- case USB_SLOW_SPEED_DEVICE:\r
- SetTDLoworFullSpeedDevice (TdStruct, TRUE);\r
- break;\r
+ case USB_SLOW_SPEED_DEVICE:\r
+ SetTDLoworFullSpeedDevice (TdStruct, TRUE);\r
+ break;\r
\r
- case USB_FULL_SPEED_DEVICE:\r
- SetTDLoworFullSpeedDevice (TdStruct, FALSE);\r
- break;\r
+ case USB_FULL_SPEED_DEVICE:\r
+ SetTDLoworFullSpeedDevice (TdStruct, FALSE);\r
+ break;\r
}\r
+\r
//\r
// Non isochronous transfer TD\r
//\r
\r
SetTDTokenPacketID (TdStruct, PktID);\r
\r
- TdStruct->PtrTDBuffer = (UINT8 *) PtrData;\r
+ TdStruct->PtrTDBuffer = (UINT8 *)PtrData;\r
TdStruct->TDBufferLength = Len;\r
//\r
// Set the beginning address of the buffer that will be used\r
// during the transaction.\r
//\r
- TdStruct->TDData.TDBufferPtr = (UINT32) (UINTN) DataPhy;\r
+ TdStruct->TDData.TDBufferPtr = (UINT32)(UINTN)DataPhy;\r
\r
*PtrTD = TdStruct;\r
\r
**/\r
EFI_STATUS\r
CreateStatusTD (\r
- IN USB_UHC_DEV *UhcDev,\r
- IN UINT8 DevAddr,\r
- IN UINT8 Endpoint,\r
- IN UINT8 PktID,\r
- IN UINT8 DeviceSpeed,\r
- OUT TD_STRUCT **PtrTD\r
+ IN USB_UHC_DEV *UhcDev,\r
+ IN UINT8 DevAddr,\r
+ IN UINT8 Endpoint,\r
+ IN UINT8 PktID,\r
+ IN UINT8 DeviceSpeed,\r
+ OUT TD_STRUCT **PtrTD\r
)\r
{\r
TD_STRUCT *PtrTDStruct;\r
// (TRUE - Slow Device; FALSE - Full Speed Device)\r
//\r
switch (DeviceSpeed) {\r
- case USB_SLOW_SPEED_DEVICE:\r
- SetTDLoworFullSpeedDevice (PtrTDStruct, TRUE);\r
- break;\r
+ case USB_SLOW_SPEED_DEVICE:\r
+ SetTDLoworFullSpeedDevice (PtrTDStruct, TRUE);\r
+ break;\r
\r
- case USB_FULL_SPEED_DEVICE:\r
- SetTDLoworFullSpeedDevice (PtrTDStruct, FALSE);\r
- break;\r
+ case USB_FULL_SPEED_DEVICE:\r
+ SetTDLoworFullSpeedDevice (PtrTDStruct, FALSE);\r
+ break;\r
}\r
+\r
//\r
// Non isochronous transfer TD\r
//\r
\r
SetTDTokenPacketID (PtrTDStruct, PktID);\r
\r
- PtrTDStruct->PtrTDBuffer = NULL;\r
+ PtrTDStruct->PtrTDBuffer = NULL;\r
PtrTDStruct->TDBufferLength = 0;\r
//\r
// Set the beginning address of the buffer that will be used\r
**/\r
VOID\r
SetTDLinkPtrValidorInvalid (\r
- IN TD_STRUCT *PtrTDStruct,\r
- IN BOOLEAN IsValid\r
+ IN TD_STRUCT *PtrTDStruct,\r
+ IN BOOLEAN IsValid\r
)\r
{\r
//\r
**/\r
VOID\r
SetTDLinkPtrQHorTDSelect (\r
- IN TD_STRUCT *PtrTDStruct,\r
- IN BOOLEAN IsQH\r
+ IN TD_STRUCT *PtrTDStruct,\r
+ IN BOOLEAN IsQH\r
)\r
{\r
//\r
**/\r
VOID\r
SetTDLinkPtrDepthorBreadth (\r
- IN TD_STRUCT *PtrTDStruct,\r
- IN BOOLEAN IsDepth\r
+ IN TD_STRUCT *PtrTDStruct,\r
+ IN BOOLEAN IsDepth\r
)\r
{\r
//\r
**/\r
VOID\r
SetTDLinkPtr (\r
- IN TD_STRUCT *PtrTDStruct,\r
- IN VOID *PtrNext\r
+ IN TD_STRUCT *PtrTDStruct,\r
+ IN VOID *PtrNext\r
)\r
{\r
//\r
// Set TD Link Pointer. Since QH,TD align on 16-byte boundaries,\r
// only the highest 28 bits are valid. (if take 32bit address as an example)\r
//\r
- PtrTDStruct->TDData.TDLinkPtr = (UINT32) (UINTN) PtrNext >> 4;\r
+ PtrTDStruct->TDData.TDLinkPtr = (UINT32)(UINTN)PtrNext >> 4;\r
}\r
\r
/**\r
**/\r
VOID *\r
GetTDLinkPtr (\r
- IN TD_STRUCT *PtrTDStruct\r
+ IN TD_STRUCT *PtrTDStruct\r
)\r
{\r
//\r
// Get TD Link Pointer. Restore it back to 32bit\r
// (if take 32bit address as an example)\r
//\r
- return (VOID *) (UINTN) ((PtrTDStruct->TDData.TDLinkPtr) << 4);\r
+ return (VOID *)(UINTN)((PtrTDStruct->TDData.TDLinkPtr) << 4);\r
}\r
\r
-\r
-\r
/**\r
Enable/Disable short packet detection mechanism.\r
\r
**/\r
VOID\r
EnableorDisableTDShortPacket (\r
- IN TD_STRUCT *PtrTDStruct,\r
- IN BOOLEAN IsEnable\r
+ IN TD_STRUCT *PtrTDStruct,\r
+ IN BOOLEAN IsEnable\r
)\r
{\r
//\r
**/\r
VOID\r
SetTDControlErrorCounter (\r
- IN TD_STRUCT *PtrTDStruct,\r
- IN UINT8 MaxErrors\r
+ IN TD_STRUCT *PtrTDStruct,\r
+ IN UINT8 MaxErrors\r
)\r
{\r
//\r
**/\r
VOID\r
SetTDLoworFullSpeedDevice (\r
- IN TD_STRUCT *PtrTDStruct,\r
- IN BOOLEAN IsLowSpeedDevice\r
+ IN TD_STRUCT *PtrTDStruct,\r
+ IN BOOLEAN IsLowSpeedDevice\r
)\r
{\r
//\r
**/\r
VOID\r
SetTDControlIsochronousorNot (\r
- IN TD_STRUCT *PtrTDStruct,\r
- IN BOOLEAN IsIsochronous\r
+ IN TD_STRUCT *PtrTDStruct,\r
+ IN BOOLEAN IsIsochronous\r
)\r
{\r
//\r
**/\r
VOID\r
SetorClearTDControlIOC (\r
- IN TD_STRUCT *PtrTDStruct,\r
- IN BOOLEAN IsSet\r
+ IN TD_STRUCT *PtrTDStruct,\r
+ IN BOOLEAN IsSet\r
)\r
{\r
//\r
**/\r
VOID\r
SetTDStatusActiveorInactive (\r
- IN TD_STRUCT *PtrTDStruct,\r
- IN BOOLEAN IsActive\r
+ IN TD_STRUCT *PtrTDStruct,\r
+ IN BOOLEAN IsActive\r
)\r
{\r
//\r
**/\r
UINT16\r
SetTDTokenMaxLength (\r
- IN TD_STRUCT *PtrTDStruct,\r
- IN UINT16 MaxLen\r
+ IN TD_STRUCT *PtrTDStruct,\r
+ IN UINT16 MaxLen\r
)\r
{\r
//\r
**/\r
VOID\r
SetTDTokenDataToggle1 (\r
- IN TD_STRUCT *PtrTDStruct\r
+ IN TD_STRUCT *PtrTDStruct\r
)\r
{\r
//\r
**/\r
VOID\r
SetTDTokenDataToggle0 (\r
- IN TD_STRUCT *PtrTDStruct\r
+ IN TD_STRUCT *PtrTDStruct\r
)\r
{\r
//\r
**/\r
VOID\r
SetTDTokenEndPoint (\r
- IN TD_STRUCT *PtrTDStruct,\r
- IN UINTN EndPoint\r
+ IN TD_STRUCT *PtrTDStruct,\r
+ IN UINTN EndPoint\r
)\r
{\r
//\r
// Set EndPoint Number the TD is targeting at.\r
//\r
- PtrTDStruct->TDData.TDTokenEndPt = (UINT8) EndPoint;\r
+ PtrTDStruct->TDData.TDTokenEndPt = (UINT8)EndPoint;\r
}\r
\r
/**\r
**/\r
VOID\r
SetTDTokenDeviceAddress (\r
- IN TD_STRUCT *PtrTDStruct,\r
- IN UINTN DevAddr\r
+ IN TD_STRUCT *PtrTDStruct,\r
+ IN UINTN DevAddr\r
)\r
{\r
//\r
// Set Device Address the TD is targeting at.\r
//\r
- PtrTDStruct->TDData.TDTokenDevAddr = (UINT8) DevAddr;\r
+ PtrTDStruct->TDData.TDTokenDevAddr = (UINT8)DevAddr;\r
}\r
\r
/**\r
**/\r
VOID\r
SetTDTokenPacketID (\r
- IN TD_STRUCT *PtrTDStruct,\r
- IN UINT8 PacketID\r
+ IN TD_STRUCT *PtrTDStruct,\r
+ IN UINT8 PacketID\r
)\r
{\r
//\r
**/\r
BOOLEAN\r
IsTDStatusActive (\r
- IN TD_STRUCT *PtrTDStruct\r
+ IN TD_STRUCT *PtrTDStruct\r
)\r
{\r
- UINT8 TDStatus;\r
+ UINT8 TDStatus;\r
\r
//\r
// Detect whether the TD is active.\r
//\r
- TDStatus = (UINT8) (PtrTDStruct->TDData.TDStatus);\r
- return (BOOLEAN) (TDStatus & 0x80);\r
+ TDStatus = (UINT8)(PtrTDStruct->TDData.TDStatus);\r
+ return (BOOLEAN)(TDStatus & 0x80);\r
}\r
\r
/**\r
**/\r
BOOLEAN\r
IsTDStatusStalled (\r
- IN TD_STRUCT *PtrTDStruct\r
+ IN TD_STRUCT *PtrTDStruct\r
)\r
{\r
- UINT8 TDStatus;\r
+ UINT8 TDStatus;\r
\r
//\r
// Detect whether the device/endpoint addressed by this TD is stalled.\r
//\r
- TDStatus = (UINT8) (PtrTDStruct->TDData.TDStatus);\r
- return (BOOLEAN) (TDStatus & 0x40);\r
+ TDStatus = (UINT8)(PtrTDStruct->TDData.TDStatus);\r
+ return (BOOLEAN)(TDStatus & 0x40);\r
}\r
\r
/**\r
**/\r
BOOLEAN\r
IsTDStatusBufferError (\r
- IN TD_STRUCT *PtrTDStruct\r
+ IN TD_STRUCT *PtrTDStruct\r
)\r
{\r
- UINT8 TDStatus;\r
+ UINT8 TDStatus;\r
\r
//\r
// Detect whether Data Buffer Error is happened.\r
//\r
- TDStatus = (UINT8) (PtrTDStruct->TDData.TDStatus);\r
- return (BOOLEAN) (TDStatus & 0x20);\r
+ TDStatus = (UINT8)(PtrTDStruct->TDData.TDStatus);\r
+ return (BOOLEAN)(TDStatus & 0x20);\r
}\r
\r
/**\r
**/\r
BOOLEAN\r
IsTDStatusBabbleError (\r
- IN TD_STRUCT *PtrTDStruct\r
+ IN TD_STRUCT *PtrTDStruct\r
)\r
{\r
- UINT8 TDStatus;\r
+ UINT8 TDStatus;\r
\r
//\r
// Detect whether Babble Error is happened.\r
//\r
- TDStatus = (UINT8) (PtrTDStruct->TDData.TDStatus);\r
- return (BOOLEAN) (TDStatus & 0x10);\r
+ TDStatus = (UINT8)(PtrTDStruct->TDData.TDStatus);\r
+ return (BOOLEAN)(TDStatus & 0x10);\r
}\r
\r
/**\r
**/\r
BOOLEAN\r
IsTDStatusNAKReceived (\r
- IN TD_STRUCT *PtrTDStruct\r
+ IN TD_STRUCT *PtrTDStruct\r
)\r
{\r
- UINT8 TDStatus;\r
+ UINT8 TDStatus;\r
\r
//\r
// Detect whether NAK is received.\r
//\r
- TDStatus = (UINT8) (PtrTDStruct->TDData.TDStatus);\r
- return (BOOLEAN) (TDStatus & 0x08);\r
+ TDStatus = (UINT8)(PtrTDStruct->TDData.TDStatus);\r
+ return (BOOLEAN)(TDStatus & 0x08);\r
}\r
\r
/**\r
**/\r
BOOLEAN\r
IsTDStatusCRCTimeOutError (\r
- IN TD_STRUCT *PtrTDStruct\r
+ IN TD_STRUCT *PtrTDStruct\r
)\r
{\r
- UINT8 TDStatus;\r
+ UINT8 TDStatus;\r
\r
//\r
// Detect whether CRC/Time Out Error is encountered.\r
//\r
- TDStatus = (UINT8) (PtrTDStruct->TDData.TDStatus);\r
- return (BOOLEAN) (TDStatus & 0x04);\r
+ TDStatus = (UINT8)(PtrTDStruct->TDData.TDStatus);\r
+ return (BOOLEAN)(TDStatus & 0x04);\r
}\r
\r
/**\r
**/\r
BOOLEAN\r
IsTDStatusBitStuffError (\r
- IN TD_STRUCT *PtrTDStruct\r
+ IN TD_STRUCT *PtrTDStruct\r
)\r
{\r
- UINT8 TDStatus;\r
+ UINT8 TDStatus;\r
\r
//\r
// Detect whether Bitstuff Error is received.\r
//\r
- TDStatus = (UINT8) (PtrTDStruct->TDData.TDStatus);\r
- return (BOOLEAN) (TDStatus & 0x02);\r
+ TDStatus = (UINT8)(PtrTDStruct->TDData.TDStatus);\r
+ return (BOOLEAN)(TDStatus & 0x02);\r
}\r
\r
/**\r
**/\r
UINT16\r
GetTDStatusActualLength (\r
- IN TD_STRUCT *PtrTDStruct\r
+ IN TD_STRUCT *PtrTDStruct\r
)\r
{\r
//\r
// Retrieve the actual number of bytes that were tansferred.\r
// the value is encoded as n-1. so return the decoded value.\r
//\r
- return (UINT16) ((PtrTDStruct->TDData.TDStatusActualLength) + 1);\r
+ return (UINT16)((PtrTDStruct->TDData.TDStatusActualLength) + 1);\r
}\r
\r
/**\r
**/\r
BOOLEAN\r
GetTDLinkPtrValidorInvalid (\r
- IN TD_STRUCT *PtrTDStruct\r
+ IN TD_STRUCT *PtrTDStruct\r
)\r
{\r
//\r
} else {\r
return TRUE;\r
}\r
-\r
}\r
\r
/**\r
**/\r
UINTN\r
CountTDsNumber (\r
- IN TD_STRUCT *PtrFirstTD\r
+ IN TD_STRUCT *PtrFirstTD\r
)\r
{\r
- UINTN Number;\r
- TD_STRUCT *Ptr;\r
+ UINTN Number;\r
+ TD_STRUCT *Ptr;\r
\r
//\r
// Count the queued TDs number.\r
//\r
- Number = 0;\r
- Ptr = PtrFirstTD;\r
+ Number = 0;\r
+ Ptr = PtrFirstTD;\r
while (Ptr != 0) {\r
- Ptr = (TD_STRUCT *) Ptr->PtrNextTD;\r
+ Ptr = (TD_STRUCT *)Ptr->PtrNextTD;\r
Number++;\r
}\r
\r
**/\r
VOID\r
LinkTDToQH (\r
- IN QH_STRUCT *PtrQH,\r
- IN TD_STRUCT *PtrTD\r
+ IN QH_STRUCT *PtrQH,\r
+ IN TD_STRUCT *PtrTD\r
)\r
{\r
- if (PtrQH == NULL || PtrTD == NULL) {\r
- return ;\r
+ if ((PtrQH == NULL) || (PtrTD == NULL)) {\r
+ return;\r
}\r
+\r
//\r
// Validate QH Vertical Ptr field\r
//\r
//\r
SetQHVerticalQHorTDSelect (PtrQH, FALSE);\r
\r
- SetQHVerticalLinkPtr (PtrQH, (VOID *) PtrTD);\r
+ SetQHVerticalLinkPtr (PtrQH, (VOID *)PtrTD);\r
\r
- PtrQH->PtrDown = (VOID *) PtrTD;\r
+ PtrQH->PtrDown = (VOID *)PtrTD;\r
}\r
\r
/**\r
**/\r
VOID\r
LinkTDToTD (\r
- IN TD_STRUCT *PtrPreTD,\r
- IN TD_STRUCT *PtrTD\r
+ IN TD_STRUCT *PtrPreTD,\r
+ IN TD_STRUCT *PtrTD\r
)\r
{\r
- if (PtrPreTD == NULL || PtrTD == NULL) {\r
- return ;\r
+ if ((PtrPreTD == NULL) || (PtrTD == NULL)) {\r
+ return;\r
}\r
+\r
//\r
// Depth first fashion\r
//\r
\r
SetTDLinkPtr (PtrPreTD, PtrTD);\r
\r
- PtrPreTD->PtrNextTD = (VOID *) PtrTD;\r
+ PtrPreTD->PtrNextTD = (VOID *)PtrTD;\r
\r
- PtrTD->PtrNextTD = NULL;\r
+ PtrTD->PtrNextTD = NULL;\r
}\r
\r
/**\r
**/\r
EFI_STATUS\r
ExecuteControlTransfer (\r
- IN USB_UHC_DEV *UhcDev,\r
- IN TD_STRUCT *PtrTD,\r
- OUT UINTN *ActualLen,\r
- IN UINTN TimeOut,\r
- OUT UINT32 *TransferResult\r
+ IN USB_UHC_DEV *UhcDev,\r
+ IN TD_STRUCT *PtrTD,\r
+ OUT UINTN *ActualLen,\r
+ IN UINTN TimeOut,\r
+ OUT UINT32 *TransferResult\r
)\r
{\r
- UINTN ErrTDPos;\r
- UINTN Delay;\r
- BOOLEAN InfiniteLoop;\r
+ UINTN ErrTDPos;\r
+ UINTN Delay;\r
+ BOOLEAN InfiniteLoop;\r
\r
- ErrTDPos = 0;\r
- *TransferResult = EFI_USB_NOERROR;\r
- *ActualLen = 0;\r
- InfiniteLoop = FALSE;\r
+ ErrTDPos = 0;\r
+ *TransferResult = EFI_USB_NOERROR;\r
+ *ActualLen = 0;\r
+ InfiniteLoop = FALSE;\r
\r
Delay = TimeOut * STALL_1_MILLI_SECOND;\r
//\r
}\r
\r
do {\r
-\r
CheckTDsResults (PtrTD, TransferResult, &ErrTDPos, ActualLen);\r
\r
//\r
if ((*TransferResult & EFI_USB_ERR_NOTEXECUTE) != EFI_USB_ERR_NOTEXECUTE) {\r
break;\r
}\r
+\r
MicroSecondDelay (STALL_1_MICRO_SECOND);\r
Delay--;\r
-\r
} while (InfiniteLoop || (Delay != 0));\r
\r
if (*TransferResult != EFI_USB_NOERROR) {\r
**/\r
EFI_STATUS\r
ExecBulkTransfer (\r
- IN USB_UHC_DEV *UhcDev,\r
- IN TD_STRUCT *PtrTD,\r
- IN OUT UINTN *ActualLen,\r
- IN UINT8 *DataToggle,\r
- IN UINTN TimeOut,\r
- OUT UINT32 *TransferResult\r
+ IN USB_UHC_DEV *UhcDev,\r
+ IN TD_STRUCT *PtrTD,\r
+ IN OUT UINTN *ActualLen,\r
+ IN UINT8 *DataToggle,\r
+ IN UINTN TimeOut,\r
+ OUT UINT32 *TransferResult\r
)\r
{\r
- UINTN ErrTDPos;\r
- UINTN ScrollNum;\r
- UINTN Delay;\r
- BOOLEAN InfiniteLoop;\r
+ UINTN ErrTDPos;\r
+ UINTN ScrollNum;\r
+ UINTN Delay;\r
+ BOOLEAN InfiniteLoop;\r
\r
- ErrTDPos = 0;\r
- *TransferResult = EFI_USB_NOERROR;\r
- *ActualLen = 0;\r
- InfiniteLoop = FALSE;\r
+ ErrTDPos = 0;\r
+ *TransferResult = EFI_USB_NOERROR;\r
+ *ActualLen = 0;\r
+ InfiniteLoop = FALSE;\r
\r
Delay = TimeOut * STALL_1_MILLI_SECOND;\r
//\r
}\r
\r
do {\r
-\r
CheckTDsResults (PtrTD, TransferResult, &ErrTDPos, ActualLen);\r
//\r
// TD is inactive, thus meaning bulk transfer's end.\r
if ((*TransferResult & EFI_USB_ERR_NOTEXECUTE) != EFI_USB_ERR_NOTEXECUTE) {\r
break;\r
}\r
+\r
MicroSecondDelay (STALL_1_MICRO_SECOND);\r
Delay--;\r
-\r
} while (InfiniteLoop || (Delay != 0));\r
\r
//\r
*DataToggle ^= 1;\r
}\r
\r
- //\r
- // If error, wait 100ms to retry by upper layer\r
- //\r
+ //\r
+ // If error, wait 100ms to retry by upper layer\r
+ //\r
MicroSecondDelay (100 * 1000);\r
return EFI_DEVICE_ERROR;\r
}\r
**/\r
VOID\r
DeleteQueuedTDs (\r
- IN USB_UHC_DEV *UhcDev,\r
- IN TD_STRUCT *PtrFirstTD\r
+ IN USB_UHC_DEV *UhcDev,\r
+ IN TD_STRUCT *PtrFirstTD\r
)\r
{\r
- TD_STRUCT *Tptr1;\r
+ TD_STRUCT *Tptr1;\r
\r
- TD_STRUCT *Tptr2;\r
+ TD_STRUCT *Tptr2;\r
\r
Tptr1 = PtrFirstTD;\r
//\r
// Delete all the TDs in a queue.\r
//\r
while (Tptr1 != NULL) {\r
-\r
Tptr2 = Tptr1;\r
\r
if (!GetTDLinkPtrValidorInvalid (Tptr2)) {\r
Tptr1 = GetTDLinkPtr (Tptr2);\r
}\r
\r
- UhcFreePool (UhcDev, (UINT8 *) Tptr2, sizeof (TD_STRUCT));\r
+ UhcFreePool (UhcDev, (UINT8 *)Tptr2, sizeof (TD_STRUCT));\r
}\r
\r
- return ;\r
+ return;\r
}\r
\r
/**\r
**/\r
BOOLEAN\r
CheckTDsResults (\r
- IN TD_STRUCT *PtrTD,\r
- OUT UINT32 *Result,\r
- OUT UINTN *ErrTDPos,\r
- OUT UINTN *ActualTransferSize\r
+ IN TD_STRUCT *PtrTD,\r
+ OUT UINT32 *Result,\r
+ OUT UINTN *ErrTDPos,\r
+ OUT UINTN *ActualTransferSize\r
)\r
{\r
- UINTN Len;\r
+ UINTN Len;\r
\r
*Result = EFI_USB_NOERROR;\r
*ErrTDPos = 0;\r
*ActualTransferSize = 0;\r
\r
while (PtrTD != NULL) {\r
-\r
if (IsTDStatusActive (PtrTD)) {\r
*Result |= EFI_USB_ERR_NOTEXECUTE;\r
}\r
if (IsTDStatusBitStuffError (PtrTD)) {\r
*Result |= EFI_USB_ERR_BITSTUFF;\r
}\r
+\r
//\r
// Accumulate actual transferred data length in each TD.\r
//\r
- Len = GetTDStatusActualLength (PtrTD) & 0x7FF;\r
+ Len = GetTDStatusActualLength (PtrTD) & 0x7FF;\r
*ActualTransferSize += Len;\r
\r
//\r
return FALSE;\r
}\r
\r
- PtrTD = (TD_STRUCT *) (PtrTD->PtrNextTD);\r
+ PtrTD = (TD_STRUCT *)(PtrTD->PtrNextTD);\r
//\r
// Record the first Error TD's position in the queue,\r
// this value is zero-based.\r
// memory management header and bit array use 1 page\r
//\r
MemPages = MemoryBlockSizeInPages + 1;\r
- Status = IoMmuAllocateBuffer (\r
- UhcDev->IoMmu,\r
- MemPages,\r
- (VOID **) &TempPtr,\r
- &MappedAddr,\r
- &Mapping\r
- );\r
+ Status = IoMmuAllocateBuffer (\r
+ UhcDev->IoMmu,\r
+ MemPages,\r
+ (VOID **)&TempPtr,\r
+ &MappedAddr,\r
+ &Mapping\r
+ );\r
if (EFI_ERROR (Status) || (TempPtr == NULL)) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
\r
ZeroMem (Ptr, MemPages * EFI_PAGE_SIZE);\r
\r
- *MemoryHeader = (MEMORY_MANAGE_HEADER *) Ptr;\r
+ *MemoryHeader = (MEMORY_MANAGE_HEADER *)Ptr;\r
//\r
// adjust Ptr pointer to the next empty memory\r
//\r
//\r
// Set Bit Array initial address\r
//\r
- (*MemoryHeader)->BitArrayPtr = Ptr;\r
+ (*MemoryHeader)->BitArrayPtr = Ptr;\r
\r
- (*MemoryHeader)->Next = NULL;\r
+ (*MemoryHeader)->Next = NULL;\r
\r
//\r
// Memory block initial address\r
//\r
- Ptr = TempPtr;\r
- Ptr += EFI_PAGE_SIZE;\r
+ Ptr = TempPtr;\r
+ Ptr += EFI_PAGE_SIZE;\r
(*MemoryHeader)->MemoryBlockPtr = Ptr;\r
//\r
// set Memory block size\r
**/\r
EFI_STATUS\r
InitializeMemoryManagement (\r
- IN USB_UHC_DEV *UhcDev\r
+ IN USB_UHC_DEV *UhcDev\r
)\r
{\r
MEMORY_MANAGE_HEADER *MemoryHeader;\r
EFI_STATUS Status;\r
UINTN MemPages;\r
\r
- MemPages = NORMAL_MEMORY_BLOCK_UNIT_IN_PAGES;\r
- Status = CreateMemoryBlock (UhcDev, &MemoryHeader, MemPages);\r
+ MemPages = NORMAL_MEMORY_BLOCK_UNIT_IN_PAGES;\r
+ Status = CreateMemoryBlock (UhcDev, &MemoryHeader, MemPages);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
**/\r
EFI_STATUS\r
UhcAllocatePool (\r
- IN USB_UHC_DEV *UhcDev,\r
- OUT UINT8 **Pool,\r
- IN UINTN AllocSize\r
+ IN USB_UHC_DEV *UhcDev,\r
+ OUT UINT8 **Pool,\r
+ IN UINTN AllocSize\r
)\r
{\r
MEMORY_MANAGE_HEADER *MemoryHeader;\r
\r
Status = EFI_NOT_FOUND;\r
for (TempHeaderPtr = MemoryHeader; TempHeaderPtr != NULL; TempHeaderPtr = TempHeaderPtr->Next) {\r
-\r
Status = AllocMemInMemoryBlock (\r
- TempHeaderPtr,\r
- (VOID **) Pool,\r
- RealAllocSize / 32\r
- );\r
+ TempHeaderPtr,\r
+ (VOID **)Pool,\r
+ RealAllocSize / 32\r
+ );\r
if (!EFI_ERROR (Status)) {\r
return EFI_SUCCESS;\r
}\r
}\r
+\r
//\r
// There is no enough memory,\r
// Create a new Memory Block\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
//\r
// Link the new Memory Block to the Memory Header list\r
//\r
InsertMemoryHeaderToList (MemoryHeader, NewMemoryHeader);\r
\r
Status = AllocMemInMemoryBlock (\r
- NewMemoryHeader,\r
- (VOID **) Pool,\r
- RealAllocSize / 32\r
- );\r
+ NewMemoryHeader,\r
+ (VOID **)Pool,\r
+ RealAllocSize / 32\r
+ );\r
return Status;\r
}\r
\r
IN UINTN NumberOfMemoryUnit\r
)\r
{\r
- UINTN TempBytePos;\r
- UINTN FoundBytePos;\r
- UINT8 Index;\r
- UINT8 FoundBitPos;\r
- UINT8 ByteValue;\r
- UINT8 BitValue;\r
- UINTN NumberOfZeros;\r
- UINTN Count;\r
+ UINTN TempBytePos;\r
+ UINTN FoundBytePos;\r
+ UINT8 Index;\r
+ UINT8 FoundBitPos;\r
+ UINT8 ByteValue;\r
+ UINT8 BitValue;\r
+ UINTN NumberOfZeros;\r
+ UINTN Count;\r
\r
- FoundBytePos = 0;\r
- FoundBitPos = 0;\r
+ FoundBytePos = 0;\r
+ FoundBitPos = 0;\r
\r
ByteValue = MemoryHeader->BitArrayPtr[0];\r
NumberOfZeros = 0;\r
- Index = 0;\r
+ Index = 0;\r
for (TempBytePos = 0; TempBytePos < MemoryHeader->BitArraySizeInBytes;) {\r
//\r
// Pop out BitValue from a byte in TempBytePos.\r
//\r
// reset the (FoundBytePos,FoundBitPos) to the position of '1'\r
//\r
- FoundBytePos = TempBytePos;\r
- FoundBitPos = Index;\r
+ FoundBytePos = TempBytePos;\r
+ FoundBitPos = Index;\r
}\r
}\r
+\r
//\r
// right shift the byte\r
//\r
// and reset the bit pos.\r
//\r
TempBytePos += 1;\r
- ByteValue = MemoryHeader->BitArrayPtr[TempBytePos];\r
- Index = 0;\r
+ ByteValue = MemoryHeader->BitArrayPtr[TempBytePos];\r
+ Index = 0;\r
}\r
}\r
\r
if (NumberOfZeros < NumberOfMemoryUnit) {\r
return EFI_NOT_FOUND;\r
}\r
+\r
//\r
// Found enough free space.\r
//\r
if ((MemoryHeader->BitArrayPtr[0] & BIT0) != 0) {\r
FoundBitPos += 1;\r
}\r
+\r
//\r
// Have the (FoundBytePos,FoundBitPos) make sense.\r
//\r
if (FoundBitPos > 7) {\r
FoundBytePos += 1;\r
- FoundBitPos -= 8;\r
+ FoundBitPos -= 8;\r
}\r
+\r
//\r
// Set the memory as allocated\r
//\r
for (TempBytePos = FoundBytePos, Index = FoundBitPos, Count = 0; Count < NumberOfMemoryUnit; Count++) {\r
-\r
- MemoryHeader->BitArrayPtr[TempBytePos] = (UINT8) (MemoryHeader->BitArrayPtr[TempBytePos] | (1 << Index));\r
+ MemoryHeader->BitArrayPtr[TempBytePos] = (UINT8)(MemoryHeader->BitArrayPtr[TempBytePos] | (1 << Index));\r
Index++;\r
if (Index == 8) {\r
TempBytePos += 1;\r
- Index = 0;\r
+ Index = 0;\r
}\r
}\r
\r
**/\r
VOID\r
UhcFreePool (\r
- IN USB_UHC_DEV *UhcDev,\r
- IN UINT8 *Pool,\r
- IN UINTN AllocSize\r
+ IN USB_UHC_DEV *UhcDev,\r
+ IN UINT8 *Pool,\r
+ IN UINTN AllocSize\r
)\r
{\r
MEMORY_MANAGE_HEADER *MemoryHeader;\r
}\r
\r
for (TempHeaderPtr = MemoryHeader; TempHeaderPtr != NULL;\r
- TempHeaderPtr = TempHeaderPtr->Next) {\r
-\r
+ TempHeaderPtr = TempHeaderPtr->Next)\r
+ {\r
if ((Pool >= TempHeaderPtr->MemoryBlockPtr) &&\r
((Pool + RealAllocSize) <= (TempHeaderPtr->MemoryBlockPtr +\r
- TempHeaderPtr->MemoryBlockSizeInBytes))) {\r
-\r
+ TempHeaderPtr->MemoryBlockSizeInBytes)))\r
+ {\r
//\r
// Pool is in the Memory Block area,\r
// find the start byte and bit in the bit array\r
//\r
- StartBytePos = ((Pool - TempHeaderPtr->MemoryBlockPtr) / 32) / 8;\r
- StartBitPos = (UINT8) (((Pool - TempHeaderPtr->MemoryBlockPtr) / 32) % 8);\r
+ StartBytePos = ((Pool - TempHeaderPtr->MemoryBlockPtr) / 32) / 8;\r
+ StartBitPos = (UINT8)(((Pool - TempHeaderPtr->MemoryBlockPtr) / 32) % 8);\r
\r
//\r
// reset associated bits in bit array\r
//\r
for (Index = StartBytePos, Index2 = StartBitPos, Count = 0; Count < (RealAllocSize / 32); Count++) {\r
-\r
- TempHeaderPtr->BitArrayPtr[Index] = (UINT8) (TempHeaderPtr->BitArrayPtr[Index] ^ (1 << Index2));\r
+ TempHeaderPtr->BitArrayPtr[Index] = (UINT8)(TempHeaderPtr->BitArrayPtr[Index] ^ (1 << Index2));\r
Index2++;\r
if (Index2 == 8) {\r
Index += 1;\r
Index2 = 0;\r
}\r
}\r
+\r
//\r
// break the loop\r
//\r
break;\r
}\r
}\r
-\r
}\r
\r
/**\r
}\r
}\r
\r
-\r
-\r
-\r
-\r
/**\r
Map address of request structure buffer.\r
\r
**/\r
EFI_STATUS\r
UhciMapUserRequest (\r
- IN USB_UHC_DEV *Uhc,\r
- IN OUT VOID *Request,\r
- OUT UINT8 **MappedAddr,\r
- OUT VOID **Map\r
+ IN USB_UHC_DEV *Uhc,\r
+ IN OUT VOID *Request,\r
+ OUT UINT8 **MappedAddr,\r
+ OUT VOID **Map\r
)\r
{\r
EFI_STATUS Status;\r
);\r
\r
if (!EFI_ERROR (Status)) {\r
- *MappedAddr = (UINT8 *) (UINTN) PhyAddr;\r
+ *MappedAddr = (UINT8 *)(UINTN)PhyAddr;\r
}\r
\r
return Status;\r
Status = EFI_SUCCESS;\r
\r
switch (Direction) {\r
- case EfiUsbDataIn:\r
- //\r
- // BusMasterWrite means cpu read\r
- //\r
- *PktId = INPUT_PACKET_ID;\r
- Status = IoMmuMap (\r
- Uhc->IoMmu,\r
- EdkiiIoMmuOperationBusMasterWrite,\r
- Data,\r
- Len,\r
- &PhyAddr,\r
- Map\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- goto EXIT;\r
- }\r
+ case EfiUsbDataIn:\r
+ //\r
+ // BusMasterWrite means cpu read\r
+ //\r
+ *PktId = INPUT_PACKET_ID;\r
+ Status = IoMmuMap (\r
+ Uhc->IoMmu,\r
+ EdkiiIoMmuOperationBusMasterWrite,\r
+ Data,\r
+ Len,\r
+ &PhyAddr,\r
+ Map\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ goto EXIT;\r
+ }\r
\r
- *MappedAddr = (UINT8 *) (UINTN) PhyAddr;\r
- break;\r
-\r
- case EfiUsbDataOut:\r
- *PktId = OUTPUT_PACKET_ID;\r
- Status = IoMmuMap (\r
- Uhc->IoMmu,\r
- EdkiiIoMmuOperationBusMasterRead,\r
- Data,\r
- Len,\r
- &PhyAddr,\r
- Map\r
- );\r
+ *MappedAddr = (UINT8 *)(UINTN)PhyAddr;\r
+ break;\r
\r
- if (EFI_ERROR (Status)) {\r
- goto EXIT;\r
- }\r
+ case EfiUsbDataOut:\r
+ *PktId = OUTPUT_PACKET_ID;\r
+ Status = IoMmuMap (\r
+ Uhc->IoMmu,\r
+ EdkiiIoMmuOperationBusMasterRead,\r
+ Data,\r
+ Len,\r
+ &PhyAddr,\r
+ Map\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ goto EXIT;\r
+ }\r
\r
- *MappedAddr = (UINT8 *) (UINTN) PhyAddr;\r
- break;\r
+ *MappedAddr = (UINT8 *)(UINTN)PhyAddr;\r
+ break;\r
\r
- case EfiUsbNoData:\r
- if ((Len != NULL) && (*Len != 0)) {\r
- Status = EFI_INVALID_PARAMETER;\r
- goto EXIT;\r
- }\r
+ case EfiUsbNoData:\r
+ if ((Len != NULL) && (*Len != 0)) {\r
+ Status = EFI_INVALID_PARAMETER;\r
+ goto EXIT;\r
+ }\r
\r
- *PktId = OUTPUT_PACKET_ID;\r
- *MappedAddr = NULL;\r
- *Map = NULL;\r
- break;\r
+ *PktId = OUTPUT_PACKET_ID;\r
+ *MappedAddr = NULL;\r
+ *Map = NULL;\r
+ break;\r
\r
- default:\r
- Status = EFI_INVALID_PARAMETER;\r
+ default:\r
+ Status = EFI_INVALID_PARAMETER;\r
}\r
\r
EXIT:\r
return Status;\r
}\r
-\r
projects / mirror_edk2.git / blobdiff