MdeModulePkg/PciBusDxe: catch unimplemented extended config space reads

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciReg.c

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
index 5f0736a516b6e4f0d23b7ec02ed1dcbdd6b0aefd..42b773ab31bea8d5264b6afa708f848014b538fd 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
@@ -3,13 +3,7 @@
   The XHCI register operation routines.\r
 \r
 Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution.  The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
-\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
 \r
@@ -586,6 +580,39 @@ XhcIsSysError (
   return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HSE);\r
 }\r
 \r
+/**\r
+  Set USBCMD Host System Error Enable(HSEE) Bit if PCICMD SERR# Enable Bit is set.\r
+\r
+  The USBCMD HSEE Bit will be reset to default 0 by USBCMD Host Controller Reset(HCRST).\r
+  This function is to set USBCMD HSEE Bit if PCICMD SERR# Enable Bit is set.\r
+\r
+  @param Xhc            The XHCI Instance.\r
+\r
+**/\r
+VOID\r
+XhcSetHsee (\r
+  IN USB_XHCI_INSTANCE  *Xhc\r
+  )\r
+{\r
+  EFI_STATUS            Status;\r
+  EFI_PCI_IO_PROTOCOL   *PciIo;\r
+  UINT16                XhciCmd;\r
+\r
+  PciIo = Xhc->PciIo;\r
+  Status = PciIo->Pci.Read (\r
+                        PciIo,\r
+                        EfiPciIoWidthUint16,\r
+                        PCI_COMMAND_OFFSET,\r
+                        sizeof (XhciCmd) / sizeof (UINT16),\r
+                        &XhciCmd\r
+                        );\r
+  if (!EFI_ERROR (Status)) {\r
+    if ((XhciCmd & EFI_PCI_COMMAND_SERR) != 0) {\r
+      XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_HSEE);\r
+    }\r
+  }\r
+}\r
+\r
 /**\r
   Reset the XHCI host controller.\r
 \r
@@ -628,6 +655,14 @@ XhcResetHC (
     //\r
     gBS->Stall (XHC_1_MILLISECOND);\r
     Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);\r
+\r
+    if (!EFI_ERROR (Status)) {\r
+      //\r
+      // The USBCMD HSEE Bit will be reset to default 0 by USBCMD HCRST.\r
+      // Set USBCMD HSEE Bit if PCICMD SERR# Enable Bit is set.\r
+      //\r
+      XhcSetHsee (Xhc);\r
+    }\r
   }\r
 \r
   return Status;\r