/**\r
Read 1-byte width XHCI capability register.\r
\r
- @param Xhc The XHCI device.\r
+ @param Xhc The XHCI Instance.\r
@param Offset The offset of the 1-byte width capability register.\r
\r
@return The register content read.\r
**/\r
UINT8\r
XhcReadCapReg8 (\r
- IN USB_XHCI_DEV *Xhc,\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
IN UINT32 Offset\r
)\r
{\r
/**\r
Read 4-bytes width XHCI capability register.\r
\r
- @param Xhc The XHCI device.\r
+ @param Xhc The XHCI Instance.\r
@param Offset The offset of the 4-bytes width capability register.\r
\r
@return The register content read.\r
**/\r
UINT32\r
XhcReadCapReg (\r
- IN USB_XHCI_DEV *Xhc,\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
IN UINT32 Offset\r
)\r
{\r
/**\r
Read 4-bytes width XHCI Operational register.\r
\r
- @param Xhc The XHCI device.\r
+ @param Xhc The XHCI Instance.\r
@param Offset The offset of the 4-bytes width operational register.\r
\r
@return The register content read.\r
**/\r
UINT32\r
XhcReadOpReg (\r
- IN USB_XHCI_DEV *Xhc,\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
IN UINT32 Offset\r
)\r
{\r
/**\r
Write the data to the 4-bytes width XHCI operational register.\r
\r
- @param Xhc The XHCI device.\r
+ @param Xhc The XHCI Instance.\r
@param Offset The offset of the 4-bytes width operational register.\r
@param Data The data to write.\r
\r
**/\r
VOID\r
XhcWriteOpReg (\r
- IN USB_XHCI_DEV *Xhc,\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
IN UINT32 Offset,\r
IN UINT32 Data\r
)\r
/**\r
Write the data to the 2-bytes width XHCI operational register.\r
\r
- @param Xhc The XHCI device.\r
+ @param Xhc The XHCI Instance.\r
@param Offset The offset of the 2-bytes width operational register.\r
@param Data The data to write.\r
\r
**/\r
VOID\r
XhcWriteOpReg16 (\r
- IN USB_XHCI_DEV *Xhc,\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
IN UINT32 Offset,\r
IN UINT16 Data\r
)\r
}\r
}\r
\r
-/**\r
- Write the data to the 8-bytes width XHCI operational register.\r
-\r
- @param Xhc The XHCI device.\r
- @param Offset The offset of the 8-bytes width operational register.\r
- @param Data The data to write.\r
-\r
-**/\r
-VOID\r
-XhcWriteOpReg64 (\r
- IN USB_XHCI_DEV *Xhc,\r
- IN UINT32 Offset,\r
- IN UINT64 Data\r
- )\r
-{\r
- EFI_STATUS Status;\r
-\r
- ASSERT (Xhc->CapLength != 0);\r
-\r
- Status = Xhc->PciIo->Mem.Write (\r
- Xhc->PciIo,\r
- EfiPciIoWidthUint64,\r
- XHC_BAR_INDEX,\r
- (UINT64) (Xhc->CapLength + Offset),\r
- 1,\r
- &Data\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "XhcWriteOpReg64: Pci Io Write error: %r at %d\n", Status, Offset));\r
- }\r
-}\r
-\r
/**\r
Read XHCI door bell register.\r
\r
- @param Xhc The XHCI device.\r
+ @param Xhc The XHCI Instance.\r
@param Offset The offset of the door bell register.\r
\r
@return The register content read\r
**/\r
UINT32\r
XhcReadDoorBellReg (\r
- IN USB_XHCI_DEV *Xhc,\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
IN UINT32 Offset\r
)\r
{\r
/**\r
Write the data to the XHCI door bell register.\r
\r
- @param Xhc The XHCI device.\r
+ @param Xhc The XHCI Instance.\r
@param Offset The offset of the door bell register.\r
@param Data The data to write.\r
\r
**/\r
VOID\r
XhcWriteDoorBellReg (\r
- IN USB_XHCI_DEV *Xhc,\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
IN UINT32 Offset,\r
IN UINT32 Data\r
)\r
/**\r
Read XHCI runtime register.\r
\r
- @param Xhc The XHCI device.\r
+ @param Xhc The XHCI Instance.\r
@param Offset The offset of the runtime register.\r
\r
@return The register content read\r
**/\r
UINT32\r
XhcReadRuntimeReg (\r
- IN USB_XHCI_DEV *Xhc,\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
IN UINT32 Offset\r
)\r
{\r
return Data;\r
}\r
\r
-/**\r
- Read 8-bytes width XHCI runtime register.\r
-\r
- @param Xhc The XHCI device.\r
- @param Offset The offset of the 8-bytes width runtime register.\r
-\r
- @return The register content read\r
-\r
-**/\r
-UINT64\r
-XhcReadRuntimeReg64 (\r
- IN USB_XHCI_DEV *Xhc,\r
- IN UINT32 Offset\r
- )\r
-{\r
- UINT64 Data;\r
- EFI_STATUS Status;\r
-\r
- ASSERT (Xhc->RTSOff != 0);\r
-\r
- Status = Xhc->PciIo->Mem.Read (\r
- Xhc->PciIo,\r
- EfiPciIoWidthUint64,\r
- XHC_BAR_INDEX,\r
- (UINT64) (Xhc->RTSOff + Offset),\r
- 1,\r
- &Data\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "XhcReadRuntimeReg64: Pci Io Read error - %r at %d\n", Status, Offset));\r
- Data = 0xFFFFFFFFFFFFFFFFULL;\r
- }\r
-\r
- return Data;\r
-}\r
-\r
/**\r
Write the data to the XHCI runtime register.\r
\r
- @param Xhc The XHCI device.\r
+ @param Xhc The XHCI Instance.\r
@param Offset The offset of the runtime register.\r
@param Data The data to write.\r
\r
**/\r
VOID\r
XhcWriteRuntimeReg (\r
- IN USB_XHCI_DEV *Xhc,\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
IN UINT32 Offset,\r
IN UINT32 Data\r
)\r
}\r
}\r
\r
-/**\r
- Write the data to the 8-bytes width XHCI runtime register.\r
-\r
- @param Xhc The XHCI device.\r
- @param Offset The offset of the 8-bytes width runtime register.\r
- @param Data The data to write.\r
-\r
-**/\r
-VOID\r
-XhcWriteRuntimeReg64 (\r
- IN USB_XHCI_DEV *Xhc,\r
- IN UINT32 Offset,\r
- IN UINT64 Data\r
- )\r
-{\r
- EFI_STATUS Status;\r
-\r
- ASSERT (Xhc->RTSOff != 0);\r
-\r
- Status = Xhc->PciIo->Mem.Write (\r
- Xhc->PciIo,\r
- EfiPciIoWidthUint64,\r
- XHC_BAR_INDEX,\r
- (UINT64) (Xhc->RTSOff + Offset),\r
- 1,\r
- &Data\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "XhcWriteRuntimeReg64: Pci Io Write error: %r at %d\n", Status, Offset));\r
- }\r
-}\r
-\r
/**\r
Read XHCI extended capability register.\r
\r
- @param Xhc The XHCI device.\r
+ @param Xhc The XHCI Instance.\r
@param Offset The offset of the extended capability register.\r
\r
@return The register content read\r
**/\r
UINT32\r
XhcReadExtCapReg (\r
- IN USB_XHCI_DEV *Xhc,\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
IN UINT32 Offset\r
)\r
{\r
/**\r
Write the data to the XHCI extended capability register.\r
\r
- @param Xhc The XHCI device.\r
+ @param Xhc The XHCI Instance.\r
@param Offset The offset of the extended capability register.\r
@param Data The data to write.\r
\r
**/\r
VOID\r
XhcWriteExtCapReg (\r
- IN USB_XHCI_DEV *Xhc,\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
IN UINT32 Offset,\r
IN UINT32 Data\r
)\r
/**\r
Set one bit of the runtime register while keeping other bits.\r
\r
- @param Xhc The XHCI device.\r
+ @param Xhc The XHCI Instance.\r
@param Offset The offset of the runtime register.\r
@param Bit The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcSetRuntimeRegBit (\r
- IN USB_XHCI_DEV *Xhc,\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
IN UINT32 Offset,\r
IN UINT32 Bit\r
)\r
/**\r
Clear one bit of the runtime register while keeping other bits.\r
\r
- @param Xhc The XHCI device.\r
+ @param Xhc The XHCI Instance.\r
@param Offset The offset of the runtime register.\r
@param Bit The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcClearRuntimeRegBit (\r
- IN USB_XHCI_DEV *Xhc,\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
IN UINT32 Offset,\r
IN UINT32 Bit\r
)\r
/**\r
Set one bit of the operational register while keeping other bits.\r
\r
- @param Xhc The XHCI device.\r
+ @param Xhc The XHCI Instance.\r
@param Offset The offset of the operational register.\r
@param Bit The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcSetOpRegBit (\r
- IN USB_XHCI_DEV *Xhc,\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
IN UINT32 Offset,\r
IN UINT32 Bit\r
)\r
/**\r
Clear one bit of the operational register while keeping other bits.\r
\r
- @param Xhc The XHCI device.\r
+ @param Xhc The XHCI Instance.\r
@param Offset The offset of the operational register.\r
@param Bit The bit mask of the register to clear.\r
\r
**/\r
VOID\r
XhcClearOpRegBit (\r
- IN USB_XHCI_DEV *Xhc,\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
IN UINT32 Offset,\r
IN UINT32 Bit\r
)\r
Wait the operation register's bit as specified by Bit\r
to become set (or clear).\r
\r
- @param Xhc The XHCI device.\r
+ @param Xhc The XHCI Instance.\r
@param Offset The offset of the operation register.\r
@param Bit The bit of the register to wait for.\r
@param WaitToSet Wait the bit to set or clear.\r
**/\r
EFI_STATUS\r
XhcWaitOpRegBit (\r
- IN USB_XHCI_DEV *Xhc,\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
IN UINT32 Offset,\r
IN UINT32 Bit,\r
IN BOOLEAN WaitToSet,\r
)\r
{\r
UINT32 Index;\r
+ UINTN Loop;\r
+\r
+ Loop = (Timeout * XHC_1_MILLISECOND / XHC_POLL_DELAY) + 1;\r
\r
- for (Index = 0; Index < Timeout / XHC_SYNC_POLL_INTERVAL + 1; Index++) {\r
+ for (Index = 0; Index < Loop; Index++) {\r
if (XHC_REG_BIT_IS_SET (Xhc, Offset, Bit) == WaitToSet) {\r
return EFI_SUCCESS;\r
}\r
\r
- gBS->Stall (XHC_SYNC_POLL_INTERVAL);\r
+ gBS->Stall (XHC_POLL_DELAY);\r
}\r
\r
return EFI_TIMEOUT;\r
/**\r
Set Bios Ownership\r
\r
- @param Xhc The XHCI device.\r
+ @param Xhc The XHCI Instance.\r
\r
**/\r
VOID\r
XhcSetBiosOwnership (\r
- IN USB_XHCI_DEV *Xhc\r
+ IN USB_XHCI_INSTANCE *Xhc\r
)\r
{\r
UINT32 Buffer;\r
/**\r
Clear Bios Ownership\r
\r
- @param Xhc The XHCI device.\r
+ @param Xhc The XHCI Instance.\r
\r
**/\r
VOID\r
XhcClearBiosOwnership (\r
- IN USB_XHCI_DEV *Xhc\r
+ IN USB_XHCI_INSTANCE *Xhc\r
)\r
{\r
UINT32 Buffer;\r
/**\r
Calculate the XHCI legacy support capability register offset.\r
\r
- @param Xhc The XHCI device.\r
+ @param Xhc The XHCI Instance.\r
\r
@return The offset of XHCI legacy support capability register.\r
\r
**/\r
UINT32\r
XhcGetLegSupCapAddr (\r
- IN USB_XHCI_DEV *Xhc\r
+ IN USB_XHCI_INSTANCE *Xhc\r
)\r
{\r
UINT32 ExtCapOffset;\r
/**\r
Whether the XHCI host controller is halted.\r
\r
- @param Xhc The XHCI device.\r
+ @param Xhc The XHCI Instance.\r
\r
@retval TRUE The controller is halted.\r
@retval FALSE It isn't halted.\r
**/\r
BOOLEAN\r
XhcIsHalt (\r
- IN USB_XHCI_DEV *Xhc\r
+ IN USB_XHCI_INSTANCE *Xhc\r
)\r
{\r
return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT);\r
/**\r
Whether system error occurred.\r
\r
- @param Xhc The XHCI device.\r
+ @param Xhc The XHCI Instance.\r
\r
@retval TRUE System error happened.\r
@retval FALSE No system error.\r
**/\r
BOOLEAN\r
XhcIsSysError (\r
- IN USB_XHCI_DEV *Xhc\r
+ IN USB_XHCI_INSTANCE *Xhc\r
)\r
{\r
return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HSE);\r
/**\r
Reset the XHCI host controller.\r
\r
- @param Xhc The XHCI device.\r
+ @param Xhc The XHCI Instance.\r
@param Timeout Time to wait before abort (in millisecond, ms).\r
\r
@retval EFI_SUCCESS The XHCI host controller is reset.\r
**/\r
EFI_STATUS\r
XhcResetHC (\r
- IN USB_XHCI_DEV *Xhc,\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
IN UINT32 Timeout\r
)\r
{\r
/**\r
Halt the XHCI host controller.\r
\r
- @param Xhc The XHCI device.\r
+ @param Xhc The XHCI Instance.\r
@param Timeout Time to wait before abort (in millisecond, ms).\r
\r
@return EFI_SUCCESS The XHCI host controller is halt.\r
**/\r
EFI_STATUS\r
XhcHaltHC (\r
- IN USB_XHCI_DEV *Xhc,\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
IN UINT32 Timeout\r
)\r
{\r
/**\r
Set the XHCI host controller to run.\r
\r
- @param Xhc The XHCI device.\r
+ @param Xhc The XHCI Instance.\r
@param Timeout Time to wait before abort (in millisecond, ms).\r
\r
@return EFI_SUCCESS The XHCI host controller is running.\r
**/\r
EFI_STATUS\r
XhcRunHC (\r
- IN USB_XHCI_DEV *Xhc,\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
IN UINT32 Timeout\r
)\r
{\r
projects / mirror_edk2.git / blobdiff