MdeModulePkg XhciPei: Fix build failure "conversion from 'UINT32' to 'UINT8', possibl...

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciReg.c

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
index 9d50ef824261acc357812e33a911eec017bea09b..a513dd958104ac0daa674c6054a3ba8f3035cb00 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
@@ -2,7 +2,7 @@
 \r
   The XHCI register operation routines.\r
 \r
-Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2011 - 2013, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -499,7 +499,7 @@ XhcClearOpRegBit (
   @param  Offset       The offset of the operation register.\r
   @param  Bit          The bit of the register to wait for.\r
   @param  WaitToSet    Wait the bit to set or clear.\r
-  @param  Timeout      The time to wait before abort (in millisecond, ms).\r
+  @param  Timeout      The time to wait before abort (in microsecond, us).\r
 \r
   @retval EFI_SUCCESS  The bit successfully changed by host controller.\r
   @retval EFI_TIMEOUT  The time out occurred.\r
@@ -517,7 +517,7 @@ XhcWaitOpRegBit (
   UINT32                  Index;\r
   UINTN                   Loop;\r
 \r
-  Loop   = (Timeout * XHC_1_MILLISECOND / XHC_POLL_DELAY) + 1;\r
+  Loop   = (Timeout / XHC_POLL_DELAY) + 1;\r
 \r
   for (Index = 0; Index < Loop; Index++) {\r
     if (XHC_REG_BIT_IS_SET (Xhc, Offset, Bit) == WaitToSet) {\r
@@ -543,6 +543,10 @@ XhcSetBiosOwnership (
 {\r
   UINT32                    Buffer;\r
 \r
+  if (Xhc->UsbLegSupOffset == 0xFFFFFFFF) {\r
+    return;\r
+  }\r
+\r
   DEBUG ((EFI_D_INFO, "XhcSetBiosOwnership: called to set BIOS ownership\n"));\r
 \r
   Buffer = XhcReadExtCapReg (Xhc, Xhc->UsbLegSupOffset);\r
@@ -563,6 +567,10 @@ XhcClearBiosOwnership (
 {\r
   UINT32                    Buffer;\r
 \r
+  if (Xhc->UsbLegSupOffset == 0xFFFFFFFF) {\r
+    return;\r
+  }\r
+\r
   DEBUG ((EFI_D_INFO, "XhcClearBiosOwnership: called to clear BIOS ownership\n"));\r
 \r
   Buffer = XhcReadExtCapReg (Xhc, Xhc->UsbLegSupOffset);\r
@@ -571,16 +579,18 @@ XhcClearBiosOwnership (
 }\r
 \r
 /**\r
-  Calculate the XHCI legacy support capability register offset.\r
+  Calculate the offset of the XHCI capability.\r
 \r
   @param  Xhc     The XHCI Instance.\r
+  @param  CapId   The XHCI Capability ID.\r
 \r
   @return The offset of XHCI legacy support capability register.\r
 \r
 **/\r
 UINT32\r
-XhcGetLegSupCapAddr (\r
-  IN USB_XHCI_INSTANCE    *Xhc\r
+XhcGetCapabilityAddr (\r
+  IN USB_XHCI_INSTANCE    *Xhc,\r
+  IN UINT8                CapId\r
   )\r
 {\r
   UINT32 ExtCapOffset;\r
@@ -594,7 +604,7 @@ XhcGetLegSupCapAddr (
     // Check if the extended capability register's capability id is USB Legacy Support.\r
     //\r
     Data = XhcReadExtCapReg (Xhc, ExtCapOffset);\r
-    if ((Data & 0xFF) == 0x1) {\r
+    if ((Data & 0xFF) == CapId) {\r
       return ExtCapOffset;\r
     }\r
     //\r
@@ -604,7 +614,7 @@ XhcGetLegSupCapAddr (
     ExtCapOffset += (NextExtCapReg << 2);\r
   } while (NextExtCapReg != 0);\r
 \r
-  return 0;\r
+  return 0xFFFFFFFF;\r
 }\r
 \r
 /**\r
@@ -646,7 +656,7 @@ XhcIsSysError (
   Reset the XHCI host controller.\r
 \r
   @param  Xhc          The XHCI Instance.\r
-  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
+  @param  Timeout      Time to wait before abort (in microsecond, us).\r
 \r
   @retval EFI_SUCCESS  The XHCI host controller is reset.\r
   @return Others       Failed to reset the XHCI before Timeout.\r
@@ -660,6 +670,8 @@ XhcResetHC (
 {\r
   EFI_STATUS              Status;\r
 \r
+  Status = EFI_SUCCESS;\r
+\r
   DEBUG ((EFI_D_INFO, "XhcResetHC!\n"));\r
   //\r
   // Host can only be reset when it is halt. If not so, halt it\r
@@ -672,8 +684,12 @@ XhcResetHC (
     }\r
   }\r
 \r
-  XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);\r
-  Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);\r
+  if ((Xhc->DebugCapSupOffset == 0xFFFFFFFF) || ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) != XHC_CAP_USB_DEBUG) ||\r
+      ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) == 0)) {\r
+    XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);\r
+    Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);\r
+  }\r
+\r
   return Status;\r
 }\r
 \r
@@ -682,7 +698,7 @@ XhcResetHC (
   Halt the XHCI host controller.\r
 \r
   @param  Xhc          The XHCI Instance.\r
-  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
+  @param  Timeout      Time to wait before abort (in microsecond, us).\r
 \r
   @return EFI_SUCCESS  The XHCI host controller is halt.\r
   @return EFI_TIMEOUT  Failed to halt the XHCI before Timeout.\r
@@ -706,7 +722,7 @@ XhcHaltHC (
   Set the XHCI host controller to run.\r
 \r
   @param  Xhc          The XHCI Instance.\r
-  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
+  @param  Timeout      Time to wait before abort (in microsecond, us).\r
 \r
   @return EFI_SUCCESS  The XHCI host controller is running.\r
   @return EFI_TIMEOUT  Failed to set the XHCI to run before Timeout.\r