MdeModulePkg/XhciDxe: Add access xHCI Extended Capabilities Pointer

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciReg.h

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
index 4950eed27212fd91cc46baa5f7d0bcd52f494442..5fe2ba4f0ec4585acffd5d72165670bfe04c5ab7 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
@@ -25,8 +25,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #define USB_HUB_CLASS_CODE     0x09\r
 #define USB_HUB_SUBCLASS_CODE  0x00\r
 \r
-#define XHC_CAP_USB_LEGACY  0x01\r
-#define XHC_CAP_USB_DEBUG   0x0A\r
+#define XHC_CAP_USB_LEGACY              0x01\r
+#define XHC_CAP_USB_DEBUG               0x0A\r
+#define XHC_CAP_USB_SUPPORTED_PROTOCOL  0x02\r
 \r
 // ============================================//\r
 //           XHCI register offset             //\r
@@ -74,6 +75,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #define USBLEGSP_BIOS_SEMAPHORE  BIT16           // HC BIOS Owned Semaphore\r
 #define USBLEGSP_OS_SEMAPHORE    BIT24           // HC OS Owned Semaphore\r
 \r
+//\r
+// xHCI Supported Protocol Capability\r
+//\r
+#define XHC_SUPPORTED_PROTOCOL_DW0_MAJOR_REVISION_USB2  0x02\r
+#define XHC_SUPPORTED_PROTOCOL_DW0_MAJOR_REVISION_USB3  0x03\r
+#define XHC_SUPPORTED_PROTOCOL_NAME_STRING_OFFSET       0x04\r
+#define XHC_SUPPORTED_PROTOCOL_NAME_STRING_VALUE        0x20425355\r
+#define XHC_SUPPORTED_PROTOCOL_DW2_OFFSET               0x08\r
+#define XHC_SUPPORTED_PROTOCOL_PSI_OFFSET               0x10\r
+#define XHC_SUPPORTED_PROTOCOL_USB2_HIGH_SPEED_PSIM     480\r
+#define XHC_SUPPORTED_PROTOCOL_USB2_LOW_SPEED_PSIM      1500\r
+\r
 #pragma pack (1)\r
 typedef struct {\r
   UINT8     MaxSlots;                     // Number of Device Slots\r
@@ -130,6 +143,52 @@ typedef union {
   HCCPARAMS    Data;\r
 } XHC_HCCPARAMS;\r
 \r
+//\r
+// xHCI Supported Protocol Cabability\r
+//\r
+typedef struct {\r
+  UINT8    CapId;\r
+  UINT8    NextExtCapReg;\r
+  UINT8    RevMinor;\r
+  UINT8    RevMajor;\r
+} SUPPORTED_PROTOCOL_DW0;\r
+\r
+typedef union {\r
+  UINT32                    Dword;\r
+  SUPPORTED_PROTOCOL_DW0    Data;\r
+} XHC_SUPPORTED_PROTOCOL_DW0;\r
+\r
+typedef struct {\r
+  UINT32    NameString;\r
+} XHC_SUPPORTED_PROTOCOL_DW1;\r
+\r
+typedef struct {\r
+  UINT8     CompPortOffset;\r
+  UINT8     CompPortCount;\r
+  UINT16    ProtocolDef : 12;\r
+  UINT16    Psic        : 4;\r
+} SUPPORTED_PROTOCOL_DW2;\r
+\r
+typedef union {\r
+  UINT32                    Dword;\r
+  SUPPORTED_PROTOCOL_DW2    Data;\r
+} XHC_SUPPORTED_PROTOCOL_DW2;\r
+\r
+typedef struct {\r
+  UINT16    Psiv  : 4;\r
+  UINT16    Psie  : 2;\r
+  UINT16    Plt   : 2;\r
+  UINT16    Pfd   : 1;\r
+  UINT16    RsvdP : 5;\r
+  UINT16    Lp    : 2;\r
+  UINT16    Psim;\r
+} SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID;\r
+\r
+typedef union {\r
+  UINT32                                  Dword;\r
+  SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID    Data;\r
+} XHC_SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID;\r
+\r
 #pragma pack ()\r
 \r
 //\r
@@ -546,4 +605,34 @@ XhcGetCapabilityAddr (
   IN UINT8              CapId\r
   );\r
 \r
+/**\r
+  Calculate the offset of the xHCI Supported Protocol Capability.\r
+\r
+  @param  Xhc           The XHCI Instance.\r
+  @param  MajorVersion  The USB Major Version in xHCI Support Protocol Capability Field\r
+\r
+  @return The offset of xHCI Supported Protocol capability register.\r
+\r
+**/\r
+UINT32\r
+XhcGetSupportedProtocolCapabilityAddr (\r
+  IN USB_XHCI_INSTANCE  *Xhc,\r
+  IN UINT8              MajorVersion\r
+  );\r
+\r
+/**\r
+  Find SpeedField value match with Port Speed ID value.\r
+\r
+  @param  Xhc    The XHCI Instance.\r
+  @param  Speed  The Port Speed filed in USB PortSc register\r
+\r
+  @return The USB Port Speed.\r
+\r
+**/\r
+UINT16\r
+XhcCheckUsbPortSpeedUsedPsic (\r
+  IN USB_XHCI_INSTANCE  *Xhc,\r
+  IN UINT8              Speed\r
+  );\r
+\r
 #endif\r