MdeModulePkg Xhci: Handle value 5 in Port Speed field of PORTSC

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciReg.h

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
index feef3a4bd5efd7d74e9595d44f7239c75d04c4ab..ac14b7426fe70f026a57e08c29731357bade670e 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
@@ -2,7 +2,7 @@
 \r
   This file contains the register definition of XHCI host controller.\r
 \r
-Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -171,7 +171,7 @@ typedef union {
 #define XHC_PORTSC_RESET                   BIT4  // Port Reset\r
 #define XHC_PORTSC_PLS                     (BIT5|BIT6|BIT7|BIT8)     // Port Link State\r
 #define XHC_PORTSC_PP                      BIT9  // Port Power\r
-#define XHC_PORTSC_PS                      (BIT10|BIT11|BIT12)       // Port Speed\r
+#define XHC_PORTSC_PS                      (BIT10|BIT11|BIT12|BIT13) // Port Speed\r
 #define XHC_PORTSC_LWS                     BIT16 // Port Link State Write Strobe\r
 #define XHC_PORTSC_CSC                     BIT17 // Connect Status Change\r
 #define XHC_PORTSC_PEC                     BIT18 // Port Enabled/Disabled Change\r