#ifndef _EFI_XHCI_REG_H_\r
#define _EFI_XHCI_REG_H_\r
\r
-#define PCI_IF_XHCI 0x30\r
+#define PCI_IF_XHCI 0x30\r
\r
//\r
// PCI Configuration Registers\r
//\r
-#define XHC_BAR_INDEX 0x00\r
+#define XHC_BAR_INDEX 0x00\r
\r
-#define XHC_PCI_BAR_OFFSET 0x10 // Memory Bar Register Offset\r
-#define XHC_PCI_BAR_MASK 0xFFFF // Memory Base Address Mask\r
+#define XHC_PCI_BAR_OFFSET 0x10 // Memory Bar Register Offset\r
+#define XHC_PCI_BAR_MASK 0xFFFF // Memory Base Address Mask\r
\r
-#define XHC_PCI_SBRN_OFFSET 0x60 // Serial Bus Release Number Register Offset\r
+#define XHC_PCI_SBRN_OFFSET 0x60 // Serial Bus Release Number Register Offset\r
\r
-#define USB_HUB_CLASS_CODE 0x09\r
-#define USB_HUB_SUBCLASS_CODE 0x00\r
+#define USB_HUB_CLASS_CODE 0x09\r
+#define USB_HUB_SUBCLASS_CODE 0x00\r
\r
-#define XHC_CAP_USB_LEGACY 0x01\r
-#define XHC_CAP_USB_DEBUG 0x0A\r
+#define XHC_CAP_USB_LEGACY 0x01\r
+#define XHC_CAP_USB_DEBUG 0x0A\r
\r
-//============================================//\r
+// ============================================//\r
// XHCI register offset //\r
-//============================================//\r
+// ============================================//\r
\r
//\r
// Capability registers offset\r
//\r
-#define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset\r
-#define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h\r
-#define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1\r
-#define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2\r
-#define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3\r
-#define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters\r
-#define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset\r
-#define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset\r
+#define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset\r
+#define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h\r
+#define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1\r
+#define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2\r
+#define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3\r
+#define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters\r
+#define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset\r
+#define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset\r
\r
//\r
// Operational registers offset\r
//\r
-#define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset\r
-#define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset\r
-#define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset\r
-#define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset\r
-#define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset\r
-#define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset\r
-#define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset\r
-#define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset\r
+#define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset\r
+#define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset\r
+#define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset\r
+#define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset\r
+#define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset\r
+#define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset\r
+#define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset\r
+#define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset\r
\r
//\r
// Runtime registers offset\r
//\r
-#define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset\r
-#define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset\r
-#define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset\r
-#define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset\r
-#define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset\r
-#define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset\r
+#define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset\r
+#define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset\r
+#define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset\r
+#define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset\r
+#define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset\r
+#define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset\r
\r
//\r
// Debug registers offset\r
//\r
-#define XHC_DC_DCCTRL 0x20\r
+#define XHC_DC_DCCTRL 0x20\r
\r
-#define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore\r
-#define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore\r
+#define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore\r
+#define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore\r
\r
#pragma pack (1)\r
typedef struct {\r
- UINT8 MaxSlots; // Number of Device Slots\r
- UINT16 MaxIntrs:11; // Number of Interrupters\r
- UINT16 Rsvd:5;\r
- UINT8 MaxPorts; // Number of Ports\r
+ UINT8 MaxSlots; // Number of Device Slots\r
+ UINT16 MaxIntrs : 11; // Number of Interrupters\r
+ UINT16 Rsvd : 5;\r
+ UINT8 MaxPorts; // Number of Ports\r
} HCSPARAMS1;\r
\r
//\r
// Structural Parameters 1 Register Bitmap Definition\r
//\r
typedef union {\r
- UINT32 Dword;\r
- HCSPARAMS1 Data;\r
+ UINT32 Dword;\r
+ HCSPARAMS1 Data;\r
} XHC_HCSPARAMS1;\r
\r
typedef struct {\r
- UINT32 Ist:4; // Isochronous Scheduling Threshold\r
- UINT32 Erst:4; // Event Ring Segment Table Max\r
- UINT32 Rsvd:13;\r
- UINT32 ScratchBufHi:5; // Max Scratchpad Buffers Hi\r
- UINT32 Spr:1; // Scratchpad Restore\r
- UINT32 ScratchBufLo:5; // Max Scratchpad Buffers Lo\r
+ UINT32 Ist : 4; // Isochronous Scheduling Threshold\r
+ UINT32 Erst : 4; // Event Ring Segment Table Max\r
+ UINT32 Rsvd : 13;\r
+ UINT32 ScratchBufHi : 5; // Max Scratchpad Buffers Hi\r
+ UINT32 Spr : 1; // Scratchpad Restore\r
+ UINT32 ScratchBufLo : 5; // Max Scratchpad Buffers Lo\r
} HCSPARAMS2;\r
\r
//\r
// Structural Parameters 2 Register Bitmap Definition\r
//\r
typedef union {\r
- UINT32 Dword;\r
- HCSPARAMS2 Data;\r
+ UINT32 Dword;\r
+ HCSPARAMS2 Data;\r
} XHC_HCSPARAMS2;\r
\r
typedef struct {\r
- UINT16 Ac64:1; // 64-bit Addressing Capability\r
- UINT16 Bnc:1; // BW Negotiation Capability\r
- UINT16 Csz:1; // Context Size\r
- UINT16 Ppc:1; // Port Power Control\r
- UINT16 Pind:1; // Port Indicators\r
- UINT16 Lhrc:1; // Light HC Reset Capability\r
- UINT16 Ltc:1; // Latency Tolerance Messaging Capability\r
- UINT16 Nss:1; // No Secondary SID Support\r
- UINT16 Pae:1; // Parse All Event Data\r
- UINT16 Rsvd:3;\r
- UINT16 MaxPsaSize:4; // Maximum Primary Stream Array Size\r
- UINT16 ExtCapReg; // xHCI Extended Capabilities Pointer\r
+ UINT16 Ac64 : 1; // 64-bit Addressing Capability\r
+ UINT16 Bnc : 1; // BW Negotiation Capability\r
+ UINT16 Csz : 1; // Context Size\r
+ UINT16 Ppc : 1; // Port Power Control\r
+ UINT16 Pind : 1; // Port Indicators\r
+ UINT16 Lhrc : 1; // Light HC Reset Capability\r
+ UINT16 Ltc : 1; // Latency Tolerance Messaging Capability\r
+ UINT16 Nss : 1; // No Secondary SID Support\r
+ UINT16 Pae : 1; // Parse All Event Data\r
+ UINT16 Rsvd : 3;\r
+ UINT16 MaxPsaSize : 4; // Maximum Primary Stream Array Size\r
+ UINT16 ExtCapReg; // xHCI Extended Capabilities Pointer\r
} HCCPARAMS;\r
\r
//\r
// Capability Parameters Register Bitmap Definition\r
//\r
typedef union {\r
- UINT32 Dword;\r
- HCCPARAMS Data;\r
+ UINT32 Dword;\r
+ HCCPARAMS Data;\r
} XHC_HCCPARAMS;\r
\r
#pragma pack ()\r
//\r
// Register Bit Definition\r
//\r
-#define XHC_USBCMD_RUN BIT0 // Run/Stop\r
-#define XHC_USBCMD_RESET BIT1 // Host Controller Reset\r
-#define XHC_USBCMD_INTE BIT2 // Interrupter Enable\r
-#define XHC_USBCMD_HSEE BIT3 // Host System Error Enable\r
-\r
-#define XHC_USBSTS_HALT BIT0 // Host Controller Halted\r
-#define XHC_USBSTS_HSE BIT2 // Host System Error\r
-#define XHC_USBSTS_EINT BIT3 // Event Interrupt\r
-#define XHC_USBSTS_PCD BIT4 // Port Change Detect\r
-#define XHC_USBSTS_SSS BIT8 // Save State Status\r
-#define XHC_USBSTS_RSS BIT9 // Restore State Status\r
-#define XHC_USBSTS_SRE BIT10 // Save/Restore Error\r
-#define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready\r
-#define XHC_USBSTS_HCE BIT12 // Host Controller Error\r
-\r
-#define XHC_PAGESIZE_MASK 0xFFFF // Page Size\r
-\r
-#define XHC_CRCR_RCS BIT0 // Ring Cycle State\r
-#define XHC_CRCR_CS BIT1 // Command Stop\r
-#define XHC_CRCR_CA BIT2 // Command Abort\r
-#define XHC_CRCR_CRR BIT3 // Command Ring Running\r
-\r
-#define XHC_CONFIG_MASK 0xFF // Command Ring Running\r
-\r
-#define XHC_PORTSC_CCS BIT0 // Current Connect Status\r
-#define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled\r
-#define XHC_PORTSC_OCA BIT3 // Over-current Active\r
-#define XHC_PORTSC_RESET BIT4 // Port Reset\r
-#define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State\r
-#define XHC_PORTSC_PP BIT9 // Port Power\r
-#define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13) // Port Speed\r
-#define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe\r
-#define XHC_PORTSC_CSC BIT17 // Connect Status Change\r
-#define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change\r
-#define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change\r
-#define XHC_PORTSC_OCC BIT20 // Over-Current Change\r
-#define XHC_PORTSC_PRC BIT21 // Port Reset Change\r
-#define XHC_PORTSC_PLC BIT22 // Port Link State Change\r
-#define XHC_PORTSC_CEC BIT23 // Port Config Error Change\r
-#define XHC_PORTSC_CAS BIT24 // Cold Attach Status\r
-\r
-#define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status\r
-#define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled\r
-#define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active\r
-#define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset\r
-#define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power\r
-#define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change\r
-#define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change\r
-#define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change\r
-#define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change\r
-#define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change\r
-#define XHC_IMAN_IP BIT0 // Interrupt Pending\r
-#define XHC_IMAN_IE BIT1 // Interrupt Enable\r
-\r
-#define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval\r
-#define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter\r
+#define XHC_USBCMD_RUN BIT0 // Run/Stop\r
+#define XHC_USBCMD_RESET BIT1 // Host Controller Reset\r
+#define XHC_USBCMD_INTE BIT2 // Interrupter Enable\r
+#define XHC_USBCMD_HSEE BIT3 // Host System Error Enable\r
+\r
+#define XHC_USBSTS_HALT BIT0 // Host Controller Halted\r
+#define XHC_USBSTS_HSE BIT2 // Host System Error\r
+#define XHC_USBSTS_EINT BIT3 // Event Interrupt\r
+#define XHC_USBSTS_PCD BIT4 // Port Change Detect\r
+#define XHC_USBSTS_SSS BIT8 // Save State Status\r
+#define XHC_USBSTS_RSS BIT9 // Restore State Status\r
+#define XHC_USBSTS_SRE BIT10 // Save/Restore Error\r
+#define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready\r
+#define XHC_USBSTS_HCE BIT12 // Host Controller Error\r
+\r
+#define XHC_PAGESIZE_MASK 0xFFFF // Page Size\r
+\r
+#define XHC_CRCR_RCS BIT0 // Ring Cycle State\r
+#define XHC_CRCR_CS BIT1 // Command Stop\r
+#define XHC_CRCR_CA BIT2 // Command Abort\r
+#define XHC_CRCR_CRR BIT3 // Command Ring Running\r
+\r
+#define XHC_CONFIG_MASK 0xFF // Command Ring Running\r
+\r
+#define XHC_PORTSC_CCS BIT0 // Current Connect Status\r
+#define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled\r
+#define XHC_PORTSC_OCA BIT3 // Over-current Active\r
+#define XHC_PORTSC_RESET BIT4 // Port Reset\r
+#define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State\r
+#define XHC_PORTSC_PP BIT9 // Port Power\r
+#define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13) // Port Speed\r
+#define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe\r
+#define XHC_PORTSC_CSC BIT17 // Connect Status Change\r
+#define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change\r
+#define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change\r
+#define XHC_PORTSC_OCC BIT20 // Over-Current Change\r
+#define XHC_PORTSC_PRC BIT21 // Port Reset Change\r
+#define XHC_PORTSC_PLC BIT22 // Port Link State Change\r
+#define XHC_PORTSC_CEC BIT23 // Port Config Error Change\r
+#define XHC_PORTSC_CAS BIT24 // Cold Attach Status\r
+\r
+#define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status\r
+#define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled\r
+#define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active\r
+#define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset\r
+#define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power\r
+#define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change\r
+#define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change\r
+#define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change\r
+#define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change\r
+#define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change\r
+#define XHC_IMAN_IP BIT0 // Interrupt Pending\r
+#define XHC_IMAN_IE BIT1 // Interrupt Enable\r
+\r
+#define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval\r
+#define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter\r
\r
//\r
// Hub Class Feature Selector for Clear Port Feature Request\r
// For more details, Please refer to USB 3.0 Spec Table 10-7.\r
//\r
typedef enum {\r
- Usb3PortBHPortReset = 28,\r
- Usb3PortBHPortResetChange = 29\r
+ Usb3PortBHPortReset = 28,\r
+ Usb3PortBHPortResetChange = 29\r
} XHC_PORT_FEATURE;\r
\r
//\r
// UEFI's port states.\r
//\r
typedef struct {\r
- UINT32 HwState;\r
- UINT16 UefiState;\r
+ UINT32 HwState;\r
+ UINT16 UefiState;\r
} USB_PORT_STATE_MAP;\r
\r
//\r
// Structure to map the hardware port states to feature selector for clear port feature request.\r
//\r
typedef struct {\r
- UINT32 HwState;\r
- UINT16 Selector;\r
+ UINT32 HwState;\r
+ UINT16 Selector;\r
} USB_CLEAR_PORT_MAP;\r
\r
/**\r
**/\r
UINT8\r
XhcReadCapReg8 (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT32 Offset\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT32 Offset\r
);\r
\r
/**\r
**/\r
UINT32\r
XhcReadCapReg (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT32 Offset\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT32 Offset\r
);\r
\r
/**\r
**/\r
UINT32\r
XhcReadOpReg (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT32 Offset\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT32 Offset\r
);\r
\r
/**\r
**/\r
VOID\r
XhcWriteOpReg (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT32 Offset,\r
- IN UINT32 Data\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT32 Offset,\r
+ IN UINT32 Data\r
);\r
\r
-\r
/**\r
Read XHCI runtime register.\r
\r
**/\r
UINT32\r
XhcReadRuntimeReg (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT32 Offset\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT32 Offset\r
);\r
\r
/**\r
**/\r
VOID\r
XhcWriteRuntimeReg (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT32 Offset,\r
- IN UINT32 Data\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT32 Offset,\r
+ IN UINT32 Data\r
);\r
\r
-\r
/**\r
Write the data to the XHCI door bell register.\r
\r
**/\r
VOID\r
XhcWriteDoorBellReg (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT32 Offset,\r
- IN UINT32 Data\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT32 Offset,\r
+ IN UINT32 Data\r
);\r
\r
/**\r
**/\r
VOID\r
XhcSetOpRegBit (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT32 Offset,\r
- IN UINT32 Bit\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT32 Offset,\r
+ IN UINT32 Bit\r
);\r
\r
/**\r
**/\r
VOID\r
XhcClearOpRegBit (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT32 Offset,\r
- IN UINT32 Bit\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT32 Offset,\r
+ IN UINT32 Bit\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
XhcWaitOpRegBit (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT32 Offset,\r
- IN UINT32 Bit,\r
- IN BOOLEAN WaitToSet,\r
- IN UINT32 Timeout\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT32 Offset,\r
+ IN UINT32 Bit,\r
+ IN BOOLEAN WaitToSet,\r
+ IN UINT32 Timeout\r
);\r
\r
/**\r
**/\r
UINT32\r
XhcReadRuntimeReg (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT32 Offset\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT32 Offset\r
);\r
\r
/**\r
**/\r
VOID\r
XhcWriteRuntimeReg (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT32 Offset,\r
- IN UINT32 Data\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT32 Offset,\r
+ IN UINT32 Data\r
);\r
\r
/**\r
**/\r
VOID\r
XhcSetRuntimeRegBit (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT32 Offset,\r
- IN UINT32 Bit\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT32 Offset,\r
+ IN UINT32 Bit\r
);\r
\r
/**\r
**/\r
VOID\r
XhcClearRuntimeRegBit (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT32 Offset,\r
- IN UINT32 Bit\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT32 Offset,\r
+ IN UINT32 Bit\r
);\r
\r
/**\r
**/\r
UINT32\r
XhcReadExtCapReg (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT32 Offset\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT32 Offset\r
);\r
\r
/**\r
**/\r
BOOLEAN\r
XhcIsHalt (\r
- IN USB_XHCI_INSTANCE *Xhc\r
+ IN USB_XHCI_INSTANCE *Xhc\r
);\r
\r
/**\r
**/\r
BOOLEAN\r
XhcIsSysError (\r
- IN USB_XHCI_INSTANCE *Xhc\r
+ IN USB_XHCI_INSTANCE *Xhc\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
XhcResetHC (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT32 Timeout\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT32 Timeout\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
XhcHaltHC (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT32 Timeout\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT32 Timeout\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
XhcRunHC (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT32 Timeout\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT32 Timeout\r
);\r
\r
/**\r
**/\r
UINT32\r
XhcGetCapabilityAddr (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT8 CapId\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 CapId\r
);\r
\r
#endif\r
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