\r
XHCI transfer scheduling routines.\r
\r
-Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2011 - 2012, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
// Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r
// So divide it to two 32-bytes width register access.\r
//\r
- XhcWriteRuntimeReg (Xhc, XHC_ERDP_OFFSET, Low | BIT3);\r
- XhcWriteRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4, High);\r
+ XhcWriteRuntimeReg (Xhc, XHC_ERDP_OFFSET, XHC_LOW_32BIT (EvtRing->EventRingDequeue) | BIT3);\r
+ XhcWriteRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4, XHC_HIGH_32BIT (EvtRing->EventRingDequeue));\r
}\r
\r
return EFI_SUCCESS;\r