\r
This file contains the definition for XHCI host controller schedule routines.\r
\r
-Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution. The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
-\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#define TRB_COMPLETION_TRB_ERROR 5\r
#define TRB_COMPLETION_STALL_ERROR 6\r
#define TRB_COMPLETION_SHORT_PACKET 13\r
+#define TRB_COMPLETION_STOPPED 26\r
+#define TRB_COMPLETION_STOPPED_LENGTH_INVALID 27\r
\r
//\r
// The topology string used to present usb device location\r
// Endpoint address and its capabilities\r
//\r
typedef struct _USB_ENDPOINT {\r
+ //\r
+ // Store logical device address assigned by UsbBus\r
+ // It's because some XHCI host controllers may assign the same physcial device\r
+ // address for those devices inserted at different root port.\r
+ //\r
+ UINT8 BusAddr;\r
UINT8 DevAddr;\r
UINT8 EpAddr;\r
EFI_USB_DATA_DIRECTION Direction;\r
} TRANSFER_RING;\r
\r
typedef struct _EVENT_RING {\r
- UINT32 EventInterrupter;\r
VOID *ERSTBase;\r
VOID *EventRingSeg0;\r
UINTN TrbNumber;\r
EFI_USB_DEVICE_REQUEST *Request;\r
VOID *Data;\r
UINTN DataLen;\r
+ VOID *DataPhy;\r
+ VOID *DataMap;\r
EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;\r
VOID *Context;\r
//\r
TRB_TEMPLATE *TrbStart;\r
TRB_TEMPLATE *TrbEnd;\r
UINTN TrbNum;\r
- EVENT_RING *EvtRing;\r
- TRB_TEMPLATE *EvtTrbStart;\r
+ BOOLEAN StartDone;\r
+ BOOLEAN EndDone;\r
+ BOOLEAN Finished;\r
+\r
+ TRB_TEMPLATE *EvtTrb;\r
} URB;\r
\r
//\r
\r
UINT32 TRBPtrHi;\r
\r
- UINT32 Lenth:17;\r
+ UINT32 Length:17;\r
UINT32 TDSize:5;\r
UINT32 IntTarget:10;\r
\r
UINT32 wIndex:16;\r
UINT32 wLength:16;\r
\r
- UINT32 Lenth:17;\r
+ UINT32 Length:17;\r
UINT32 RsvdZ1:5;\r
UINT32 IntTarget:10;\r
\r
\r
UINT32 TRBPtrHi;\r
\r
- UINT32 Lenth:17;\r
+ UINT32 Length:17;\r
UINT32 TDSize:5;\r
UINT32 IntTarget:10;\r
\r
\r
UINT32 TRBPtrHi;\r
\r
- UINT32 Lenth:24;\r
+ UINT32 Length:24;\r
UINT32 Completecode:8;\r
\r
UINT32 CycleBit:1;\r
UINT32 RsvdZ7;\r
} SLOT_CONTEXT;\r
\r
+typedef struct _SLOT_CONTEXT_64 {\r
+ UINT32 RouteString:20;\r
+ UINT32 Speed:4;\r
+ UINT32 RsvdZ1:1;\r
+ UINT32 MTT:1;\r
+ UINT32 Hub:1;\r
+ UINT32 ContextEntries:5;\r
+\r
+ UINT32 MaxExitLatency:16;\r
+ UINT32 RootHubPortNum:8;\r
+ UINT32 PortNum:8;\r
+\r
+ UINT32 TTHubSlotId:8;\r
+ UINT32 TTPortNum:8;\r
+ UINT32 TTT:2;\r
+ UINT32 RsvdZ2:4;\r
+ UINT32 InterTarget:10;\r
+\r
+ UINT32 DeviceAddress:8;\r
+ UINT32 RsvdZ3:19;\r
+ UINT32 SlotState:5;\r
+\r
+ UINT32 RsvdZ4;\r
+ UINT32 RsvdZ5;\r
+ UINT32 RsvdZ6;\r
+ UINT32 RsvdZ7;\r
+\r
+ UINT32 RsvdZ8;\r
+ UINT32 RsvdZ9;\r
+ UINT32 RsvdZ10;\r
+ UINT32 RsvdZ11;\r
+\r
+ UINT32 RsvdZ12;\r
+ UINT32 RsvdZ13;\r
+ UINT32 RsvdZ14;\r
+ UINT32 RsvdZ15;\r
+\r
+} SLOT_CONTEXT_64;\r
+\r
+\r
//\r
// 6.2.3 Endpoint Context\r
//\r
UINT32 RsvdZ7;\r
} ENDPOINT_CONTEXT;\r
\r
+typedef struct _ENDPOINT_CONTEXT_64 {\r
+ UINT32 EPState:3;\r
+ UINT32 RsvdZ1:5;\r
+ UINT32 Mult:2;\r
+ UINT32 MaxPStreams:5;\r
+ UINT32 LSA:1;\r
+ UINT32 Interval:8;\r
+ UINT32 RsvdZ2:8;\r
+\r
+ UINT32 RsvdZ3:1;\r
+ UINT32 CErr:2;\r
+ UINT32 EPType:3;\r
+ UINT32 RsvdZ4:1;\r
+ UINT32 HID:1;\r
+ UINT32 MaxBurstSize:8;\r
+ UINT32 MaxPacketSize:16;\r
+\r
+ UINT32 PtrLo;\r
+\r
+ UINT32 PtrHi;\r
+\r
+ UINT32 AverageTRBLength:16;\r
+ UINT32 MaxESITPayload:16;\r
+\r
+ UINT32 RsvdZ5;\r
+ UINT32 RsvdZ6;\r
+ UINT32 RsvdZ7;\r
+\r
+ UINT32 RsvdZ8;\r
+ UINT32 RsvdZ9;\r
+ UINT32 RsvdZ10;\r
+ UINT32 RsvdZ11;\r
+\r
+ UINT32 RsvdZ12;\r
+ UINT32 RsvdZ13;\r
+ UINT32 RsvdZ14;\r
+ UINT32 RsvdZ15;\r
+\r
+} ENDPOINT_CONTEXT_64;\r
+\r
+\r
//\r
// 6.2.5.1 Input Control Context\r
//\r
UINT32 RsvdZ6;\r
} INPUT_CONTRL_CONTEXT;\r
\r
+typedef struct _INPUT_CONTRL_CONTEXT_64 {\r
+ UINT32 Dword1;\r
+ UINT32 Dword2;\r
+ UINT32 RsvdZ1;\r
+ UINT32 RsvdZ2;\r
+ UINT32 RsvdZ3;\r
+ UINT32 RsvdZ4;\r
+ UINT32 RsvdZ5;\r
+ UINT32 RsvdZ6;\r
+ UINT32 RsvdZ7;\r
+ UINT32 RsvdZ8;\r
+ UINT32 RsvdZ9;\r
+ UINT32 RsvdZ10;\r
+ UINT32 RsvdZ11;\r
+ UINT32 RsvdZ12;\r
+ UINT32 RsvdZ13;\r
+ UINT32 RsvdZ14;\r
+} INPUT_CONTRL_CONTEXT_64;\r
+\r
//\r
// 6.2.1 Device Context\r
//\r
ENDPOINT_CONTEXT EP[31];\r
} DEVICE_CONTEXT;\r
\r
+typedef struct _DEVICE_CONTEXT_64 {\r
+ SLOT_CONTEXT_64 Slot;\r
+ ENDPOINT_CONTEXT_64 EP[31];\r
+} DEVICE_CONTEXT_64;\r
+\r
//\r
// 6.2.5 Input Context\r
//\r
ENDPOINT_CONTEXT EP[31];\r
} INPUT_CONTEXT;\r
\r
+typedef struct _INPUT_CONTEXT_64 {\r
+ INPUT_CONTRL_CONTEXT_64 InputControlContext;\r
+ SLOT_CONTEXT_64 Slot;\r
+ ENDPOINT_CONTEXT_64 EP[31];\r
+} INPUT_CONTEXT_64;\r
+\r
+\r
/**\r
Initialize the XHCI host controller for schedule.\r
\r
the device and endpoint.\r
\r
@param Xhc The XHCI Instance.\r
- @param DevAddr The address of the target device.\r
+ @param BusAddr The logical device address assigned by UsbBus driver.\r
@param EpNum The endpoint of the target.\r
\r
@retval EFI_SUCCESS An asynchronous transfer is removed.\r
EFI_STATUS\r
XhciDelAsyncIntTransfer (\r
IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT8 DevAddr,\r
+ IN UINT8 BusAddr,\r
IN UINT8 EpNum\r
);\r
\r
IN USB_XHCI_INSTANCE *Xhc\r
);\r
\r
+/**\r
+ Insert a single asynchronous interrupt transfer for\r
+ the device and endpoint.\r
+\r
+ @param Xhc The XHCI Instance\r
+ @param BusAddr The logical device address assigned by UsbBus driver\r
+ @param EpAddr Endpoint addrress\r
+ @param DevSpeed The device speed\r
+ @param MaxPacket The max packet length of the endpoint\r
+ @param DataLen The length of data buffer\r
+ @param Callback The function to call when data is transferred\r
+ @param Context The context to the callback\r
+\r
+ @return Created URB or NULL\r
+\r
+**/\r
+URB *\r
+XhciInsertAsyncIntTransfer (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 BusAddr,\r
+ IN UINT8 EpAddr,\r
+ IN UINT8 DevSpeed,\r
+ IN UINTN MaxPacket,\r
+ IN UINTN DataLen,\r
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r
+ IN VOID *Context\r
+ );\r
+\r
/**\r
Set Bios Ownership\r
\r
IN USB_XHCI_INSTANCE *Xhc\r
);\r
\r
-/**\r
- Find out the slot id according to device address assigned by XHCI's Address_Device cmd.\r
-\r
- @param Xhc The XHCI Instance.\r
- @param DevAddr The device address of the target device.\r
-\r
- @return The slot id used by the device.\r
-\r
-**/\r
-UINT8\r
-XhcDevAddrToSlotId (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT8 DevAddr\r
- );\r
-\r
/**\r
Find out the slot id according to the device's route string.\r
\r
IN UINT8 MTT\r
);\r
\r
+\r
+/**\r
+ Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.\r
+\r
+ @param Xhc The XHCI Instance.\r
+ @param SlotId The slot id to be configured.\r
+ @param PortNum The total number of downstream port supported by the hub.\r
+ @param TTT The TT think time of the hub device.\r
+ @param MTT The multi-TT of the hub device.\r
+\r
+ @retval EFI_SUCCESS Successfully configure the hub device's slot context.\r
+\r
+**/\r
+EFI_STATUS\r
+XhcConfigHubContext64 (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 PortNum,\r
+ IN UINT8 TTT,\r
+ IN UINT8 MTT\r
+ );\r
+\r
+\r
/**\r
Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r
\r
IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r
);\r
\r
+\r
+/**\r
+ Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r
+\r
+ @param Xhc The XHCI Instance.\r
+ @param SlotId The slot id to be configured.\r
+ @param DeviceSpeed The device's speed.\r
+ @param ConfigDesc The pointer to the usb device configuration descriptor.\r
+\r
+ @retval EFI_SUCCESS Successfully configure all the device endpoints.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+XhcSetConfigCmd64 (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 DeviceSpeed,\r
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r
+ );\r
+\r
+/**\r
+ Set interface through XHCI's Configure_Endpoint cmd.\r
+\r
+ @param Xhc The XHCI Instance.\r
+ @param SlotId The slot id to be configured.\r
+ @param DeviceSpeed The device's speed.\r
+ @param ConfigDesc The pointer to the usb device configuration descriptor.\r
+ @param Request USB device request to send.\r
+\r
+ @retval EFI_SUCCESS Successfully set interface.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+XhcSetInterface (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 DeviceSpeed,\r
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc,\r
+ IN EFI_USB_DEVICE_REQUEST *Request\r
+ );\r
+\r
+/**\r
+ Set interface through XHCI's Configure_Endpoint cmd.\r
+\r
+ @param Xhc The XHCI Instance.\r
+ @param SlotId The slot id to be configured.\r
+ @param DeviceSpeed The device's speed.\r
+ @param ConfigDesc The pointer to the usb device configuration descriptor.\r
+ @param Request USB device request to send.\r
+\r
+ @retval EFI_SUCCESS Successfully set interface.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+XhcSetInterface64 (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 DeviceSpeed,\r
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc,\r
+ IN EFI_USB_DEVICE_REQUEST *Request\r
+ );\r
+\r
/**\r
Find out the actual device address according to the requested device address from UsbBus.\r
\r
IN UINT8 DeviceSpeed\r
);\r
\r
+/**\r
+ Assign and initialize the device slot for a new device.\r
+\r
+ @param Xhc The XHCI Instance.\r
+ @param ParentRouteChart The route string pointed to the parent device.\r
+ @param ParentPort The port at which the device is located.\r
+ @param RouteChart The route string pointed to the device.\r
+ @param DeviceSpeed The device speed.\r
+\r
+ @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+XhcInitializeDeviceSlot64 (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN USB_DEV_ROUTE ParentRouteChart,\r
+ IN UINT16 ParentPort,\r
+ IN USB_DEV_ROUTE RouteChart,\r
+ IN UINT8 DeviceSpeed\r
+ );\r
+\r
/**\r
Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.\r
\r
IN UINT32 MaxPacketSize\r
);\r
\r
+\r
+/**\r
+ Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.\r
+\r
+ @param Xhc The XHCI Instance.\r
+ @param SlotId The slot id to be evaluated.\r
+ @param MaxPacketSize The max packet size supported by the device control transfer.\r
+\r
+ @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+XhcEvaluateContext64 (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT32 MaxPacketSize\r
+ );\r
+\r
+\r
/**\r
Disable the specified device slot.\r
\r
IN UINT8 SlotId\r
);\r
\r
+\r
+/**\r
+ Disable the specified device slot.\r
+\r
+ @param Xhc The XHCI Instance.\r
+ @param SlotId The slot id to be disabled.\r
+\r
+ @retval EFI_SUCCESS Successfully disable the device slot.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+XhcDisableSlotCmd64 (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId\r
+ );\r
+\r
+\r
/**\r
Synchronize the specified transfer ring to update the enqueue and dequeue pointer.\r
\r
Create XHCI event ring.\r
\r
@param Xhc The XHCI Instance.\r
- @param EventInterrupter The interrupter of event.\r
@param EventRing The created event ring.\r
\r
**/\r
VOID\r
CreateEventRing (\r
IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT8 EventInterrupter,\r
OUT EVENT_RING *EventRing\r
);\r
\r
IN URB *Urb\r
);\r
\r
+/**\r
+ System software shall use a Stop Endpoint Command (section 4.6.9) and the Set TR Dequeue Pointer\r
+ Command (section 4.6.10) to remove the timed-out TDs from the xHC transfer ring. The next write to\r
+ the Doorbell of the Endpoint will transition the Endpoint Context from the Stopped to the Running\r
+ state.\r
+\r
+ @param Xhc The XHCI Instance.\r
+ @param Urb The urb which doesn't get completed in a specified timeout range.\r
+\r
+ @retval EFI_SUCCESS The dequeuing of the TDs is successful.\r
+ @retval Others Failed to stop the endpoint and dequeue the TDs.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+XhcDequeueTrbFromEndpoint (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN URB *Urb\r
+ );\r
+\r
+/**\r
+ Stop endpoint through XHCI's Stop_Endpoint cmd.\r
+\r
+ @param Xhc The XHCI Instance.\r
+ @param SlotId The slot id to be configured.\r
+ @param Dci The device context index of endpoint.\r
+ @param PendingUrb The pending URB to check completion status when stopping the end point.\r
+\r
+ @retval EFI_SUCCESS Stop endpoint successfully.\r
+ @retval Others Failed to stop endpoint.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+XhcStopEndpoint (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 Dci,\r
+ IN URB *PendingUrb OPTIONAL\r
+ );\r
+\r
+/**\r
+ Reset endpoint through XHCI's Reset_Endpoint cmd.\r
+\r
+ @param Xhc The XHCI Instance.\r
+ @param SlotId The slot id to be configured.\r
+ @param Dci The device context index of endpoint.\r
+\r
+ @retval EFI_SUCCESS Reset endpoint successfully.\r
+ @retval Others Failed to reset endpoint.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+XhcResetEndpoint (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 Dci\r
+ );\r
+\r
+/**\r
+ Set transfer ring dequeue pointer through XHCI's Set_Tr_Dequeue_Pointer cmd.\r
+\r
+ @param Xhc The XHCI Instance.\r
+ @param SlotId The slot id to be configured.\r
+ @param Dci The device context index of endpoint.\r
+ @param Urb The dequeue pointer of the transfer ring specified\r
+ by the urb to be updated.\r
+\r
+ @retval EFI_SUCCESS Set transfer ring dequeue pointer succeeds.\r
+ @retval Others Failed to set transfer ring dequeue pointer.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+XhcSetTrDequeuePointer (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 Dci,\r
+ IN URB *Urb\r
+ );\r
+\r
/**\r
Create a new URB for a new transaction.\r
\r
IN VOID *Context\r
);\r
\r
+/**\r
+ Free an allocated URB.\r
+\r
+ @param Xhc The XHCI device.\r
+ @param Urb The URB to free.\r
+\r
+**/\r
+VOID\r
+XhcFreeUrb (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN URB *Urb\r
+ );\r
+\r
/**\r
Create a transfer TRB.\r
\r
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