This file contains the definition for XHCI host controller schedule routines.\r
\r
Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution. The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
-\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef _EFI_XHCI_SCHED_H_\r
#define _EFI_XHCI_SCHED_H_\r
\r
-#define XHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')\r
+#define XHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')\r
+#define XHC_INIT_DEVICE_SLOT_RETRIES 1\r
\r
//\r
// Transfer types, used in URB to identify the transfer type\r
//\r
-#define XHC_CTRL_TRANSFER 0x01\r
-#define XHC_BULK_TRANSFER 0x02\r
-#define XHC_INT_TRANSFER_SYNC 0x04\r
-#define XHC_INT_TRANSFER_ASYNC 0x08\r
-#define XHC_INT_ONLY_TRANSFER_ASYNC 0x10\r
+#define XHC_CTRL_TRANSFER 0x01\r
+#define XHC_BULK_TRANSFER 0x02\r
+#define XHC_INT_TRANSFER_SYNC 0x04\r
+#define XHC_INT_TRANSFER_ASYNC 0x08\r
+#define XHC_INT_ONLY_TRANSFER_ASYNC 0x10\r
\r
//\r
// 6.4.6 TRB Types\r
//\r
-#define TRB_TYPE_NORMAL 1\r
-#define TRB_TYPE_SETUP_STAGE 2\r
-#define TRB_TYPE_DATA_STAGE 3\r
-#define TRB_TYPE_STATUS_STAGE 4\r
-#define TRB_TYPE_ISOCH 5\r
-#define TRB_TYPE_LINK 6\r
-#define TRB_TYPE_EVENT_DATA 7\r
-#define TRB_TYPE_NO_OP 8\r
-#define TRB_TYPE_EN_SLOT 9\r
-#define TRB_TYPE_DIS_SLOT 10\r
-#define TRB_TYPE_ADDRESS_DEV 11\r
-#define TRB_TYPE_CON_ENDPOINT 12\r
-#define TRB_TYPE_EVALU_CONTXT 13\r
-#define TRB_TYPE_RESET_ENDPOINT 14\r
-#define TRB_TYPE_STOP_ENDPOINT 15\r
-#define TRB_TYPE_SET_TR_DEQUE 16\r
-#define TRB_TYPE_RESET_DEV 17\r
-#define TRB_TYPE_GET_PORT_BANW 21\r
-#define TRB_TYPE_FORCE_HEADER 22\r
-#define TRB_TYPE_NO_OP_COMMAND 23\r
-#define TRB_TYPE_TRANS_EVENT 32\r
-#define TRB_TYPE_COMMAND_COMPLT_EVENT 33\r
-#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34\r
-#define TRB_TYPE_HOST_CONTROLLER_EVENT 37\r
-#define TRB_TYPE_DEVICE_NOTIFI_EVENT 38\r
-#define TRB_TYPE_MFINDEX_WRAP_EVENT 39\r
+#define TRB_TYPE_NORMAL 1\r
+#define TRB_TYPE_SETUP_STAGE 2\r
+#define TRB_TYPE_DATA_STAGE 3\r
+#define TRB_TYPE_STATUS_STAGE 4\r
+#define TRB_TYPE_ISOCH 5\r
+#define TRB_TYPE_LINK 6\r
+#define TRB_TYPE_EVENT_DATA 7\r
+#define TRB_TYPE_NO_OP 8\r
+#define TRB_TYPE_EN_SLOT 9\r
+#define TRB_TYPE_DIS_SLOT 10\r
+#define TRB_TYPE_ADDRESS_DEV 11\r
+#define TRB_TYPE_CON_ENDPOINT 12\r
+#define TRB_TYPE_EVALU_CONTXT 13\r
+#define TRB_TYPE_RESET_ENDPOINT 14\r
+#define TRB_TYPE_STOP_ENDPOINT 15\r
+#define TRB_TYPE_SET_TR_DEQUE 16\r
+#define TRB_TYPE_RESET_DEV 17\r
+#define TRB_TYPE_GET_PORT_BANW 21\r
+#define TRB_TYPE_FORCE_HEADER 22\r
+#define TRB_TYPE_NO_OP_COMMAND 23\r
+#define TRB_TYPE_TRANS_EVENT 32\r
+#define TRB_TYPE_COMMAND_COMPLT_EVENT 33\r
+#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34\r
+#define TRB_TYPE_HOST_CONTROLLER_EVENT 37\r
+#define TRB_TYPE_DEVICE_NOTIFI_EVENT 38\r
+#define TRB_TYPE_MFINDEX_WRAP_EVENT 39\r
\r
//\r
// Endpoint Type (EP Type).\r
//\r
-#define ED_NOT_VALID 0\r
-#define ED_ISOCH_OUT 1\r
-#define ED_BULK_OUT 2\r
-#define ED_INTERRUPT_OUT 3\r
-#define ED_CONTROL_BIDIR 4\r
-#define ED_ISOCH_IN 5\r
-#define ED_BULK_IN 6\r
-#define ED_INTERRUPT_IN 7\r
+#define ED_NOT_VALID 0\r
+#define ED_ISOCH_OUT 1\r
+#define ED_BULK_OUT 2\r
+#define ED_INTERRUPT_OUT 3\r
+#define ED_CONTROL_BIDIR 4\r
+#define ED_ISOCH_IN 5\r
+#define ED_BULK_IN 6\r
+#define ED_INTERRUPT_IN 7\r
\r
//\r
// 6.4.5 TRB Completion Codes\r
//\r
-#define TRB_COMPLETION_INVALID 0\r
-#define TRB_COMPLETION_SUCCESS 1\r
-#define TRB_COMPLETION_DATA_BUFFER_ERROR 2\r
-#define TRB_COMPLETION_BABBLE_ERROR 3\r
-#define TRB_COMPLETION_USB_TRANSACTION_ERROR 4\r
-#define TRB_COMPLETION_TRB_ERROR 5\r
-#define TRB_COMPLETION_STALL_ERROR 6\r
-#define TRB_COMPLETION_SHORT_PACKET 13\r
-#define TRB_COMPLETION_STOPPED 26\r
-#define TRB_COMPLETION_STOPPED_LENGTH_INVALID 27\r
+#define TRB_COMPLETION_INVALID 0\r
+#define TRB_COMPLETION_SUCCESS 1\r
+#define TRB_COMPLETION_DATA_BUFFER_ERROR 2\r
+#define TRB_COMPLETION_BABBLE_ERROR 3\r
+#define TRB_COMPLETION_USB_TRANSACTION_ERROR 4\r
+#define TRB_COMPLETION_TRB_ERROR 5\r
+#define TRB_COMPLETION_STALL_ERROR 6\r
+#define TRB_COMPLETION_SHORT_PACKET 13\r
+#define TRB_COMPLETION_STOPPED 26\r
+#define TRB_COMPLETION_STOPPED_LENGTH_INVALID 27\r
\r
//\r
// The topology string used to present usb device location\r
//\r
// The tier concatenation of down stream port.\r
//\r
- UINT32 RouteString:20;\r
+ UINT32 RouteString : 20;\r
//\r
// The root port number of the chain.\r
//\r
- UINT32 RootPortNum:8;\r
+ UINT32 RootPortNum : 8;\r
//\r
// The Tier the device reside.\r
//\r
- UINT32 TierNum:4;\r
+ UINT32 TierNum : 4;\r
} USB_DEV_TOPOLOGY;\r
\r
//\r
// TRB Template\r
//\r
typedef struct _TRB_TEMPLATE {\r
- UINT32 Parameter1;\r
+ UINT32 Parameter1;\r
\r
- UINT32 Parameter2;\r
+ UINT32 Parameter2;\r
\r
- UINT32 Status;\r
+ UINT32 Status;\r
\r
- UINT32 CycleBit:1;\r
- UINT32 RsvdZ1:9;\r
- UINT32 Type:6;\r
- UINT32 Control:16;\r
+ UINT32 CycleBit : 1;\r
+ UINT32 RsvdZ1 : 9;\r
+ UINT32 Type : 6;\r
+ UINT32 Control : 16;\r
} TRB_TEMPLATE;\r
\r
typedef struct _TRANSFER_RING {\r
- VOID *RingSeg0;\r
- UINTN TrbNumber;\r
- TRB_TEMPLATE *RingEnqueue;\r
- TRB_TEMPLATE *RingDequeue;\r
- UINT32 RingPCS;\r
+ VOID *RingSeg0;\r
+ UINTN TrbNumber;\r
+ TRB_TEMPLATE *RingEnqueue;\r
+ TRB_TEMPLATE *RingDequeue;\r
+ UINT32 RingPCS;\r
} TRANSFER_RING;\r
\r
typedef struct _EVENT_RING {\r
- VOID *ERSTBase;\r
- VOID *EventRingSeg0;\r
- UINTN TrbNumber;\r
- TRB_TEMPLATE *EventRingEnqueue;\r
- TRB_TEMPLATE *EventRingDequeue;\r
- UINT32 EventRingCCS;\r
+ VOID *ERSTBase;\r
+ VOID *EventRingSeg0;\r
+ UINTN TrbNumber;\r
+ TRB_TEMPLATE *EventRingEnqueue;\r
+ TRB_TEMPLATE *EventRingDequeue;\r
+ UINT32 EventRingCCS;\r
} EVENT_RING;\r
\r
//\r
// usb requests.\r
//\r
typedef struct _URB {\r
- UINT32 Signature;\r
- LIST_ENTRY UrbList;\r
+ UINT32 Signature;\r
+ LIST_ENTRY UrbList;\r
//\r
// Usb Device URB related information\r
//\r
- USB_ENDPOINT Ep;\r
- EFI_USB_DEVICE_REQUEST *Request;\r
- VOID *Data;\r
- UINTN DataLen;\r
- VOID *DataPhy;\r
- VOID *DataMap;\r
- EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;\r
- VOID *Context;\r
+ USB_ENDPOINT Ep;\r
+ EFI_USB_DEVICE_REQUEST *Request;\r
+ VOID *Data;\r
+ UINTN DataLen;\r
+ VOID *DataPhy;\r
+ VOID *DataMap;\r
+ EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;\r
+ VOID *Context;\r
//\r
// Execute result\r
//\r
- UINT32 Result;\r
+ UINT32 Result;\r
//\r
// completed data length\r
//\r
- UINTN Completed;\r
+ UINTN Completed;\r
//\r
// Command/Tranfer Ring info\r
//\r
- TRANSFER_RING *Ring;\r
- TRB_TEMPLATE *TrbStart;\r
- TRB_TEMPLATE *TrbEnd;\r
- UINTN TrbNum;\r
- BOOLEAN StartDone;\r
- BOOLEAN EndDone;\r
- BOOLEAN Finished;\r
-\r
- TRB_TEMPLATE *EvtTrb;\r
+ TRANSFER_RING *Ring;\r
+ TRB_TEMPLATE *TrbStart;\r
+ TRB_TEMPLATE *TrbEnd;\r
+ UINTN TrbNum;\r
+ BOOLEAN StartDone;\r
+ BOOLEAN EndDone;\r
+ BOOLEAN Finished;\r
+\r
+ TRB_TEMPLATE *EvtTrb;\r
} URB;\r
\r
//\r
// is defined by the Event Ring Segment Table Base Size Register (5.5.2.3.1).\r
//\r
typedef struct _EVENT_RING_SEG_TABLE_ENTRY {\r
- UINT32 PtrLo;\r
- UINT32 PtrHi;\r
- UINT32 RingTrbSize:16;\r
- UINT32 RsvdZ1:16;\r
- UINT32 RsvdZ2;\r
+ UINT32 PtrLo;\r
+ UINT32 PtrHi;\r
+ UINT32 RingTrbSize : 16;\r
+ UINT32 RsvdZ1 : 16;\r
+ UINT32 RsvdZ2;\r
} EVENT_RING_SEG_TABLE_ENTRY;\r
\r
//\r
// Rings, and to define the Data stage information for Control Transfer Rings.\r
//\r
typedef struct _TRANSFER_TRB_NORMAL {\r
- UINT32 TRBPtrLo;\r
-\r
- UINT32 TRBPtrHi;\r
-\r
- UINT32 Length:17;\r
- UINT32 TDSize:5;\r
- UINT32 IntTarget:10;\r
-\r
- UINT32 CycleBit:1;\r
- UINT32 ENT:1;\r
- UINT32 ISP:1;\r
- UINT32 NS:1;\r
- UINT32 CH:1;\r
- UINT32 IOC:1;\r
- UINT32 IDT:1;\r
- UINT32 RsvdZ1:2;\r
- UINT32 BEI:1;\r
- UINT32 Type:6;\r
- UINT32 RsvdZ2:16;\r
+ UINT32 TRBPtrLo;\r
+\r
+ UINT32 TRBPtrHi;\r
+\r
+ UINT32 Length : 17;\r
+ UINT32 TDSize : 5;\r
+ UINT32 IntTarget : 10;\r
+\r
+ UINT32 CycleBit : 1;\r
+ UINT32 ENT : 1;\r
+ UINT32 ISP : 1;\r
+ UINT32 NS : 1;\r
+ UINT32 CH : 1;\r
+ UINT32 IOC : 1;\r
+ UINT32 IDT : 1;\r
+ UINT32 RsvdZ1 : 2;\r
+ UINT32 BEI : 1;\r
+ UINT32 Type : 6;\r
+ UINT32 RsvdZ2 : 16;\r
} TRANSFER_TRB_NORMAL;\r
\r
//\r
// A Setup Stage TRB is created by system software to initiate a USB Setup packet on a control endpoint.\r
//\r
typedef struct _TRANSFER_TRB_CONTROL_SETUP {\r
- UINT32 bmRequestType:8;\r
- UINT32 bRequest:8;\r
- UINT32 wValue:16;\r
-\r
- UINT32 wIndex:16;\r
- UINT32 wLength:16;\r
-\r
- UINT32 Length:17;\r
- UINT32 RsvdZ1:5;\r
- UINT32 IntTarget:10;\r
-\r
- UINT32 CycleBit:1;\r
- UINT32 RsvdZ2:4;\r
- UINT32 IOC:1;\r
- UINT32 IDT:1;\r
- UINT32 RsvdZ3:3;\r
- UINT32 Type:6;\r
- UINT32 TRT:2;\r
- UINT32 RsvdZ4:14;\r
+ UINT32 bmRequestType : 8;\r
+ UINT32 bRequest : 8;\r
+ UINT32 wValue : 16;\r
+\r
+ UINT32 wIndex : 16;\r
+ UINT32 wLength : 16;\r
+\r
+ UINT32 Length : 17;\r
+ UINT32 RsvdZ1 : 5;\r
+ UINT32 IntTarget : 10;\r
+\r
+ UINT32 CycleBit : 1;\r
+ UINT32 RsvdZ2 : 4;\r
+ UINT32 IOC : 1;\r
+ UINT32 IDT : 1;\r
+ UINT32 RsvdZ3 : 3;\r
+ UINT32 Type : 6;\r
+ UINT32 TRT : 2;\r
+ UINT32 RsvdZ4 : 14;\r
} TRANSFER_TRB_CONTROL_SETUP;\r
\r
//\r
// A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.\r
//\r
typedef struct _TRANSFER_TRB_CONTROL_DATA {\r
- UINT32 TRBPtrLo;\r
-\r
- UINT32 TRBPtrHi;\r
-\r
- UINT32 Length:17;\r
- UINT32 TDSize:5;\r
- UINT32 IntTarget:10;\r
-\r
- UINT32 CycleBit:1;\r
- UINT32 ENT:1;\r
- UINT32 ISP:1;\r
- UINT32 NS:1;\r
- UINT32 CH:1;\r
- UINT32 IOC:1;\r
- UINT32 IDT:1;\r
- UINT32 RsvdZ1:3;\r
- UINT32 Type:6;\r
- UINT32 DIR:1;\r
- UINT32 RsvdZ2:15;\r
+ UINT32 TRBPtrLo;\r
+\r
+ UINT32 TRBPtrHi;\r
+\r
+ UINT32 Length : 17;\r
+ UINT32 TDSize : 5;\r
+ UINT32 IntTarget : 10;\r
+\r
+ UINT32 CycleBit : 1;\r
+ UINT32 ENT : 1;\r
+ UINT32 ISP : 1;\r
+ UINT32 NS : 1;\r
+ UINT32 CH : 1;\r
+ UINT32 IOC : 1;\r
+ UINT32 IDT : 1;\r
+ UINT32 RsvdZ1 : 3;\r
+ UINT32 Type : 6;\r
+ UINT32 DIR : 1;\r
+ UINT32 RsvdZ2 : 15;\r
} TRANSFER_TRB_CONTROL_DATA;\r
\r
//\r
// A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.\r
//\r
typedef struct _TRANSFER_TRB_CONTROL_STATUS {\r
- UINT32 RsvdZ1;\r
- UINT32 RsvdZ2;\r
-\r
- UINT32 RsvdZ3:22;\r
- UINT32 IntTarget:10;\r
-\r
- UINT32 CycleBit:1;\r
- UINT32 ENT:1;\r
- UINT32 RsvdZ4:2;\r
- UINT32 CH:1;\r
- UINT32 IOC:1;\r
- UINT32 RsvdZ5:4;\r
- UINT32 Type:6;\r
- UINT32 DIR:1;\r
- UINT32 RsvdZ6:15;\r
+ UINT32 RsvdZ1;\r
+ UINT32 RsvdZ2;\r
+\r
+ UINT32 RsvdZ3 : 22;\r
+ UINT32 IntTarget : 10;\r
+\r
+ UINT32 CycleBit : 1;\r
+ UINT32 ENT : 1;\r
+ UINT32 RsvdZ4 : 2;\r
+ UINT32 CH : 1;\r
+ UINT32 IOC : 1;\r
+ UINT32 RsvdZ5 : 4;\r
+ UINT32 Type : 6;\r
+ UINT32 DIR : 1;\r
+ UINT32 RsvdZ6 : 15;\r
} TRANSFER_TRB_CONTROL_STATUS;\r
\r
//\r
// for more information on the use and operation of Transfer Events.\r
//\r
typedef struct _EVT_TRB_TRANSFER {\r
- UINT32 TRBPtrLo;\r
+ UINT32 TRBPtrLo;\r
\r
- UINT32 TRBPtrHi;\r
+ UINT32 TRBPtrHi;\r
\r
- UINT32 Length:24;\r
- UINT32 Completecode:8;\r
+ UINT32 Length : 24;\r
+ UINT32 Completecode : 8;\r
\r
- UINT32 CycleBit:1;\r
- UINT32 RsvdZ1:1;\r
- UINT32 ED:1;\r
- UINT32 RsvdZ2:7;\r
- UINT32 Type:6;\r
- UINT32 EndpointId:5;\r
- UINT32 RsvdZ3:3;\r
- UINT32 SlotId:8;\r
+ UINT32 CycleBit : 1;\r
+ UINT32 RsvdZ1 : 1;\r
+ UINT32 ED : 1;\r
+ UINT32 RsvdZ2 : 7;\r
+ UINT32 Type : 6;\r
+ UINT32 EndpointId : 5;\r
+ UINT32 RsvdZ3 : 3;\r
+ UINT32 SlotId : 8;\r
} EVT_TRB_TRANSFER;\r
\r
//\r
// Command Ring. Refer to section 4.11.4 for more information on the use of Command Completion Events.\r
//\r
typedef struct _EVT_TRB_COMMAND_COMPLETION {\r
- UINT32 TRBPtrLo;\r
+ UINT32 TRBPtrLo;\r
\r
- UINT32 TRBPtrHi;\r
+ UINT32 TRBPtrHi;\r
\r
- UINT32 RsvdZ2:24;\r
- UINT32 Completecode:8;\r
+ UINT32 RsvdZ2 : 24;\r
+ UINT32 Completecode : 8;\r
\r
- UINT32 CycleBit:1;\r
- UINT32 RsvdZ3:9;\r
- UINT32 Type:6;\r
- UINT32 VFID:8;\r
- UINT32 SlotId:8;\r
+ UINT32 CycleBit : 1;\r
+ UINT32 RsvdZ3 : 9;\r
+ UINT32 Type : 6;\r
+ UINT32 VFID : 8;\r
+ UINT32 SlotId : 8;\r
} EVT_TRB_COMMAND_COMPLETION;\r
\r
typedef union _TRB {\r
- TRB_TEMPLATE TrbTemplate;\r
- TRANSFER_TRB_NORMAL TrbNormal;\r
- TRANSFER_TRB_CONTROL_SETUP TrbCtrSetup;\r
- TRANSFER_TRB_CONTROL_DATA TrbCtrData;\r
- TRANSFER_TRB_CONTROL_STATUS TrbCtrStatus;\r
+ TRB_TEMPLATE TrbTemplate;\r
+ TRANSFER_TRB_NORMAL TrbNormal;\r
+ TRANSFER_TRB_CONTROL_SETUP TrbCtrSetup;\r
+ TRANSFER_TRB_CONTROL_DATA TrbCtrData;\r
+ TRANSFER_TRB_CONTROL_STATUS TrbCtrStatus;\r
} TRB;\r
\r
//\r
// mechanisms offered by the xHCI.\r
//\r
typedef struct _CMD_TRB_NO_OP {\r
- UINT32 RsvdZ0;\r
- UINT32 RsvdZ1;\r
- UINT32 RsvdZ2;\r
-\r
- UINT32 CycleBit:1;\r
- UINT32 RsvdZ3:9;\r
- UINT32 Type:6;\r
- UINT32 RsvdZ4:16;\r
+ UINT32 RsvdZ0;\r
+ UINT32 RsvdZ1;\r
+ UINT32 RsvdZ2;\r
+\r
+ UINT32 CycleBit : 1;\r
+ UINT32 RsvdZ3 : 9;\r
+ UINT32 Type : 6;\r
+ UINT32 RsvdZ4 : 16;\r
} CMD_TRB_NO_OP;\r
\r
//\r
// selected slot to the host in a Command Completion Event.\r
//\r
typedef struct _CMD_TRB_ENABLE_SLOT {\r
- UINT32 RsvdZ0;\r
- UINT32 RsvdZ1;\r
- UINT32 RsvdZ2;\r
-\r
- UINT32 CycleBit:1;\r
- UINT32 RsvdZ3:9;\r
- UINT32 Type:6;\r
- UINT32 RsvdZ4:16;\r
+ UINT32 RsvdZ0;\r
+ UINT32 RsvdZ1;\r
+ UINT32 RsvdZ2;\r
+\r
+ UINT32 CycleBit : 1;\r
+ UINT32 RsvdZ3 : 9;\r
+ UINT32 Type : 6;\r
+ UINT32 RsvdZ4 : 16;\r
} CMD_TRB_ENABLE_SLOT;\r
\r
//\r
// internal xHC resources assigned to the slot.\r
//\r
typedef struct _CMD_TRB_DISABLE_SLOT {\r
- UINT32 RsvdZ0;\r
- UINT32 RsvdZ1;\r
- UINT32 RsvdZ2;\r
-\r
- UINT32 CycleBit:1;\r
- UINT32 RsvdZ3:9;\r
- UINT32 Type:6;\r
- UINT32 RsvdZ4:8;\r
- UINT32 SlotId:8;\r
+ UINT32 RsvdZ0;\r
+ UINT32 RsvdZ1;\r
+ UINT32 RsvdZ2;\r
+\r
+ UINT32 CycleBit : 1;\r
+ UINT32 RsvdZ3 : 9;\r
+ UINT32 Type : 6;\r
+ UINT32 RsvdZ4 : 8;\r
+ UINT32 SlotId : 8;\r
} CMD_TRB_DISABLE_SLOT;\r
\r
//\r
// issue a SET_ADDRESS request to the USB device.\r
//\r
typedef struct _CMD_TRB_ADDRESS_DEVICE {\r
- UINT32 PtrLo;\r
+ UINT32 PtrLo;\r
\r
- UINT32 PtrHi;\r
+ UINT32 PtrHi;\r
\r
- UINT32 RsvdZ1;\r
+ UINT32 RsvdZ1;\r
\r
- UINT32 CycleBit:1;\r
- UINT32 RsvdZ2:8;\r
- UINT32 BSR:1;\r
- UINT32 Type:6;\r
- UINT32 RsvdZ3:8;\r
- UINT32 SlotId:8;\r
+ UINT32 CycleBit : 1;\r
+ UINT32 RsvdZ2 : 8;\r
+ UINT32 BSR : 1;\r
+ UINT32 Type : 6;\r
+ UINT32 RsvdZ3 : 8;\r
+ UINT32 SlotId : 8;\r
} CMD_TRB_ADDRESS_DEVICE;\r
\r
//\r
// endpoints selected by the command.\r
//\r
typedef struct _CMD_TRB_CONFIG_ENDPOINT {\r
- UINT32 PtrLo;\r
+ UINT32 PtrLo;\r
\r
- UINT32 PtrHi;\r
+ UINT32 PtrHi;\r
\r
- UINT32 RsvdZ1;\r
+ UINT32 RsvdZ1;\r
\r
- UINT32 CycleBit:1;\r
- UINT32 RsvdZ2:8;\r
- UINT32 DC:1;\r
- UINT32 Type:6;\r
- UINT32 RsvdZ3:8;\r
- UINT32 SlotId:8;\r
+ UINT32 CycleBit : 1;\r
+ UINT32 RsvdZ2 : 8;\r
+ UINT32 DC : 1;\r
+ UINT32 Type : 6;\r
+ UINT32 RsvdZ3 : 8;\r
+ UINT32 SlotId : 8;\r
} CMD_TRB_CONFIG_ENDPOINT;\r
\r
//\r
// shall evaluate any changes\r
//\r
typedef struct _CMD_TRB_EVALUATE_CONTEXT {\r
- UINT32 PtrLo;\r
+ UINT32 PtrLo;\r
\r
- UINT32 PtrHi;\r
+ UINT32 PtrHi;\r
\r
- UINT32 RsvdZ1;\r
+ UINT32 RsvdZ1;\r
\r
- UINT32 CycleBit:1;\r
- UINT32 RsvdZ2:9;\r
- UINT32 Type:6;\r
- UINT32 RsvdZ3:8;\r
- UINT32 SlotId:8;\r
+ UINT32 CycleBit : 1;\r
+ UINT32 RsvdZ2 : 9;\r
+ UINT32 Type : 6;\r
+ UINT32 RsvdZ3 : 8;\r
+ UINT32 SlotId : 8;\r
} CMD_TRB_EVALUATE_CONTEXT;\r
\r
//\r
// The Reset Endpoint Command TRB is used by system software to reset a specified Transfer Ring\r
//\r
typedef struct _CMD_TRB_RESET_ENDPOINT {\r
- UINT32 RsvdZ0;\r
- UINT32 RsvdZ1;\r
- UINT32 RsvdZ2;\r
-\r
- UINT32 CycleBit:1;\r
- UINT32 RsvdZ3:8;\r
- UINT32 TSP:1;\r
- UINT32 Type:6;\r
- UINT32 EDID:5;\r
- UINT32 RsvdZ4:3;\r
- UINT32 SlotId:8;\r
+ UINT32 RsvdZ0;\r
+ UINT32 RsvdZ1;\r
+ UINT32 RsvdZ2;\r
+\r
+ UINT32 CycleBit : 1;\r
+ UINT32 RsvdZ3 : 8;\r
+ UINT32 TSP : 1;\r
+ UINT32 Type : 6;\r
+ UINT32 EDID : 5;\r
+ UINT32 RsvdZ4 : 3;\r
+ UINT32 SlotId : 8;\r
} CMD_TRB_RESET_ENDPOINT;\r
\r
//\r
// Transfer Ring and temporarily take ownership of TDs that had previously been passed to the xHC.\r
//\r
typedef struct _CMD_TRB_STOP_ENDPOINT {\r
- UINT32 RsvdZ0;\r
- UINT32 RsvdZ1;\r
- UINT32 RsvdZ2;\r
-\r
- UINT32 CycleBit:1;\r
- UINT32 RsvdZ3:9;\r
- UINT32 Type:6;\r
- UINT32 EDID:5;\r
- UINT32 RsvdZ4:2;\r
- UINT32 SP:1;\r
- UINT32 SlotId:8;\r
+ UINT32 RsvdZ0;\r
+ UINT32 RsvdZ1;\r
+ UINT32 RsvdZ2;\r
+\r
+ UINT32 CycleBit : 1;\r
+ UINT32 RsvdZ3 : 9;\r
+ UINT32 Type : 6;\r
+ UINT32 EDID : 5;\r
+ UINT32 RsvdZ4 : 2;\r
+ UINT32 SP : 1;\r
+ UINT32 SlotId : 8;\r
} CMD_TRB_STOP_ENDPOINT;\r
\r
//\r
// Pointer and DCS fields of an Endpoint or Stream Context.\r
//\r
typedef struct _CMD_SET_TR_DEQ_POINTER {\r
- UINT32 PtrLo;\r
+ UINT32 PtrLo;\r
\r
- UINT32 PtrHi;\r
+ UINT32 PtrHi;\r
\r
- UINT32 RsvdZ1:16;\r
- UINT32 StreamID:16;\r
+ UINT32 RsvdZ1 : 16;\r
+ UINT32 StreamID : 16;\r
\r
- UINT32 CycleBit:1;\r
- UINT32 RsvdZ2:9;\r
- UINT32 Type:6;\r
- UINT32 Endpoint:5;\r
- UINT32 RsvdZ3:3;\r
- UINT32 SlotId:8;\r
+ UINT32 CycleBit : 1;\r
+ UINT32 RsvdZ2 : 9;\r
+ UINT32 Type : 6;\r
+ UINT32 Endpoint : 5;\r
+ UINT32 RsvdZ3 : 3;\r
+ UINT32 SlotId : 8;\r
} CMD_SET_TR_DEQ_POINTER;\r
\r
//\r
// A Link TRB provides support for non-contiguous TRB Rings.\r
//\r
typedef struct _LINK_TRB {\r
- UINT32 PtrLo;\r
+ UINT32 PtrLo;\r
\r
- UINT32 PtrHi;\r
+ UINT32 PtrHi;\r
\r
- UINT32 RsvdZ1:22;\r
- UINT32 InterTarget:10;\r
+ UINT32 RsvdZ1 : 22;\r
+ UINT32 InterTarget : 10;\r
\r
- UINT32 CycleBit:1;\r
- UINT32 TC:1;\r
- UINT32 RsvdZ2:2;\r
- UINT32 CH:1;\r
- UINT32 IOC:1;\r
- UINT32 RsvdZ3:4;\r
- UINT32 Type:6;\r
- UINT32 RsvdZ4:16;\r
+ UINT32 CycleBit : 1;\r
+ UINT32 TC : 1;\r
+ UINT32 RsvdZ2 : 2;\r
+ UINT32 CH : 1;\r
+ UINT32 IOC : 1;\r
+ UINT32 RsvdZ3 : 4;\r
+ UINT32 Type : 6;\r
+ UINT32 RsvdZ4 : 16;\r
} LINK_TRB;\r
\r
//\r
// 6.2.2 Slot Context\r
//\r
typedef struct _SLOT_CONTEXT {\r
- UINT32 RouteString:20;\r
- UINT32 Speed:4;\r
- UINT32 RsvdZ1:1;\r
- UINT32 MTT:1;\r
- UINT32 Hub:1;\r
- UINT32 ContextEntries:5;\r
-\r
- UINT32 MaxExitLatency:16;\r
- UINT32 RootHubPortNum:8;\r
- UINT32 PortNum:8;\r
-\r
- UINT32 TTHubSlotId:8;\r
- UINT32 TTPortNum:8;\r
- UINT32 TTT:2;\r
- UINT32 RsvdZ2:4;\r
- UINT32 InterTarget:10;\r
-\r
- UINT32 DeviceAddress:8;\r
- UINT32 RsvdZ3:19;\r
- UINT32 SlotState:5;\r
-\r
- UINT32 RsvdZ4;\r
- UINT32 RsvdZ5;\r
- UINT32 RsvdZ6;\r
- UINT32 RsvdZ7;\r
+ UINT32 RouteString : 20;\r
+ UINT32 Speed : 4;\r
+ UINT32 RsvdZ1 : 1;\r
+ UINT32 MTT : 1;\r
+ UINT32 Hub : 1;\r
+ UINT32 ContextEntries : 5;\r
+\r
+ UINT32 MaxExitLatency : 16;\r
+ UINT32 RootHubPortNum : 8;\r
+ UINT32 PortNum : 8;\r
+\r
+ UINT32 TTHubSlotId : 8;\r
+ UINT32 TTPortNum : 8;\r
+ UINT32 TTT : 2;\r
+ UINT32 RsvdZ2 : 4;\r
+ UINT32 InterTarget : 10;\r
+\r
+ UINT32 DeviceAddress : 8;\r
+ UINT32 RsvdZ3 : 19;\r
+ UINT32 SlotState : 5;\r
+\r
+ UINT32 RsvdZ4;\r
+ UINT32 RsvdZ5;\r
+ UINT32 RsvdZ6;\r
+ UINT32 RsvdZ7;\r
} SLOT_CONTEXT;\r
\r
typedef struct _SLOT_CONTEXT_64 {\r
- UINT32 RouteString:20;\r
- UINT32 Speed:4;\r
- UINT32 RsvdZ1:1;\r
- UINT32 MTT:1;\r
- UINT32 Hub:1;\r
- UINT32 ContextEntries:5;\r
-\r
- UINT32 MaxExitLatency:16;\r
- UINT32 RootHubPortNum:8;\r
- UINT32 PortNum:8;\r
-\r
- UINT32 TTHubSlotId:8;\r
- UINT32 TTPortNum:8;\r
- UINT32 TTT:2;\r
- UINT32 RsvdZ2:4;\r
- UINT32 InterTarget:10;\r
-\r
- UINT32 DeviceAddress:8;\r
- UINT32 RsvdZ3:19;\r
- UINT32 SlotState:5;\r
-\r
- UINT32 RsvdZ4;\r
- UINT32 RsvdZ5;\r
- UINT32 RsvdZ6;\r
- UINT32 RsvdZ7;\r
-\r
- UINT32 RsvdZ8;\r
- UINT32 RsvdZ9;\r
- UINT32 RsvdZ10;\r
- UINT32 RsvdZ11;\r
-\r
- UINT32 RsvdZ12;\r
- UINT32 RsvdZ13;\r
- UINT32 RsvdZ14;\r
- UINT32 RsvdZ15;\r
-\r
+ UINT32 RouteString : 20;\r
+ UINT32 Speed : 4;\r
+ UINT32 RsvdZ1 : 1;\r
+ UINT32 MTT : 1;\r
+ UINT32 Hub : 1;\r
+ UINT32 ContextEntries : 5;\r
+\r
+ UINT32 MaxExitLatency : 16;\r
+ UINT32 RootHubPortNum : 8;\r
+ UINT32 PortNum : 8;\r
+\r
+ UINT32 TTHubSlotId : 8;\r
+ UINT32 TTPortNum : 8;\r
+ UINT32 TTT : 2;\r
+ UINT32 RsvdZ2 : 4;\r
+ UINT32 InterTarget : 10;\r
+\r
+ UINT32 DeviceAddress : 8;\r
+ UINT32 RsvdZ3 : 19;\r
+ UINT32 SlotState : 5;\r
+\r
+ UINT32 RsvdZ4;\r
+ UINT32 RsvdZ5;\r
+ UINT32 RsvdZ6;\r
+ UINT32 RsvdZ7;\r
+\r
+ UINT32 RsvdZ8;\r
+ UINT32 RsvdZ9;\r
+ UINT32 RsvdZ10;\r
+ UINT32 RsvdZ11;\r
+\r
+ UINT32 RsvdZ12;\r
+ UINT32 RsvdZ13;\r
+ UINT32 RsvdZ14;\r
+ UINT32 RsvdZ15;\r
} SLOT_CONTEXT_64;\r
\r
-\r
//\r
// 6.2.3 Endpoint Context\r
//\r
typedef struct _ENDPOINT_CONTEXT {\r
- UINT32 EPState:3;\r
- UINT32 RsvdZ1:5;\r
- UINT32 Mult:2;\r
- UINT32 MaxPStreams:5;\r
- UINT32 LSA:1;\r
- UINT32 Interval:8;\r
- UINT32 RsvdZ2:8;\r
-\r
- UINT32 RsvdZ3:1;\r
- UINT32 CErr:2;\r
- UINT32 EPType:3;\r
- UINT32 RsvdZ4:1;\r
- UINT32 HID:1;\r
- UINT32 MaxBurstSize:8;\r
- UINT32 MaxPacketSize:16;\r
-\r
- UINT32 PtrLo;\r
-\r
- UINT32 PtrHi;\r
-\r
- UINT32 AverageTRBLength:16;\r
- UINT32 MaxESITPayload:16;\r
-\r
- UINT32 RsvdZ5;\r
- UINT32 RsvdZ6;\r
- UINT32 RsvdZ7;\r
+ UINT32 EPState : 3;\r
+ UINT32 RsvdZ1 : 5;\r
+ UINT32 Mult : 2;\r
+ UINT32 MaxPStreams : 5;\r
+ UINT32 LSA : 1;\r
+ UINT32 Interval : 8;\r
+ UINT32 RsvdZ2 : 8;\r
+\r
+ UINT32 RsvdZ3 : 1;\r
+ UINT32 CErr : 2;\r
+ UINT32 EPType : 3;\r
+ UINT32 RsvdZ4 : 1;\r
+ UINT32 HID : 1;\r
+ UINT32 MaxBurstSize : 8;\r
+ UINT32 MaxPacketSize : 16;\r
+\r
+ UINT32 PtrLo;\r
+\r
+ UINT32 PtrHi;\r
+\r
+ UINT32 AverageTRBLength : 16;\r
+ UINT32 MaxESITPayload : 16;\r
+\r
+ UINT32 RsvdZ5;\r
+ UINT32 RsvdZ6;\r
+ UINT32 RsvdZ7;\r
} ENDPOINT_CONTEXT;\r
\r
typedef struct _ENDPOINT_CONTEXT_64 {\r
- UINT32 EPState:3;\r
- UINT32 RsvdZ1:5;\r
- UINT32 Mult:2;\r
- UINT32 MaxPStreams:5;\r
- UINT32 LSA:1;\r
- UINT32 Interval:8;\r
- UINT32 RsvdZ2:8;\r
-\r
- UINT32 RsvdZ3:1;\r
- UINT32 CErr:2;\r
- UINT32 EPType:3;\r
- UINT32 RsvdZ4:1;\r
- UINT32 HID:1;\r
- UINT32 MaxBurstSize:8;\r
- UINT32 MaxPacketSize:16;\r
-\r
- UINT32 PtrLo;\r
-\r
- UINT32 PtrHi;\r
-\r
- UINT32 AverageTRBLength:16;\r
- UINT32 MaxESITPayload:16;\r
-\r
- UINT32 RsvdZ5;\r
- UINT32 RsvdZ6;\r
- UINT32 RsvdZ7;\r
-\r
- UINT32 RsvdZ8;\r
- UINT32 RsvdZ9;\r
- UINT32 RsvdZ10;\r
- UINT32 RsvdZ11;\r
-\r
- UINT32 RsvdZ12;\r
- UINT32 RsvdZ13;\r
- UINT32 RsvdZ14;\r
- UINT32 RsvdZ15;\r
-\r
+ UINT32 EPState : 3;\r
+ UINT32 RsvdZ1 : 5;\r
+ UINT32 Mult : 2;\r
+ UINT32 MaxPStreams : 5;\r
+ UINT32 LSA : 1;\r
+ UINT32 Interval : 8;\r
+ UINT32 RsvdZ2 : 8;\r
+\r
+ UINT32 RsvdZ3 : 1;\r
+ UINT32 CErr : 2;\r
+ UINT32 EPType : 3;\r
+ UINT32 RsvdZ4 : 1;\r
+ UINT32 HID : 1;\r
+ UINT32 MaxBurstSize : 8;\r
+ UINT32 MaxPacketSize : 16;\r
+\r
+ UINT32 PtrLo;\r
+\r
+ UINT32 PtrHi;\r
+\r
+ UINT32 AverageTRBLength : 16;\r
+ UINT32 MaxESITPayload : 16;\r
+\r
+ UINT32 RsvdZ5;\r
+ UINT32 RsvdZ6;\r
+ UINT32 RsvdZ7;\r
+\r
+ UINT32 RsvdZ8;\r
+ UINT32 RsvdZ9;\r
+ UINT32 RsvdZ10;\r
+ UINT32 RsvdZ11;\r
+\r
+ UINT32 RsvdZ12;\r
+ UINT32 RsvdZ13;\r
+ UINT32 RsvdZ14;\r
+ UINT32 RsvdZ15;\r
} ENDPOINT_CONTEXT_64;\r
\r
-\r
//\r
// 6.2.5.1 Input Control Context\r
//\r
typedef struct _INPUT_CONTRL_CONTEXT {\r
- UINT32 Dword1;\r
- UINT32 Dword2;\r
- UINT32 RsvdZ1;\r
- UINT32 RsvdZ2;\r
- UINT32 RsvdZ3;\r
- UINT32 RsvdZ4;\r
- UINT32 RsvdZ5;\r
- UINT32 RsvdZ6;\r
+ UINT32 Dword1;\r
+ UINT32 Dword2;\r
+ UINT32 RsvdZ1;\r
+ UINT32 RsvdZ2;\r
+ UINT32 RsvdZ3;\r
+ UINT32 RsvdZ4;\r
+ UINT32 RsvdZ5;\r
+ UINT32 RsvdZ6;\r
} INPUT_CONTRL_CONTEXT;\r
\r
typedef struct _INPUT_CONTRL_CONTEXT_64 {\r
- UINT32 Dword1;\r
- UINT32 Dword2;\r
- UINT32 RsvdZ1;\r
- UINT32 RsvdZ2;\r
- UINT32 RsvdZ3;\r
- UINT32 RsvdZ4;\r
- UINT32 RsvdZ5;\r
- UINT32 RsvdZ6;\r
- UINT32 RsvdZ7;\r
- UINT32 RsvdZ8;\r
- UINT32 RsvdZ9;\r
- UINT32 RsvdZ10;\r
- UINT32 RsvdZ11;\r
- UINT32 RsvdZ12;\r
- UINT32 RsvdZ13;\r
- UINT32 RsvdZ14;\r
+ UINT32 Dword1;\r
+ UINT32 Dword2;\r
+ UINT32 RsvdZ1;\r
+ UINT32 RsvdZ2;\r
+ UINT32 RsvdZ3;\r
+ UINT32 RsvdZ4;\r
+ UINT32 RsvdZ5;\r
+ UINT32 RsvdZ6;\r
+ UINT32 RsvdZ7;\r
+ UINT32 RsvdZ8;\r
+ UINT32 RsvdZ9;\r
+ UINT32 RsvdZ10;\r
+ UINT32 RsvdZ11;\r
+ UINT32 RsvdZ12;\r
+ UINT32 RsvdZ13;\r
+ UINT32 RsvdZ14;\r
} INPUT_CONTRL_CONTEXT_64;\r
\r
//\r
// 6.2.1 Device Context\r
//\r
typedef struct _DEVICE_CONTEXT {\r
- SLOT_CONTEXT Slot;\r
- ENDPOINT_CONTEXT EP[31];\r
+ SLOT_CONTEXT Slot;\r
+ ENDPOINT_CONTEXT EP[31];\r
} DEVICE_CONTEXT;\r
\r
typedef struct _DEVICE_CONTEXT_64 {\r
- SLOT_CONTEXT_64 Slot;\r
- ENDPOINT_CONTEXT_64 EP[31];\r
+ SLOT_CONTEXT_64 Slot;\r
+ ENDPOINT_CONTEXT_64 EP[31];\r
} DEVICE_CONTEXT_64;\r
\r
//\r
} INPUT_CONTEXT;\r
\r
typedef struct _INPUT_CONTEXT_64 {\r
- INPUT_CONTRL_CONTEXT_64 InputControlContext;\r
- SLOT_CONTEXT_64 Slot;\r
- ENDPOINT_CONTEXT_64 EP[31];\r
+ INPUT_CONTRL_CONTEXT_64 InputControlContext;\r
+ SLOT_CONTEXT_64 Slot;\r
+ ENDPOINT_CONTEXT_64 EP[31];\r
} INPUT_CONTEXT_64;\r
\r
-\r
/**\r
Initialize the XHCI host controller for schedule.\r
\r
**/\r
VOID\r
XhcInitSched (\r
- IN USB_XHCI_INSTANCE *Xhc\r
+ IN USB_XHCI_INSTANCE *Xhc\r
);\r
\r
/**\r
**/\r
VOID\r
XhcFreeSched (\r
- IN USB_XHCI_INSTANCE *Xhc\r
+ IN USB_XHCI_INSTANCE *Xhc\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
RingIntTransferDoorBell (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN URB *Urb\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN URB *Urb\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
XhcExecTransfer (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN BOOLEAN CmdTransfer,\r
- IN URB *Urb,\r
- IN UINTN Timeout\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN BOOLEAN CmdTransfer,\r
+ IN URB *Urb,\r
+ IN UINTN Timeout\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
XhciDelAsyncIntTransfer (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT8 BusAddr,\r
- IN UINT8 EpNum\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 BusAddr,\r
+ IN UINT8 EpNum\r
);\r
\r
/**\r
**/\r
VOID\r
XhciDelAllAsyncIntTransfers (\r
- IN USB_XHCI_INSTANCE *Xhc\r
+ IN USB_XHCI_INSTANCE *Xhc\r
+ );\r
+\r
+/**\r
+ Insert a single asynchronous interrupt transfer for\r
+ the device and endpoint.\r
+\r
+ @param Xhc The XHCI Instance\r
+ @param BusAddr The logical device address assigned by UsbBus driver\r
+ @param EpAddr Endpoint addrress\r
+ @param DevSpeed The device speed\r
+ @param MaxPacket The max packet length of the endpoint\r
+ @param DataLen The length of data buffer\r
+ @param Callback The function to call when data is transferred\r
+ @param Context The context to the callback\r
+\r
+ @return Created URB or NULL\r
+\r
+**/\r
+URB *\r
+XhciInsertAsyncIntTransfer (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 BusAddr,\r
+ IN UINT8 EpAddr,\r
+ IN UINT8 DevSpeed,\r
+ IN UINTN MaxPacket,\r
+ IN UINTN DataLen,\r
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r
+ IN VOID *Context\r
);\r
\r
/**\r
**/\r
VOID\r
XhcSetBiosOwnership (\r
- IN USB_XHCI_INSTANCE *Xhc\r
+ IN USB_XHCI_INSTANCE *Xhc\r
);\r
\r
/**\r
**/\r
VOID\r
XhcClearBiosOwnership (\r
- IN USB_XHCI_INSTANCE *Xhc\r
+ IN USB_XHCI_INSTANCE *Xhc\r
);\r
\r
/**\r
**/\r
UINT8\r
XhcEndpointToDci (\r
- IN UINT8 EpAddr,\r
- IN UINT8 Direction\r
+ IN UINT8 EpAddr,\r
+ IN UINT8 Direction\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
XhcRingDoorBell (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT8 SlotId,\r
- IN UINT8 Dci\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 Dci\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
XhcMonitorAsyncRequests (\r
- IN EFI_EVENT Event,\r
- IN VOID *Context\r
+ IN EFI_EVENT Event,\r
+ IN VOID *Context\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
XhcPollPortStatusChange (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN USB_DEV_ROUTE ParentRouteChart,\r
- IN UINT8 Port,\r
- IN EFI_USB_PORT_STATUS *PortState\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN USB_DEV_ROUTE ParentRouteChart,\r
+ IN UINT8 Port,\r
+ IN EFI_USB_PORT_STATUS *PortState\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
XhcConfigHubContext (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT8 SlotId,\r
- IN UINT8 PortNum,\r
- IN UINT8 TTT,\r
- IN UINT8 MTT\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 PortNum,\r
+ IN UINT8 TTT,\r
+ IN UINT8 MTT\r
);\r
\r
-\r
/**\r
Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.\r
\r
**/\r
EFI_STATUS\r
XhcConfigHubContext64 (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT8 SlotId,\r
- IN UINT8 PortNum,\r
- IN UINT8 TTT,\r
- IN UINT8 MTT\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 PortNum,\r
+ IN UINT8 TTT,\r
+ IN UINT8 MTT\r
);\r
\r
-\r
/**\r
Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r
\r
EFI_STATUS\r
EFIAPI\r
XhcSetConfigCmd (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT8 SlotId,\r
- IN UINT8 DeviceSpeed,\r
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 DeviceSpeed,\r
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r
);\r
\r
-\r
/**\r
Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r
\r
EFI_STATUS\r
EFIAPI\r
XhcSetConfigCmd64 (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT8 SlotId,\r
- IN UINT8 DeviceSpeed,\r
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 DeviceSpeed,\r
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
XhcSetInterface (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT8 SlotId,\r
- IN UINT8 DeviceSpeed,\r
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc,\r
- IN EFI_USB_DEVICE_REQUEST *Request\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 DeviceSpeed,\r
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc,\r
+ IN EFI_USB_DEVICE_REQUEST *Request\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
XhcSetInterface64 (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT8 SlotId,\r
- IN UINT8 DeviceSpeed,\r
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc,\r
- IN EFI_USB_DEVICE_REQUEST *Request\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 DeviceSpeed,\r
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc,\r
+ IN EFI_USB_DEVICE_REQUEST *Request\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
XhcInitializeDeviceSlot (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN USB_DEV_ROUTE ParentRouteChart,\r
- IN UINT16 ParentPort,\r
- IN USB_DEV_ROUTE RouteChart,\r
- IN UINT8 DeviceSpeed\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN USB_DEV_ROUTE ParentRouteChart,\r
+ IN UINT16 ParentPort,\r
+ IN USB_DEV_ROUTE RouteChart,\r
+ IN UINT8 DeviceSpeed\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
XhcInitializeDeviceSlot64 (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN USB_DEV_ROUTE ParentRouteChart,\r
- IN UINT16 ParentPort,\r
- IN USB_DEV_ROUTE RouteChart,\r
- IN UINT8 DeviceSpeed\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN USB_DEV_ROUTE ParentRouteChart,\r
+ IN UINT16 ParentPort,\r
+ IN USB_DEV_ROUTE RouteChart,\r
+ IN UINT8 DeviceSpeed\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
XhcEvaluateContext (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT8 SlotId,\r
- IN UINT32 MaxPacketSize\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT32 MaxPacketSize\r
);\r
\r
-\r
/**\r
Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.\r
\r
EFI_STATUS\r
EFIAPI\r
XhcEvaluateContext64 (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT8 SlotId,\r
- IN UINT32 MaxPacketSize\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT32 MaxPacketSize\r
);\r
\r
-\r
/**\r
Disable the specified device slot.\r
\r
EFI_STATUS\r
EFIAPI\r
XhcDisableSlotCmd (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT8 SlotId\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId\r
);\r
\r
-\r
/**\r
Disable the specified device slot.\r
\r
EFI_STATUS\r
EFIAPI\r
XhcDisableSlotCmd64 (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT8 SlotId\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId\r
);\r
\r
-\r
/**\r
Synchronize the specified transfer ring to update the enqueue and dequeue pointer.\r
\r
EFI_STATUS\r
EFIAPI\r
XhcSyncTrsRing (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- TRANSFER_RING *TrsRing\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ TRANSFER_RING *TrsRing\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
XhcSyncEventRing (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- EVENT_RING *EvtRing\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ EVENT_RING *EvtRing\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
XhcCheckNewEvent (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN EVENT_RING *EvtRing,\r
- OUT TRB_TEMPLATE **NewEvtTrb\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN EVENT_RING *EvtRing,\r
+ OUT TRB_TEMPLATE **NewEvtTrb\r
);\r
\r
/**\r
**/\r
VOID\r
CreateTransferRing (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINTN TrbNum,\r
- OUT TRANSFER_RING *TransferRing\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINTN TrbNum,\r
+ OUT TRANSFER_RING *TransferRing\r
);\r
\r
/**\r
**/\r
VOID\r
CreateEventRing (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- OUT EVENT_RING *EventRing\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ OUT EVENT_RING *EventRing\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
XhcRecoverHaltedEndpoint (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN URB *Urb\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN URB *Urb\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
XhcDequeueTrbFromEndpoint (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN URB *Urb\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN URB *Urb\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
XhcStopEndpoint (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT8 SlotId,\r
- IN UINT8 Dci,\r
- IN URB *PendingUrb OPTIONAL\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 Dci,\r
+ IN URB *PendingUrb OPTIONAL\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
XhcResetEndpoint (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT8 SlotId,\r
- IN UINT8 Dci\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 Dci\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
XhcSetTrDequeuePointer (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT8 SlotId,\r
- IN UINT8 Dci,\r
- IN URB *Urb\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 Dci,\r
+ IN URB *Urb\r
);\r
\r
/**\r
@return Created URB or NULL\r
\r
**/\r
-URB*\r
+URB *\r
XhcCreateUrb (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT8 DevAddr,\r
- IN UINT8 EpAddr,\r
- IN UINT8 DevSpeed,\r
- IN UINTN MaxPacket,\r
- IN UINTN Type,\r
- IN EFI_USB_DEVICE_REQUEST *Request,\r
- IN VOID *Data,\r
- IN UINTN DataLen,\r
- IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r
- IN VOID *Context\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 DevAddr,\r
+ IN UINT8 EpAddr,\r
+ IN UINT8 DevSpeed,\r
+ IN UINTN MaxPacket,\r
+ IN UINTN Type,\r
+ IN EFI_USB_DEVICE_REQUEST *Request,\r
+ IN VOID *Data,\r
+ IN UINTN DataLen,\r
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r
+ IN VOID *Context\r
);\r
\r
/**\r
**/\r
VOID\r
XhcFreeUrb (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN URB *Urb\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN URB *Urb\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
XhcCreateTransferTrb (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN URB *Urb\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN URB *Urb\r
);\r
\r
#endif\r
projects / mirror_edk2.git / blobdiff