/** @file\r
Private Header file for Usb Host Controller PEIM\r
\r
-Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
\r
//\r
// XHC reset timeout experience values.\r
-// The unit is microsecond, setting it as 1s.\r
+// The unit is millisecond, setting it as 1s.\r
//\r
-#define XHC_RESET_TIMEOUT (1 * XHC_1_SECOND)\r
+#define XHC_RESET_TIMEOUT (1000)\r
+\r
//\r
-// XHC delay experience value for polling operation.\r
-// The unit is microsecond, set it as 1ms.\r
+// TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5.\r
+// The unit is microsecond, setting it as 10ms.\r
//\r
-#define XHC_POLL_DELAY (1 * XHC_1_MILLISECOND)\r
+#define XHC_RESET_RECOVERY_DELAY (10 * 1000)\r
\r
//\r
// Wait for root port state stable.\r
//\r
#define XHC_ROOT_PORT_STATE_STABLE (200 * XHC_1_MILLISECOND)\r
\r
-#define XHC_GENERIC_TIMEOUT (10 * XHC_1_MILLISECOND)\r
+//\r
+// XHC generic timeout experience values.\r
+// The unit is millisecond, setting it as 10s.\r
+//\r
+#define XHC_GENERIC_TIMEOUT (10 * 1000)\r
\r
#define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))\r
#define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))\r