@return Created URB or NULL.\r
\r
**/\r
-URB*\r
+URB *\r
XhcPeiCreateCmdTrb (\r
- IN PEI_XHC_DEV *Xhc,\r
- IN TRB_TEMPLATE *CmdTrb\r
+ IN PEI_XHC_DEV *Xhc,\r
+ IN TRB_TEMPLATE *CmdTrb\r
)\r
{\r
- URB *Urb;\r
+ URB *Urb;\r
\r
Urb = AllocateZeroPool (sizeof (URB));\r
if (Urb == NULL) {\r
return NULL;\r
}\r
\r
- Urb->Signature = XHC_URB_SIG;\r
+ Urb->Signature = XHC_URB_SIG;\r
\r
- Urb->Ring = &Xhc->CmdRing;\r
+ Urb->Ring = &Xhc->CmdRing;\r
XhcPeiSyncTrsRing (Xhc, Urb->Ring);\r
- Urb->TrbNum = 1;\r
- Urb->TrbStart = Urb->Ring->RingEnqueue;\r
+ Urb->TrbNum = 1;\r
+ Urb->TrbStart = Urb->Ring->RingEnqueue;\r
CopyMem (Urb->TrbStart, CmdTrb, sizeof (TRB_TEMPLATE));\r
Urb->TrbStart->CycleBit = Urb->Ring->RingPCS & BIT0;\r
Urb->TrbEnd = Urb->TrbStart;\r
**/\r
EFI_STATUS\r
XhcPeiCmdTransfer (\r
- IN PEI_XHC_DEV *Xhc,\r
- IN TRB_TEMPLATE *CmdTrb,\r
- IN UINTN Timeout,\r
- OUT TRB_TEMPLATE **EvtTrb\r
+ IN PEI_XHC_DEV *Xhc,\r
+ IN TRB_TEMPLATE *CmdTrb,\r
+ IN UINTN Timeout,\r
+ OUT TRB_TEMPLATE **EvtTrb\r
)\r
{\r
- EFI_STATUS Status;\r
- URB *Urb;\r
+ EFI_STATUS Status;\r
+ URB *Urb;\r
\r
//\r
// Validate the parameters\r
@return Created URB or NULL\r
\r
**/\r
-URB*\r
+URB *\r
XhcPeiCreateUrb (\r
- IN PEI_XHC_DEV *Xhc,\r
- IN UINT8 BusAddr,\r
- IN UINT8 EpAddr,\r
- IN UINT8 DevSpeed,\r
- IN UINTN MaxPacket,\r
- IN UINTN Type,\r
- IN EFI_USB_DEVICE_REQUEST *Request,\r
- IN VOID *Data,\r
- IN UINTN DataLen,\r
- IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r
- IN VOID *Context\r
+ IN PEI_XHC_DEV *Xhc,\r
+ IN UINT8 BusAddr,\r
+ IN UINT8 EpAddr,\r
+ IN UINT8 DevSpeed,\r
+ IN UINTN MaxPacket,\r
+ IN UINTN Type,\r
+ IN EFI_USB_DEVICE_REQUEST *Request,\r
+ IN VOID *Data,\r
+ IN UINTN DataLen,\r
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r
+ IN VOID *Context\r
)\r
{\r
- USB_ENDPOINT *Ep;\r
- EFI_STATUS Status;\r
- URB *Urb;\r
+ USB_ENDPOINT *Ep;\r
+ EFI_STATUS Status;\r
+ URB *Urb;\r
\r
Urb = AllocateZeroPool (sizeof (URB));\r
if (Urb == NULL) {\r
\r
Ep = &Urb->Ep;\r
Ep->BusAddr = BusAddr;\r
- Ep->EpAddr = (UINT8) (EpAddr & 0x0F);\r
+ Ep->EpAddr = (UINT8)(EpAddr & 0x0F);\r
Ep->Direction = ((EpAddr & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut;\r
Ep->DevSpeed = DevSpeed;\r
Ep->MaxPacket = MaxPacket;\r
**/\r
VOID\r
XhcPeiFreeUrb (\r
- IN PEI_XHC_DEV *Xhc,\r
- IN URB *Urb\r
+ IN PEI_XHC_DEV *Xhc,\r
+ IN URB *Urb\r
)\r
{\r
if ((Xhc == NULL) || (Urb == NULL)) {\r
**/\r
EFI_STATUS\r
XhcPeiCreateTransferTrb (\r
- IN PEI_XHC_DEV *Xhc,\r
- IN URB *Urb\r
+ IN PEI_XHC_DEV *Xhc,\r
+ IN URB *Urb\r
)\r
{\r
- VOID *OutputContext;\r
- TRANSFER_RING *EPRing;\r
- UINT8 EPType;\r
- UINT8 SlotId;\r
- UINT8 Dci;\r
- TRB *TrbStart;\r
- UINTN TotalLen;\r
- UINTN Len;\r
- UINTN TrbNum;\r
- EDKII_IOMMU_OPERATION MapOp;\r
- EFI_PHYSICAL_ADDRESS PhyAddr;\r
- VOID *Map;\r
- EFI_STATUS Status;\r
+ VOID *OutputContext;\r
+ TRANSFER_RING *EPRing;\r
+ UINT8 EPType;\r
+ UINT8 SlotId;\r
+ UINT8 Dci;\r
+ TRB *TrbStart;\r
+ UINTN TotalLen;\r
+ UINTN Len;\r
+ UINTN TrbNum;\r
+ EDKII_IOMMU_OPERATION MapOp;\r
+ EFI_PHYSICAL_ADDRESS PhyAddr;\r
+ VOID *Map;\r
+ EFI_STATUS Status;\r
\r
SlotId = XhcPeiBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);\r
if (SlotId == 0) {\r
Urb->Completed = 0;\r
Urb->Result = EFI_USB_NOERROR;\r
\r
- Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));\r
- EPRing = (TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1];\r
- Urb->Ring = EPRing;\r
+ Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));\r
+ EPRing = (TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1];\r
+ Urb->Ring = EPRing;\r
OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;\r
if (Xhc->HcCParams.Data.Csz == 0) {\r
- EPType = (UINT8) ((DEVICE_CONTEXT *)OutputContext)->EP[Dci-1].EPType;\r
+ EPType = (UINT8)((DEVICE_CONTEXT *)OutputContext)->EP[Dci-1].EPType;\r
} else {\r
- EPType = (UINT8) ((DEVICE_CONTEXT_64 *)OutputContext)->EP[Dci-1].EPType;\r
+ EPType = (UINT8)((DEVICE_CONTEXT_64 *)OutputContext)->EP[Dci-1].EPType;\r
}\r
\r
//\r
// No need to remap.\r
//\r
if ((Urb->Data != NULL) && (Urb->DataMap == NULL)) {\r
- if (((UINT8) (Urb->Ep.Direction)) == EfiUsbDataIn) {\r
+ if (((UINT8)(Urb->Ep.Direction)) == EfiUsbDataIn) {\r
MapOp = EdkiiIoMmuOperationBusMasterWrite;\r
} else {\r
MapOp = EdkiiIoMmuOperationBusMasterRead;\r
}\r
\r
- Len = Urb->DataLen;\r
+ Len = Urb->DataLen;\r
Status = IoMmuMap (MapOp, Urb->Data, &Len, &PhyAddr, &Map);\r
\r
if (EFI_ERROR (Status) || (Len != Urb->DataLen)) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
\r
- Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);\r
- Urb->DataMap = Map;\r
+ Urb->DataPhy = (VOID *)((UINTN)PhyAddr);\r
+ Urb->DataMap = Map;\r
}\r
\r
//\r
//\r
// For control transfer, create SETUP_STAGE_TRB first.\r
//\r
- TrbStart = (TRB *) (UINTN) EPRing->RingEnqueue;\r
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
TrbStart->TrbCtrSetup.bmRequestType = Urb->Request->RequestType;\r
TrbStart->TrbCtrSetup.bRequest = Urb->Request->Request;\r
TrbStart->TrbCtrSetup.wValue = Urb->Request->Value;\r
} else {\r
TrbStart->TrbCtrSetup.TRT = 0;\r
}\r
+\r
//\r
// Update the cycle bit\r
//\r
//\r
if (Urb->DataLen > 0) {\r
XhcPeiSyncTrsRing (Xhc, EPRing);\r
- TrbStart = (TRB *) (UINTN) EPRing->RingEnqueue;\r
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
TrbStart->TrbCtrData.TRBPtrLo = XHC_LOW_32BIT (Urb->DataPhy);\r
TrbStart->TrbCtrData.TRBPtrHi = XHC_HIGH_32BIT (Urb->DataPhy);\r
- TrbStart->TrbCtrData.Length = (UINT32) Urb->DataLen;\r
+ TrbStart->TrbCtrData.Length = (UINT32)Urb->DataLen;\r
TrbStart->TrbCtrData.TDSize = 0;\r
TrbStart->TrbCtrData.IntTarget = 0;\r
TrbStart->TrbCtrData.ISP = 1;\r
} else {\r
TrbStart->TrbCtrData.DIR = 0;\r
}\r
+\r
//\r
// Update the cycle bit\r
//\r
TrbStart->TrbCtrData.CycleBit = EPRing->RingPCS & BIT0;\r
Urb->TrbNum++;\r
}\r
+\r
//\r
// For control transfer, create STATUS_STAGE_TRB.\r
// Get the pointer to next TRB for status stage use\r
//\r
XhcPeiSyncTrsRing (Xhc, EPRing);\r
- TrbStart = (TRB *) (UINTN) EPRing->RingEnqueue;\r
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
TrbStart->TrbCtrStatus.IntTarget = 0;\r
TrbStart->TrbCtrStatus.IOC = 1;\r
TrbStart->TrbCtrStatus.CH = 0;\r
} else {\r
TrbStart->TrbCtrStatus.DIR = 0;\r
}\r
+\r
//\r
// Update the cycle bit\r
//\r
//\r
XhcPeiSyncTrsRing (Xhc, EPRing);\r
Urb->TrbNum++;\r
- Urb->TrbEnd = (TRB_TEMPLATE *) (UINTN) TrbStart;\r
+ Urb->TrbEnd = (TRB_TEMPLATE *)(UINTN)TrbStart;\r
\r
break;\r
\r
TotalLen = 0;\r
Len = 0;\r
TrbNum = 0;\r
- TrbStart = (TRB *) (UINTN) EPRing->RingEnqueue;\r
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
while (TotalLen < Urb->DataLen) {\r
if ((TotalLen + 0x10000) >= Urb->DataLen) {\r
Len = Urb->DataLen - TotalLen;\r
} else {\r
Len = 0x10000;\r
}\r
- TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
- TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);\r
- TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);\r
- TrbStart->TrbNormal.Length = (UINT32) Len;\r
+\r
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
+ TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT ((UINT8 *)Urb->DataPhy + TotalLen);\r
+ TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT ((UINT8 *)Urb->DataPhy + TotalLen);\r
+ TrbStart->TrbNormal.Length = (UINT32)Len;\r
TrbStart->TrbNormal.TDSize = 0;\r
TrbStart->TrbNormal.IntTarget = 0;\r
TrbStart->TrbNormal.ISP = 1;\r
TotalLen = 0;\r
Len = 0;\r
TrbNum = 0;\r
- TrbStart = (TRB *) (UINTN) EPRing->RingEnqueue;\r
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
while (TotalLen < Urb->DataLen) {\r
if ((TotalLen + 0x10000) >= Urb->DataLen) {\r
Len = Urb->DataLen - TotalLen;\r
} else {\r
Len = 0x10000;\r
}\r
- TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
- TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);\r
- TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);\r
- TrbStart->TrbNormal.Length = (UINT32) Len;\r
+\r
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
+ TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT ((UINT8 *)Urb->DataPhy + TotalLen);\r
+ TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT ((UINT8 *)Urb->DataPhy + TotalLen);\r
+ TrbStart->TrbNormal.Length = (UINT32)Len;\r
TrbStart->TrbNormal.TDSize = 0;\r
TrbStart->TrbNormal.IntTarget = 0;\r
TrbStart->TrbNormal.ISP = 1;\r
break;\r
\r
default:\r
- DEBUG ((DEBUG_INFO, "Not supported EPType 0x%x!\n",EPType));\r
+ DEBUG ((DEBUG_INFO, "Not supported EPType 0x%x!\n", EPType));\r
ASSERT (FALSE);\r
break;\r
}\r
**/\r
EFI_STATUS\r
XhcPeiRecoverHaltedEndpoint (\r
- IN PEI_XHC_DEV *Xhc,\r
- IN URB *Urb\r
+ IN PEI_XHC_DEV *Xhc,\r
+ IN URB *Urb\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT8 Dci;\r
- UINT8 SlotId;\r
+ EFI_STATUS Status;\r
+ UINT8 Dci;\r
+ UINT8 SlotId;\r
\r
Status = EFI_SUCCESS;\r
SlotId = XhcPeiBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);\r
if (SlotId == 0) {\r
return EFI_DEVICE_ERROR;\r
}\r
- Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8) (Urb->Ep.Direction));\r
+\r
+ Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));\r
\r
DEBUG ((DEBUG_INFO, "XhcPeiRecoverHaltedEndpoint: Recovery Halted Slot = %x, Dci = %x\n", SlotId, Dci));\r
\r
// 1) Send Reset endpoint command to transit from halt to stop state\r
//\r
Status = XhcPeiResetEndpoint (Xhc, SlotId, Dci);\r
- if (EFI_ERROR(Status)) {\r
+ if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "XhcPeiRecoverHaltedEndpoint: Reset Endpoint Failed, Status = %r\n", Status));\r
goto Done;\r
}\r
// 2) Set dequeue pointer\r
//\r
Status = XhcPeiSetTrDequeuePointer (Xhc, SlotId, Dci, Urb);\r
- if (EFI_ERROR(Status)) {\r
+ if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "XhcPeiRecoverHaltedEndpoint: Set Dequeue Pointer Failed, Status = %r\n", Status));\r
goto Done;\r
}\r
**/\r
EFI_STATUS\r
XhcPeiDequeueTrbFromEndpoint (\r
- IN PEI_XHC_DEV *Xhc,\r
- IN URB *Urb\r
+ IN PEI_XHC_DEV *Xhc,\r
+ IN URB *Urb\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT8 Dci;\r
- UINT8 SlotId;\r
+ EFI_STATUS Status;\r
+ UINT8 Dci;\r
+ UINT8 SlotId;\r
\r
Status = EFI_SUCCESS;\r
SlotId = XhcPeiBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);\r
if (SlotId == 0) {\r
return EFI_DEVICE_ERROR;\r
}\r
- Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8) (Urb->Ep.Direction));\r
+\r
+ Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));\r
\r
DEBUG ((DEBUG_INFO, "XhcPeiDequeueTrbFromEndpoint: Stop Slot = %x, Dci = %x\n", SlotId, Dci));\r
\r
// 1) Send Stop endpoint command to stop endpoint.\r
//\r
Status = XhcPeiStopEndpoint (Xhc, SlotId, Dci);\r
- if (EFI_ERROR(Status)) {\r
+ if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "XhcPeiDequeueTrbFromEndpoint: Stop Endpoint Failed, Status = %r\n", Status));\r
goto Done;\r
}\r
// 2) Set dequeue pointer\r
//\r
Status = XhcPeiSetTrDequeuePointer (Xhc, SlotId, Dci, Urb);\r
- if (EFI_ERROR(Status)) {\r
+ if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "XhcPeiDequeueTrbFromEndpoint: Set Dequeue Pointer Failed, Status = %r\n", Status));\r
goto Done;\r
}\r
**/\r
BOOLEAN\r
XhcPeiIsTransferRingTrb (\r
- IN TRB_TEMPLATE *Trb,\r
- IN URB *Urb\r
+ IN TRB_TEMPLATE *Trb,\r
+ IN URB *Urb\r
)\r
{\r
TRB_TEMPLATE *CheckedTrb;\r
if (Trb == CheckedTrb) {\r
return TRUE;\r
}\r
+\r
CheckedTrb++;\r
}\r
\r
**/\r
BOOLEAN\r
XhcPeiCheckUrbResult (\r
- IN PEI_XHC_DEV *Xhc,\r
- IN URB *Urb\r
+ IN PEI_XHC_DEV *Xhc,\r
+ IN URB *Urb\r
)\r
{\r
- EVT_TRB_TRANSFER *EvtTrb;\r
- TRB_TEMPLATE *TRBPtr;\r
- UINTN Index;\r
- UINT8 TRBType;\r
- EFI_STATUS Status;\r
- URB *CheckedUrb;\r
- UINT64 XhcDequeue;\r
- UINT32 High;\r
- UINT32 Low;\r
- EFI_PHYSICAL_ADDRESS PhyAddr;\r
+ EVT_TRB_TRANSFER *EvtTrb;\r
+ TRB_TEMPLATE *TRBPtr;\r
+ UINTN Index;\r
+ UINT8 TRBType;\r
+ EFI_STATUS Status;\r
+ URB *CheckedUrb;\r
+ UINT64 XhcDequeue;\r
+ UINT32 High;\r
+ UINT32 Low;\r
+ EFI_PHYSICAL_ADDRESS PhyAddr;\r
\r
ASSERT ((Xhc != NULL) && (Urb != NULL));\r
\r
//\r
XhcPeiSyncEventRing (Xhc, &Xhc->EventRing);\r
for (Index = 0; Index < Xhc->EventRing.TrbNumber; Index++) {\r
- Status = XhcPeiCheckNewEvent (Xhc, &Xhc->EventRing, ((TRB_TEMPLATE **) &EvtTrb));\r
+ Status = XhcPeiCheckNewEvent (Xhc, &Xhc->EventRing, ((TRB_TEMPLATE **)&EvtTrb));\r
if (Status == EFI_NOT_READY) {\r
//\r
// All new events are handled, return directly.\r
//\r
// Need convert pci device address to host address\r
//\r
- PhyAddr = (EFI_PHYSICAL_ADDRESS) (EvtTrb->TRBPtrLo | LShiftU64 ((UINT64) EvtTrb->TRBPtrHi, 32));\r
- TRBPtr = (TRB_TEMPLATE *) (UINTN) UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *) (UINTN) PhyAddr, sizeof (TRB_TEMPLATE));\r
+ PhyAddr = (EFI_PHYSICAL_ADDRESS)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64)EvtTrb->TRBPtrHi, 32));\r
+ TRBPtr = (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE));\r
\r
//\r
// Update the status of Urb according to the finished event regardless of whether\r
DEBUG ((DEBUG_VERBOSE, "XhcPeiCheckUrbResult: short packet happens!\n"));\r
}\r
\r
- TRBType = (UINT8) (TRBPtr->Type);\r
+ TRBType = (UINT8)(TRBPtr->Type);\r
if ((TRBType == TRB_TYPE_DATA_STAGE) ||\r
(TRBType == TRB_TYPE_NORMAL) ||\r
- (TRBType == TRB_TYPE_ISOCH)) {\r
- CheckedUrb->Completed += (((TRANSFER_TRB_NORMAL*)TRBPtr)->Length - EvtTrb->Length);\r
+ (TRBType == TRB_TYPE_ISOCH))\r
+ {\r
+ CheckedUrb->Completed += (((TRANSFER_TRB_NORMAL *)TRBPtr)->Length - EvtTrb->Length);\r
}\r
\r
break;\r
\r
if (CheckedUrb->StartDone && CheckedUrb->EndDone) {\r
CheckedUrb->Finished = TRUE;\r
- CheckedUrb->EvtTrb = (TRB_TEMPLATE *) EvtTrb;\r
+ CheckedUrb->EvtTrb = (TRB_TEMPLATE *)EvtTrb;\r
}\r
}\r
\r
// Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r
// So divide it to two 32-bytes width register access.\r
//\r
- Low = XhcPeiReadRuntimeReg (Xhc, XHC_ERDP_OFFSET);\r
- High = XhcPeiReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4);\r
- XhcDequeue = (UINT64) (LShiftU64((UINT64) High, 32) | Low);\r
+ Low = XhcPeiReadRuntimeReg (Xhc, XHC_ERDP_OFFSET);\r
+ High = XhcPeiReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4);\r
+ XhcDequeue = (UINT64)(LShiftU64 ((UINT64)High, 32) | Low);\r
\r
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->EventRing.EventRingDequeue, sizeof (TRB_TEMPLATE));\r
\r
**/\r
EFI_STATUS\r
XhcPeiExecTransfer (\r
- IN PEI_XHC_DEV *Xhc,\r
- IN BOOLEAN CmdTransfer,\r
- IN URB *Urb,\r
- IN UINTN Timeout\r
+ IN PEI_XHC_DEV *Xhc,\r
+ IN BOOLEAN CmdTransfer,\r
+ IN URB *Urb,\r
+ IN UINTN Timeout\r
)\r
{\r
- EFI_STATUS Status;\r
- UINTN Index;\r
- UINT64 Loop;\r
- UINT8 SlotId;\r
- UINT8 Dci;\r
- BOOLEAN Finished;\r
+ EFI_STATUS Status;\r
+ UINTN Index;\r
+ UINT64 Loop;\r
+ UINT8 SlotId;\r
+ UINT8 Dci;\r
+ BOOLEAN Finished;\r
\r
if (CmdTransfer) {\r
SlotId = 0;\r
if (SlotId == 0) {\r
return EFI_DEVICE_ERROR;\r
}\r
- Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));\r
+\r
+ Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));\r
}\r
\r
Status = EFI_SUCCESS;\r
if (Finished) {\r
break;\r
}\r
+\r
MicroSecondDelay (XHC_1_MICROSECOND);\r
}\r
\r
Urb->Result = EFI_USB_ERR_TIMEOUT;\r
Status = EFI_TIMEOUT;\r
} else if (Urb->Result != EFI_USB_NOERROR) {\r
- Status = EFI_DEVICE_ERROR;\r
+ Status = EFI_DEVICE_ERROR;\r
}\r
\r
return Status;\r
**/\r
EFI_STATUS\r
XhcPeiPollPortStatusChange (\r
- IN PEI_XHC_DEV *Xhc,\r
- IN USB_DEV_ROUTE ParentRouteChart,\r
- IN UINT8 Port,\r
- IN EFI_USB_PORT_STATUS *PortState\r
+ IN PEI_XHC_DEV *Xhc,\r
+ IN USB_DEV_ROUTE ParentRouteChart,\r
+ IN UINT8 Port,\r
+ IN EFI_USB_PORT_STATUS *PortState\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT8 Speed;\r
- UINT8 SlotId;\r
- USB_DEV_ROUTE RouteChart;\r
+ EFI_STATUS Status;\r
+ UINT8 Speed;\r
+ UINT8 SlotId;\r
+ USB_DEV_ROUTE RouteChart;\r
\r
DEBUG ((DEBUG_INFO, "XhcPeiPollPortStatusChange: PortChangeStatus: %x PortStatus: %x\n", PortState->PortChangeStatus, PortState->PortStatus));\r
\r
RouteChart.Route.RootPortNum = Port + 1;\r
RouteChart.Route.TierNum = 1;\r
} else {\r
- if(Port < 14) {\r
+ if (Port < 14) {\r
RouteChart.Route.RouteString = ParentRouteChart.Route.RouteString | (Port << (4 * (ParentRouteChart.Route.TierNum - 1)));\r
} else {\r
RouteChart.Route.RouteString = ParentRouteChart.Route.RouteString | (15 << (4 * (ParentRouteChart.Route.TierNum - 1)));\r
}\r
- RouteChart.Route.RootPortNum = ParentRouteChart.Route.RootPortNum;\r
- RouteChart.Route.TierNum = ParentRouteChart.Route.TierNum + 1;\r
+\r
+ RouteChart.Route.RootPortNum = ParentRouteChart.Route.RootPortNum;\r
+ RouteChart.Route.TierNum = ParentRouteChart.Route.TierNum + 1;\r
}\r
\r
SlotId = XhcPeiRouteStringToSlotId (Xhc, RouteChart);\r
}\r
\r
if (((PortState->PortStatus & USB_PORT_STAT_ENABLE) != 0) &&\r
- ((PortState->PortStatus & USB_PORT_STAT_CONNECTION) != 0)) {\r
+ ((PortState->PortStatus & USB_PORT_STAT_CONNECTION) != 0))\r
+ {\r
//\r
// Has a device attached, Identify device speed after port is enabled.\r
//\r
} else if ((PortState->PortStatus & USB_PORT_STAT_SUPER_SPEED) != 0) {\r
Speed = EFI_USB_SPEED_SUPER;\r
}\r
+\r
//\r
// Execute Enable_Slot cmd for attached device, initialize device context and assign device address.\r
//\r
**/\r
UINT8\r
XhcPeiEndpointToDci (\r
- IN UINT8 EpAddr,\r
- IN EFI_USB_DATA_DIRECTION Direction\r
+ IN UINT8 EpAddr,\r
+ IN EFI_USB_DATA_DIRECTION Direction\r
)\r
{\r
- UINT8 Index;\r
+ UINT8 Index;\r
\r
ASSERT (EpAddr <= 15);\r
\r
if (EpAddr == 0) {\r
return 1;\r
} else {\r
- Index = (UINT8) (2 * EpAddr);\r
+ Index = (UINT8)(2 * EpAddr);\r
if (Direction == EfiUsbDataIn) {\r
Index += 1;\r
}\r
+\r
return Index;\r
}\r
}\r
**/\r
UINT8\r
XhcPeiBusDevAddrToSlotId (\r
- IN PEI_XHC_DEV *Xhc,\r
- IN UINT8 BusDevAddr\r
+ IN PEI_XHC_DEV *Xhc,\r
+ IN UINT8 BusDevAddr\r
)\r
{\r
- UINT8 Index;\r
+ UINT8 Index;\r
\r
for (Index = 0; Index < 255; Index++) {\r
if (Xhc->UsbDevContext[Index + 1].Enabled &&\r
(Xhc->UsbDevContext[Index + 1].SlotId != 0) &&\r
- (Xhc->UsbDevContext[Index + 1].BusDevAddr == BusDevAddr)) {\r
+ (Xhc->UsbDevContext[Index + 1].BusDevAddr == BusDevAddr))\r
+ {\r
break;\r
}\r
}\r
**/\r
UINT8\r
XhcPeiRouteStringToSlotId (\r
- IN PEI_XHC_DEV *Xhc,\r
- IN USB_DEV_ROUTE RouteString\r
+ IN PEI_XHC_DEV *Xhc,\r
+ IN USB_DEV_ROUTE RouteString\r
)\r
{\r
- UINT8 Index;\r
+ UINT8 Index;\r
\r
for (Index = 0; Index < 255; Index++) {\r
if (Xhc->UsbDevContext[Index + 1].Enabled &&\r
(Xhc->UsbDevContext[Index + 1].SlotId != 0) &&\r
- (Xhc->UsbDevContext[Index + 1].RouteString.Dword == RouteString.Dword)) {\r
+ (Xhc->UsbDevContext[Index + 1].RouteString.Dword == RouteString.Dword))\r
+ {\r
break;\r
}\r
}\r
**/\r
VOID\r
XhcPeiRingDoorBell (\r
- IN PEI_XHC_DEV *Xhc,\r
- IN UINT8 SlotId,\r
- IN UINT8 Dci\r
+ IN PEI_XHC_DEV *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 Dci\r
)\r
{\r
if (SlotId == 0) {\r
**/\r
EFI_STATUS\r
XhcPeiInitializeDeviceSlot (\r
- IN PEI_XHC_DEV *Xhc,\r
- IN USB_DEV_ROUTE ParentRouteChart,\r
- IN UINT16 ParentPort,\r
- IN USB_DEV_ROUTE RouteChart,\r
- IN UINT8 DeviceSpeed\r
+ IN PEI_XHC_DEV *Xhc,\r
+ IN USB_DEV_ROUTE ParentRouteChart,\r
+ IN UINT16 ParentPort,\r
+ IN USB_DEV_ROUTE RouteChart,\r
+ IN UINT8 DeviceSpeed\r
)\r
{\r
- EFI_STATUS Status;\r
- EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
- INPUT_CONTEXT *InputContext;\r
- DEVICE_CONTEXT *OutputContext;\r
- TRANSFER_RING *EndpointTransferRing;\r
- CMD_TRB_ADDRESS_DEVICE CmdTrbAddr;\r
- UINT8 DeviceAddress;\r
- CMD_TRB_ENABLE_SLOT CmdTrb;\r
- UINT8 SlotId;\r
- UINT8 ParentSlotId;\r
- DEVICE_CONTEXT *ParentDeviceContext;\r
- EFI_PHYSICAL_ADDRESS PhyAddr;\r
+ EFI_STATUS Status;\r
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
+ INPUT_CONTEXT *InputContext;\r
+ DEVICE_CONTEXT *OutputContext;\r
+ TRANSFER_RING *EndpointTransferRing;\r
+ CMD_TRB_ADDRESS_DEVICE CmdTrbAddr;\r
+ UINT8 DeviceAddress;\r
+ CMD_TRB_ENABLE_SLOT CmdTrb;\r
+ UINT8 SlotId;\r
+ UINT8 ParentSlotId;\r
+ DEVICE_CONTEXT *ParentDeviceContext;\r
+ EFI_PHYSICAL_ADDRESS PhyAddr;\r
\r
ZeroMem (&CmdTrb, sizeof (CMD_TRB_ENABLE_SLOT));\r
CmdTrb.CycleBit = 1;\r
\r
Status = XhcPeiCmdTransfer (\r
Xhc,\r
- (TRB_TEMPLATE *) (UINTN) &CmdTrb,\r
+ (TRB_TEMPLATE *)(UINTN)&CmdTrb,\r
XHC_GENERIC_TIMEOUT,\r
- (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb\r
);\r
if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "XhcPeiInitializeDeviceSlot: Enable Slot Failed, Status = %r\n", Status));\r
return Status;\r
}\r
+\r
ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);\r
DEBUG ((DEBUG_INFO, "XhcPeiInitializeDeviceSlot: Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));\r
- SlotId = (UINT8) EvtTrb->SlotId;\r
+ SlotId = (UINT8)EvtTrb->SlotId;\r
ASSERT (SlotId != 0);\r
\r
ZeroMem (&Xhc->UsbDevContext[SlotId], sizeof (USB_DEV_CONTEXT));\r
//\r
InputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (INPUT_CONTEXT));\r
ASSERT (InputContext != NULL);\r
- ASSERT (((UINTN) InputContext & 0x3F) == 0);\r
+ ASSERT (((UINTN)InputContext & 0x3F) == 0);\r
ZeroMem (InputContext, sizeof (INPUT_CONTEXT));\r
\r
- Xhc->UsbDevContext[SlotId].InputContext = (VOID *) InputContext;\r
+ Xhc->UsbDevContext[SlotId].InputContext = (VOID *)InputContext;\r
\r
//\r
// 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1\r
//\r
// If the Full/Low device attached to a High Speed Hub, init the TTPortNum and TTHubSlotId field of slot context\r
//\r
- ParentDeviceContext = (DEVICE_CONTEXT *) Xhc->UsbDevContext[ParentSlotId].OutputContext;\r
+ ParentDeviceContext = (DEVICE_CONTEXT *)Xhc->UsbDevContext[ParentSlotId].OutputContext;\r
if ((ParentDeviceContext->Slot.TTPortNum == 0) &&\r
- (ParentDeviceContext->Slot.TTHubSlotId == 0)) {\r
+ (ParentDeviceContext->Slot.TTHubSlotId == 0))\r
+ {\r
if ((ParentDeviceContext->Slot.Speed == (EFI_USB_SPEED_HIGH + 1)) && (DeviceSpeed < EFI_USB_SPEED_HIGH)) {\r
//\r
// Full/Low device attached to High speed hub port that isolates the high speed signaling\r
//\r
// 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.\r
//\r
- EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));\r
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));\r
Xhc->UsbDevContext[SlotId].EndpointTransferRing[0] = EndpointTransferRing;\r
- XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *) Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);\r
+ XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);\r
//\r
// 5) Initialize the Input default control Endpoint 0 Context (6.2.3).\r
//\r
} else {\r
InputContext->EP[0].MaxPacketSize = 8;\r
}\r
+\r
//\r
// Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints\r
// 1KB, and Bulk and Isoch endpoints 3KB.\r
//\r
PhyAddr = UsbHcGetPciAddrForHostAddr (\r
Xhc->MemPool,\r
- ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,\r
+ ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,\r
sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER\r
);\r
InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0;\r
//\r
OutputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (DEVICE_CONTEXT));\r
ASSERT (OutputContext != NULL);\r
- ASSERT (((UINTN) OutputContext & 0x3F) == 0);\r
+ ASSERT (((UINTN)OutputContext & 0x3F) == 0);\r
ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT));\r
\r
Xhc->UsbDevContext[SlotId].OutputContext = OutputContext;\r
//\r
// Fill DCBAA with PCI device address\r
//\r
- Xhc->DCBAA[SlotId] = (UINT64) (UINTN) PhyAddr;\r
+ Xhc->DCBAA[SlotId] = (UINT64)(UINTN)PhyAddr;\r
\r
//\r
// 8) Issue an Address Device Command for the Device Slot, where the command points to the Input\r
//\r
MicroSecondDelay (XHC_RESET_RECOVERY_DELAY);\r
ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));\r
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));\r
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));\r
CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);\r
CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
CmdTrbAddr.CycleBit = 1;\r
CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV;\r
CmdTrbAddr.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r
- Status = XhcPeiCmdTransfer (\r
- Xhc,\r
- (TRB_TEMPLATE *) (UINTN) &CmdTrbAddr,\r
- XHC_GENERIC_TIMEOUT,\r
- (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
- );\r
+ Status = XhcPeiCmdTransfer (\r
+ Xhc,\r
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbAddr,\r
+ XHC_GENERIC_TIMEOUT,\r
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb\r
+ );\r
if (!EFI_ERROR (Status)) {\r
- DeviceAddress = (UINT8) OutputContext->Slot.DeviceAddress;\r
+ DeviceAddress = (UINT8)OutputContext->Slot.DeviceAddress;\r
DEBUG ((DEBUG_INFO, "XhcPeiInitializeDeviceSlot: Address %d assigned successfully\n", DeviceAddress));\r
Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;\r
}\r
**/\r
EFI_STATUS\r
XhcPeiInitializeDeviceSlot64 (\r
- IN PEI_XHC_DEV *Xhc,\r
- IN USB_DEV_ROUTE ParentRouteChart,\r
- IN UINT16 ParentPort,\r
- IN USB_DEV_ROUTE RouteChart,\r
- IN UINT8 DeviceSpeed\r
+ IN PEI_XHC_DEV *Xhc,\r
+ IN USB_DEV_ROUTE ParentRouteChart,\r
+ IN UINT16 ParentPort,\r
+ IN USB_DEV_ROUTE RouteChart,\r
+ IN UINT8 DeviceSpeed\r
)\r
{\r
- EFI_STATUS Status;\r
- EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
- INPUT_CONTEXT_64 *InputContext;\r
- DEVICE_CONTEXT_64 *OutputContext;\r
- TRANSFER_RING *EndpointTransferRing;\r
- CMD_TRB_ADDRESS_DEVICE CmdTrbAddr;\r
- UINT8 DeviceAddress;\r
- CMD_TRB_ENABLE_SLOT CmdTrb;\r
- UINT8 SlotId;\r
- UINT8 ParentSlotId;\r
- DEVICE_CONTEXT_64 *ParentDeviceContext;\r
- EFI_PHYSICAL_ADDRESS PhyAddr;\r
+ EFI_STATUS Status;\r
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
+ INPUT_CONTEXT_64 *InputContext;\r
+ DEVICE_CONTEXT_64 *OutputContext;\r
+ TRANSFER_RING *EndpointTransferRing;\r
+ CMD_TRB_ADDRESS_DEVICE CmdTrbAddr;\r
+ UINT8 DeviceAddress;\r
+ CMD_TRB_ENABLE_SLOT CmdTrb;\r
+ UINT8 SlotId;\r
+ UINT8 ParentSlotId;\r
+ DEVICE_CONTEXT_64 *ParentDeviceContext;\r
+ EFI_PHYSICAL_ADDRESS PhyAddr;\r
\r
ZeroMem (&CmdTrb, sizeof (CMD_TRB_ENABLE_SLOT));\r
CmdTrb.CycleBit = 1;\r
\r
Status = XhcPeiCmdTransfer (\r
Xhc,\r
- (TRB_TEMPLATE *) (UINTN) &CmdTrb,\r
+ (TRB_TEMPLATE *)(UINTN)&CmdTrb,\r
XHC_GENERIC_TIMEOUT,\r
- (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb\r
);\r
if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "XhcPeiInitializeDeviceSlot64: Enable Slot Failed, Status = %r\n", Status));\r
return Status;\r
}\r
+\r
ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);\r
DEBUG ((DEBUG_INFO, "XhcPeiInitializeDeviceSlot64: Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));\r
SlotId = (UINT8)EvtTrb->SlotId;\r
//\r
InputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (INPUT_CONTEXT_64));\r
ASSERT (InputContext != NULL);\r
- ASSERT (((UINTN) InputContext & 0x3F) == 0);\r
+ ASSERT (((UINTN)InputContext & 0x3F) == 0);\r
ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));\r
\r
- Xhc->UsbDevContext[SlotId].InputContext = (VOID *) InputContext;\r
+ Xhc->UsbDevContext[SlotId].InputContext = (VOID *)InputContext;\r
\r
//\r
// 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1\r
ParentSlotId = XhcPeiRouteStringToSlotId (Xhc, ParentRouteChart);\r
ASSERT (ParentSlotId != 0);\r
//\r
- //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context\r
+ // if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context\r
//\r
- ParentDeviceContext = (DEVICE_CONTEXT_64 *) Xhc->UsbDevContext[ParentSlotId].OutputContext;\r
+ ParentDeviceContext = (DEVICE_CONTEXT_64 *)Xhc->UsbDevContext[ParentSlotId].OutputContext;\r
if ((ParentDeviceContext->Slot.TTPortNum == 0) &&\r
- (ParentDeviceContext->Slot.TTHubSlotId == 0)) {\r
+ (ParentDeviceContext->Slot.TTHubSlotId == 0))\r
+ {\r
if ((ParentDeviceContext->Slot.Speed == (EFI_USB_SPEED_HIGH + 1)) && (DeviceSpeed < EFI_USB_SPEED_HIGH)) {\r
//\r
// Full/Low device attached to High speed hub port that isolates the high speed signaling\r
//\r
// 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.\r
//\r
- EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));\r
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));\r
Xhc->UsbDevContext[SlotId].EndpointTransferRing[0] = EndpointTransferRing;\r
- XhcPeiCreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *) Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);\r
+ XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);\r
//\r
// 5) Initialize the Input default control Endpoint 0 Context (6.2.3).\r
//\r
} else {\r
InputContext->EP[0].MaxPacketSize = 8;\r
}\r
+\r
//\r
// Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints\r
// 1KB, and Bulk and Isoch endpoints 3KB.\r
//\r
PhyAddr = UsbHcGetPciAddrForHostAddr (\r
Xhc->MemPool,\r
- ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,\r
+ ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,\r
sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER\r
);\r
InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0;\r
//\r
OutputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (DEVICE_CONTEXT_64));\r
ASSERT (OutputContext != NULL);\r
- ASSERT (((UINTN) OutputContext & 0x3F) == 0);\r
+ ASSERT (((UINTN)OutputContext & 0x3F) == 0);\r
ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT_64));\r
\r
Xhc->UsbDevContext[SlotId].OutputContext = OutputContext;\r
//\r
// Fill DCBAA with PCI device address\r
//\r
- Xhc->DCBAA[SlotId] = (UINT64) (UINTN) PhyAddr;\r
+ Xhc->DCBAA[SlotId] = (UINT64)(UINTN)PhyAddr;\r
\r
//\r
// 8) Issue an Address Device Command for the Device Slot, where the command points to the Input\r
//\r
MicroSecondDelay (XHC_RESET_RECOVERY_DELAY);\r
ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));\r
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));\r
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));\r
CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);\r
CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
CmdTrbAddr.CycleBit = 1;\r
CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV;\r
CmdTrbAddr.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r
- Status = XhcPeiCmdTransfer (\r
- Xhc,\r
- (TRB_TEMPLATE *) (UINTN) &CmdTrbAddr,\r
- XHC_GENERIC_TIMEOUT,\r
- (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
- );\r
+ Status = XhcPeiCmdTransfer (\r
+ Xhc,\r
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbAddr,\r
+ XHC_GENERIC_TIMEOUT,\r
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb\r
+ );\r
if (!EFI_ERROR (Status)) {\r
- DeviceAddress = (UINT8) OutputContext->Slot.DeviceAddress;\r
+ DeviceAddress = (UINT8)OutputContext->Slot.DeviceAddress;\r
DEBUG ((DEBUG_INFO, "XhcPeiInitializeDeviceSlot64: Address %d assigned successfully\n", DeviceAddress));\r
Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;\r
}\r
return Status;\r
}\r
\r
-\r
/**\r
Disable the specified device slot.\r
\r
**/\r
EFI_STATUS\r
XhcPeiDisableSlotCmd (\r
- IN PEI_XHC_DEV *Xhc,\r
- IN UINT8 SlotId\r
+ IN PEI_XHC_DEV *Xhc,\r
+ IN UINT8 SlotId\r
)\r
{\r
EFI_STATUS Status;\r
for (Index = 0; Index < 255; Index++) {\r
if (!Xhc->UsbDevContext[Index + 1].Enabled ||\r
(Xhc->UsbDevContext[Index + 1].SlotId == 0) ||\r
- (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword)) {\r
+ (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword))\r
+ {\r
continue;\r
}\r
\r
CmdTrbDisSlot.CycleBit = 1;\r
CmdTrbDisSlot.Type = TRB_TYPE_DIS_SLOT;\r
CmdTrbDisSlot.SlotId = SlotId;\r
- Status = XhcPeiCmdTransfer (\r
- Xhc,\r
- (TRB_TEMPLATE *) (UINTN) &CmdTrbDisSlot,\r
- XHC_GENERIC_TIMEOUT,\r
- (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
- );\r
+ Status = XhcPeiCmdTransfer (\r
+ Xhc,\r
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbDisSlot,\r
+ XHC_GENERIC_TIMEOUT,\r
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb\r
+ );\r
if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "XhcPeiDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));\r
return Status;\r
}\r
+\r
//\r
// Free the slot's device context entry\r
//\r
//\r
for (Index = 0; Index < 31; Index++) {\r
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] != NULL) {\r
- RingSeg = ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;\r
+ RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;\r
if (RingSeg != NULL) {\r
UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);\r
}\r
+\r
FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);\r
Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] = NULL;\r
}\r
if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {\r
UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT));\r
}\r
+\r
//\r
// Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established\r
// asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to\r
**/\r
EFI_STATUS\r
XhcPeiDisableSlotCmd64 (\r
- IN PEI_XHC_DEV *Xhc,\r
- IN UINT8 SlotId\r
+ IN PEI_XHC_DEV *Xhc,\r
+ IN UINT8 SlotId\r
)\r
{\r
EFI_STATUS Status;\r
for (Index = 0; Index < 255; Index++) {\r
if (!Xhc->UsbDevContext[Index + 1].Enabled ||\r
(Xhc->UsbDevContext[Index + 1].SlotId == 0) ||\r
- (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword)) {\r
+ (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword))\r
+ {\r
continue;\r
}\r
\r
CmdTrbDisSlot.CycleBit = 1;\r
CmdTrbDisSlot.Type = TRB_TYPE_DIS_SLOT;\r
CmdTrbDisSlot.SlotId = SlotId;\r
- Status = XhcPeiCmdTransfer (\r
- Xhc,\r
- (TRB_TEMPLATE *) (UINTN) &CmdTrbDisSlot,\r
- XHC_GENERIC_TIMEOUT,\r
- (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
- );\r
+ Status = XhcPeiCmdTransfer (\r
+ Xhc,\r
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbDisSlot,\r
+ XHC_GENERIC_TIMEOUT,\r
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb\r
+ );\r
if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "XhcPeiDisableSlotCmd64: Disable Slot Command Failed, Status = %r\n", Status));\r
return Status;\r
}\r
+\r
//\r
// Free the slot's device context entry\r
//\r
//\r
for (Index = 0; Index < 31; Index++) {\r
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] != NULL) {\r
- RingSeg = ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;\r
+ RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;\r
if (RingSeg != NULL) {\r
UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);\r
}\r
+\r
FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);\r
Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] = NULL;\r
}\r
}\r
\r
if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {\r
- UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT_64));\r
+ UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT_64));\r
}\r
+\r
//\r
// Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established\r
// asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to\r
**/\r
EFI_STATUS\r
XhcPeiSetConfigCmd (\r
- IN PEI_XHC_DEV *Xhc,\r
- IN UINT8 SlotId,\r
- IN UINT8 DeviceSpeed,\r
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r
+ IN PEI_XHC_DEV *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 DeviceSpeed,\r
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r
)\r
{\r
- EFI_STATUS Status;\r
- USB_INTERFACE_DESCRIPTOR *IfDesc;\r
- USB_ENDPOINT_DESCRIPTOR *EpDesc;\r
- UINT8 Index;\r
- UINTN NumEp;\r
- UINTN EpIndex;\r
- UINT8 EpAddr;\r
- EFI_USB_DATA_DIRECTION Direction;\r
- UINT8 Dci;\r
- UINT8 MaxDci;\r
- EFI_PHYSICAL_ADDRESS PhyAddr;\r
- UINT8 Interval;\r
-\r
- TRANSFER_RING *EndpointTransferRing;\r
- CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;\r
- INPUT_CONTEXT *InputContext;\r
- DEVICE_CONTEXT *OutputContext;\r
- EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
+ EFI_STATUS Status;\r
+ USB_INTERFACE_DESCRIPTOR *IfDesc;\r
+ USB_ENDPOINT_DESCRIPTOR *EpDesc;\r
+ UINT8 Index;\r
+ UINTN NumEp;\r
+ UINTN EpIndex;\r
+ UINT8 EpAddr;\r
+ EFI_USB_DATA_DIRECTION Direction;\r
+ UINT8 Dci;\r
+ UINT8 MaxDci;\r
+ EFI_PHYSICAL_ADDRESS PhyAddr;\r
+ UINT8 Interval;\r
+\r
+ TRANSFER_RING *EndpointTransferRing;\r
+ CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;\r
+ INPUT_CONTEXT *InputContext;\r
+ DEVICE_CONTEXT *OutputContext;\r
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
+\r
//\r
// 4.6.6 Configure Endpoint\r
//\r
\r
MaxDci = 0;\r
\r
- IfDesc = (USB_INTERFACE_DESCRIPTOR *) (ConfigDesc + 1);\r
+ IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);\r
for (Index = 0; Index < ConfigDesc->NumInterfaces; Index++) {\r
while ((IfDesc->DescriptorType != USB_DESC_TYPE_INTERFACE) || (IfDesc->AlternateSetting != 0)) {\r
- IfDesc = (USB_INTERFACE_DESCRIPTOR *) ((UINTN) IfDesc + IfDesc->Length);\r
+ IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r
}\r
\r
NumEp = IfDesc->NumEndpoints;\r
\r
- EpDesc = (USB_ENDPOINT_DESCRIPTOR *) (IfDesc + 1);\r
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDesc + 1);\r
for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {\r
while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {\r
- EpDesc = (USB_ENDPOINT_DESCRIPTOR *) ((UINTN) EpDesc + EpDesc->Length);\r
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
}\r
\r
- EpAddr = (UINT8) (EpDesc->EndpointAddress & 0x0F);\r
- Direction = (UINT8) ((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);\r
+ EpAddr = (UINT8)(EpDesc->EndpointAddress & 0x0F);\r
+ Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);\r
\r
Dci = XhcPeiEndpointToDci (EpAddr, Direction);\r
if (Dci > MaxDci) {\r
\r
InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {\r
- EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));\r
- Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;\r
- XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);\r
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));\r
+ Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *)EndpointTransferRing;\r
+ XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);\r
}\r
\r
break;\r
InputContext->EP[Dci-1].CErr = 0;\r
InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;\r
}\r
+\r
//\r
// Get the bInterval from descriptor and init the the interval field of endpoint context.\r
// Refer to XHCI 1.1 spec section 6.2.3.6.\r
InputContext->EP[Dci-1].CErr = 3;\r
InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;\r
}\r
+\r
InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r
InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;\r
//\r
// Calculate through the bInterval field of Endpoint descriptor.\r
//\r
ASSERT (Interval != 0);\r
- InputContext->EP[Dci-1].Interval = (UINT32) HighBitSet32 ((UINT32) Interval) + 3;\r
+ InputContext->EP[Dci-1].Interval = (UINT32)HighBitSet32 ((UINT32)Interval) + 3;\r
} else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {\r
Interval = EpDesc->Interval;\r
ASSERT (Interval >= 1 && Interval <= 16);\r
}\r
\r
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {\r
- EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));\r
- Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;\r
- XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);\r
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));\r
+ Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *)EndpointTransferRing;\r
+ XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);\r
}\r
+\r
break;\r
\r
case USB_ENDPOINT_CONTROL:\r
\r
PhyAddr = UsbHcGetPciAddrForHostAddr (\r
Xhc->MemPool,\r
- ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,\r
+ ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,\r
sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER\r
);\r
- PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);\r
- PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;\r
+ PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);\r
+ PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;\r
InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);\r
InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
\r
- EpDesc = (USB_ENDPOINT_DESCRIPTOR *) ((UINTN) EpDesc + EpDesc->Length);\r
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
}\r
- IfDesc = (USB_INTERFACE_DESCRIPTOR *) ((UINTN) IfDesc + IfDesc->Length);\r
+\r
+ IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r
}\r
\r
InputContext->InputControlContext.Dword2 |= BIT0;\r
// configure endpoint\r
//\r
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));\r
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));\r
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));\r
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);\r
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
CmdTrbCfgEP.CycleBit = 1;\r
DEBUG ((DEBUG_INFO, "XhcSetConfigCmd: Configure Endpoint\n"));\r
Status = XhcPeiCmdTransfer (\r
Xhc,\r
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,\r
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,\r
XHC_GENERIC_TIMEOUT,\r
- (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb\r
);\r
if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "XhcSetConfigCmd: Config Endpoint Failed, Status = %r\n", Status));\r
}\r
+\r
return Status;\r
}\r
\r
**/\r
EFI_STATUS\r
XhcPeiSetConfigCmd64 (\r
- IN PEI_XHC_DEV *Xhc,\r
- IN UINT8 SlotId,\r
- IN UINT8 DeviceSpeed,\r
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r
+ IN PEI_XHC_DEV *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 DeviceSpeed,\r
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r
)\r
{\r
- EFI_STATUS Status;\r
- USB_INTERFACE_DESCRIPTOR *IfDesc;\r
- USB_ENDPOINT_DESCRIPTOR *EpDesc;\r
- UINT8 Index;\r
- UINTN NumEp;\r
- UINTN EpIndex;\r
- UINT8 EpAddr;\r
- EFI_USB_DATA_DIRECTION Direction;\r
- UINT8 Dci;\r
- UINT8 MaxDci;\r
- EFI_PHYSICAL_ADDRESS PhyAddr;\r
- UINT8 Interval;\r
-\r
- TRANSFER_RING *EndpointTransferRing;\r
- CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;\r
- INPUT_CONTEXT_64 *InputContext;\r
- DEVICE_CONTEXT_64 *OutputContext;\r
- EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
+ EFI_STATUS Status;\r
+ USB_INTERFACE_DESCRIPTOR *IfDesc;\r
+ USB_ENDPOINT_DESCRIPTOR *EpDesc;\r
+ UINT8 Index;\r
+ UINTN NumEp;\r
+ UINTN EpIndex;\r
+ UINT8 EpAddr;\r
+ EFI_USB_DATA_DIRECTION Direction;\r
+ UINT8 Dci;\r
+ UINT8 MaxDci;\r
+ EFI_PHYSICAL_ADDRESS PhyAddr;\r
+ UINT8 Interval;\r
+\r
+ TRANSFER_RING *EndpointTransferRing;\r
+ CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;\r
+ INPUT_CONTEXT_64 *InputContext;\r
+ DEVICE_CONTEXT_64 *OutputContext;\r
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
+\r
//\r
// 4.6.6 Configure Endpoint\r
//\r
\r
MaxDci = 0;\r
\r
- IfDesc = (USB_INTERFACE_DESCRIPTOR *) (ConfigDesc + 1);\r
+ IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);\r
for (Index = 0; Index < ConfigDesc->NumInterfaces; Index++) {\r
while ((IfDesc->DescriptorType != USB_DESC_TYPE_INTERFACE) || (IfDesc->AlternateSetting != 0)) {\r
- IfDesc = (USB_INTERFACE_DESCRIPTOR *) ((UINTN) IfDesc + IfDesc->Length);\r
+ IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r
}\r
\r
NumEp = IfDesc->NumEndpoints;\r
\r
- EpDesc = (USB_ENDPOINT_DESCRIPTOR *) (IfDesc + 1);\r
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDesc + 1);\r
for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {\r
while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {\r
- EpDesc = (USB_ENDPOINT_DESCRIPTOR *) ((UINTN) EpDesc + EpDesc->Length);\r
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
}\r
\r
- EpAddr = (UINT8) (EpDesc->EndpointAddress & 0x0F);\r
- Direction = (UINT8) ((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);\r
+ EpAddr = (UINT8)(EpDesc->EndpointAddress & 0x0F);\r
+ Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);\r
\r
Dci = XhcPeiEndpointToDci (EpAddr, Direction);\r
ASSERT (Dci < 32);\r
\r
InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {\r
- EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));\r
- Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;\r
- XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);\r
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));\r
+ Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *)EndpointTransferRing;\r
+ XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);\r
}\r
\r
break;\r
InputContext->EP[Dci-1].CErr = 0;\r
InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;\r
}\r
+\r
//\r
// Get the bInterval from descriptor and init the the interval field of endpoint context.\r
// Refer to XHCI 1.1 spec section 6.2.3.6.\r
InputContext->EP[Dci-1].CErr = 3;\r
InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;\r
}\r
+\r
InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r
InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;\r
//\r
// Calculate through the bInterval field of Endpoint descriptor.\r
//\r
ASSERT (Interval != 0);\r
- InputContext->EP[Dci-1].Interval = (UINT32) HighBitSet32( (UINT32) Interval) + 3;\r
+ InputContext->EP[Dci-1].Interval = (UINT32)HighBitSet32 ((UINT32)Interval) + 3;\r
} else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {\r
Interval = EpDesc->Interval;\r
ASSERT (Interval >= 1 && Interval <= 16);\r
}\r
\r
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {\r
- EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));\r
- Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;\r
- XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);\r
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));\r
+ Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *)EndpointTransferRing;\r
+ XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);\r
}\r
+\r
break;\r
\r
case USB_ENDPOINT_CONTROL:\r
\r
PhyAddr = UsbHcGetPciAddrForHostAddr (\r
Xhc->MemPool,\r
- ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,\r
+ ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,\r
sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER\r
);\r
\r
PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);\r
- PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;\r
+ PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;\r
\r
InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);\r
InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
\r
- EpDesc = (USB_ENDPOINT_DESCRIPTOR *) ((UINTN)EpDesc + EpDesc->Length);\r
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
}\r
- IfDesc = (USB_INTERFACE_DESCRIPTOR *) ((UINTN)IfDesc + IfDesc->Length);\r
+\r
+ IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r
}\r
\r
InputContext->InputControlContext.Dword2 |= BIT0;\r
// configure endpoint\r
//\r
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));\r
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));\r
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));\r
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);\r
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
CmdTrbCfgEP.CycleBit = 1;\r
DEBUG ((DEBUG_INFO, "XhcSetConfigCmd64: Configure Endpoint\n"));\r
Status = XhcPeiCmdTransfer (\r
Xhc,\r
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,\r
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,\r
XHC_GENERIC_TIMEOUT,\r
- (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb\r
);\r
if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "XhcSetConfigCmd64: Config Endpoint Failed, Status = %r\n", Status));\r
return Status;\r
}\r
\r
-\r
/**\r
Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.\r
\r
**/\r
EFI_STATUS\r
XhcPeiEvaluateContext (\r
- IN PEI_XHC_DEV *Xhc,\r
- IN UINT8 SlotId,\r
- IN UINT32 MaxPacketSize\r
+ IN PEI_XHC_DEV *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT32 MaxPacketSize\r
)\r
{\r
- EFI_STATUS Status;\r
- CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu;\r
- EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
- INPUT_CONTEXT *InputContext;\r
- EFI_PHYSICAL_ADDRESS PhyAddr;\r
+ EFI_STATUS Status;\r
+ CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu;\r
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
+ INPUT_CONTEXT *InputContext;\r
+ EFI_PHYSICAL_ADDRESS PhyAddr;\r
\r
ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);\r
\r
InputContext->EP[0].MaxPacketSize = MaxPacketSize;\r
\r
ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));\r
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));\r
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));\r
CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (PhyAddr);\r
CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
CmdTrbEvalu.CycleBit = 1;\r
DEBUG ((DEBUG_INFO, "XhcEvaluateContext: Evaluate context\n"));\r
Status = XhcPeiCmdTransfer (\r
Xhc,\r
- (TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,\r
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbEvalu,\r
XHC_GENERIC_TIMEOUT,\r
- (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb\r
);\r
if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "XhcEvaluateContext: Evaluate Context Failed, Status = %r\n", Status));\r
}\r
+\r
return Status;\r
}\r
\r
**/\r
EFI_STATUS\r
XhcPeiEvaluateContext64 (\r
- IN PEI_XHC_DEV *Xhc,\r
- IN UINT8 SlotId,\r
- IN UINT32 MaxPacketSize\r
+ IN PEI_XHC_DEV *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT32 MaxPacketSize\r
)\r
{\r
- EFI_STATUS Status;\r
- CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu;\r
- EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
- INPUT_CONTEXT_64 *InputContext;\r
- EFI_PHYSICAL_ADDRESS PhyAddr;\r
+ EFI_STATUS Status;\r
+ CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu;\r
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
+ INPUT_CONTEXT_64 *InputContext;\r
+ EFI_PHYSICAL_ADDRESS PhyAddr;\r
\r
ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);\r
\r
InputContext->EP[0].MaxPacketSize = MaxPacketSize;\r
\r
ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));\r
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));\r
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));\r
CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (PhyAddr);\r
CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
CmdTrbEvalu.CycleBit = 1;\r
DEBUG ((DEBUG_INFO, "XhcEvaluateContext64: Evaluate context 64\n"));\r
Status = XhcPeiCmdTransfer (\r
Xhc,\r
- (TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,\r
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbEvalu,\r
XHC_GENERIC_TIMEOUT,\r
- (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb\r
);\r
if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "XhcEvaluateContext64: Evaluate Context Failed, Status = %r\n", Status));\r
}\r
+\r
return Status;\r
}\r
\r
**/\r
EFI_STATUS\r
XhcPeiConfigHubContext (\r
- IN PEI_XHC_DEV *Xhc,\r
- IN UINT8 SlotId,\r
- IN UINT8 PortNum,\r
- IN UINT8 TTT,\r
- IN UINT8 MTT\r
+ IN PEI_XHC_DEV *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 PortNum,\r
+ IN UINT8 TTT,\r
+ IN UINT8 MTT\r
)\r
{\r
- EFI_STATUS Status;\r
- EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
- INPUT_CONTEXT *InputContext;\r
- DEVICE_CONTEXT *OutputContext;\r
- CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;\r
- EFI_PHYSICAL_ADDRESS PhyAddr;\r
+ EFI_STATUS Status;\r
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
+ INPUT_CONTEXT *InputContext;\r
+ DEVICE_CONTEXT *OutputContext;\r
+ CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;\r
+ EFI_PHYSICAL_ADDRESS PhyAddr;\r
\r
ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);\r
InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r
//\r
// Copy the slot context from OutputContext to Input context\r
//\r
- CopyMem(&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT));\r
+ CopyMem (&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT));\r
InputContext->Slot.Hub = 1;\r
InputContext->Slot.PortNum = PortNum;\r
InputContext->Slot.TTT = TTT;\r
InputContext->Slot.MTT = MTT;\r
\r
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));\r
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));\r
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));\r
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);\r
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
CmdTrbCfgEP.CycleBit = 1;\r
DEBUG ((DEBUG_INFO, "Configure Hub Slot Context\n"));\r
Status = XhcPeiCmdTransfer (\r
Xhc,\r
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,\r
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,\r
XHC_GENERIC_TIMEOUT,\r
- (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb\r
);\r
if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "XhcConfigHubContext: Config Endpoint Failed, Status = %r\n", Status));\r
}\r
+\r
return Status;\r
}\r
\r
**/\r
EFI_STATUS\r
XhcPeiConfigHubContext64 (\r
- IN PEI_XHC_DEV *Xhc,\r
- IN UINT8 SlotId,\r
- IN UINT8 PortNum,\r
- IN UINT8 TTT,\r
- IN UINT8 MTT\r
+ IN PEI_XHC_DEV *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 PortNum,\r
+ IN UINT8 TTT,\r
+ IN UINT8 MTT\r
)\r
{\r
- EFI_STATUS Status;\r
- EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
- INPUT_CONTEXT_64 *InputContext;\r
- DEVICE_CONTEXT_64 *OutputContext;\r
- CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;\r
- EFI_PHYSICAL_ADDRESS PhyAddr;\r
+ EFI_STATUS Status;\r
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
+ INPUT_CONTEXT_64 *InputContext;\r
+ DEVICE_CONTEXT_64 *OutputContext;\r
+ CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;\r
+ EFI_PHYSICAL_ADDRESS PhyAddr;\r
\r
ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);\r
InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r
//\r
// Copy the slot context from OutputContext to Input context\r
//\r
- CopyMem(&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT_64));\r
+ CopyMem (&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT_64));\r
InputContext->Slot.Hub = 1;\r
InputContext->Slot.PortNum = PortNum;\r
InputContext->Slot.TTT = TTT;\r
InputContext->Slot.MTT = MTT;\r
\r
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));\r
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));\r
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));\r
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);\r
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
CmdTrbCfgEP.CycleBit = 1;\r
DEBUG ((DEBUG_INFO, "Configure Hub Slot Context 64\n"));\r
Status = XhcPeiCmdTransfer (\r
Xhc,\r
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,\r
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,\r
XHC_GENERIC_TIMEOUT,\r
- (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb\r
);\r
if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "XhcConfigHubContext64: Config Endpoint Failed, Status = %r\n", Status));\r
}\r
+\r
return Status;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
XhcPeiStopEndpoint (\r
- IN PEI_XHC_DEV *Xhc,\r
- IN UINT8 SlotId,\r
- IN UINT8 Dci\r
+ IN PEI_XHC_DEV *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 Dci\r
)\r
{\r
- EFI_STATUS Status;\r
- EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
- CMD_TRB_STOP_ENDPOINT CmdTrbStopED;\r
+ EFI_STATUS Status;\r
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
+ CMD_TRB_STOP_ENDPOINT CmdTrbStopED;\r
\r
DEBUG ((DEBUG_INFO, "XhcPeiStopEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId, Dci));\r
\r
CmdTrbStopED.Type = TRB_TYPE_STOP_ENDPOINT;\r
CmdTrbStopED.EDID = Dci;\r
CmdTrbStopED.SlotId = SlotId;\r
- Status = XhcPeiCmdTransfer (\r
- Xhc,\r
- (TRB_TEMPLATE *) (UINTN) &CmdTrbStopED,\r
- XHC_GENERIC_TIMEOUT,\r
- (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
- );\r
- if (EFI_ERROR(Status)) {\r
+ Status = XhcPeiCmdTransfer (\r
+ Xhc,\r
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbStopED,\r
+ XHC_GENERIC_TIMEOUT,\r
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "XhcPeiStopEndpoint: Stop Endpoint Failed, Status = %r\n", Status));\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
XhcPeiResetEndpoint (\r
- IN PEI_XHC_DEV *Xhc,\r
- IN UINT8 SlotId,\r
- IN UINT8 Dci\r
+ IN PEI_XHC_DEV *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 Dci\r
)\r
{\r
EFI_STATUS Status;\r
CmdTrbResetED.Type = TRB_TYPE_RESET_ENDPOINT;\r
CmdTrbResetED.EDID = Dci;\r
CmdTrbResetED.SlotId = SlotId;\r
- Status = XhcPeiCmdTransfer (\r
- Xhc,\r
- (TRB_TEMPLATE *) (UINTN) &CmdTrbResetED,\r
- XHC_GENERIC_TIMEOUT,\r
- (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
- );\r
- if (EFI_ERROR(Status)) {\r
+ Status = XhcPeiCmdTransfer (\r
+ Xhc,\r
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbResetED,\r
+ XHC_GENERIC_TIMEOUT,\r
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "XhcPeiResetEndpoint: Reset Endpoint Failed, Status = %r\n", Status));\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
XhcPeiSetTrDequeuePointer (\r
- IN PEI_XHC_DEV *Xhc,\r
- IN UINT8 SlotId,\r
- IN UINT8 Dci,\r
- IN URB *Urb\r
+ IN PEI_XHC_DEV *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 Dci,\r
+ IN URB *Urb\r
)\r
{\r
EFI_STATUS Status;\r
// Send stop endpoint command to transit Endpoint from running to stop state\r
//\r
ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq));\r
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER));\r
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER));\r
CmdSetTRDeq.PtrLo = XHC_LOW_32BIT (PhyAddr) | Urb->Ring->RingPCS;\r
CmdSetTRDeq.PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
CmdSetTRDeq.CycleBit = 1;\r
CmdSetTRDeq.Type = TRB_TYPE_SET_TR_DEQUE;\r
CmdSetTRDeq.Endpoint = Dci;\r
CmdSetTRDeq.SlotId = SlotId;\r
- Status = XhcPeiCmdTransfer (\r
- Xhc,\r
- (TRB_TEMPLATE *) (UINTN) &CmdSetTRDeq,\r
- XHC_GENERIC_TIMEOUT,\r
- (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
- );\r
- if (EFI_ERROR(Status)) {\r
+ Status = XhcPeiCmdTransfer (\r
+ Xhc,\r
+ (TRB_TEMPLATE *)(UINTN)&CmdSetTRDeq,\r
+ XHC_GENERIC_TIMEOUT,\r
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "XhcPeiSetTrDequeuePointer: Set TR Dequeue Pointer Failed, Status = %r\n", Status));\r
}\r
\r
**/\r
EFI_STATUS\r
XhcPeiCheckNewEvent (\r
- IN PEI_XHC_DEV *Xhc,\r
- IN EVENT_RING *EvtRing,\r
- OUT TRB_TEMPLATE **NewEvtTrb\r
+ IN PEI_XHC_DEV *Xhc,\r
+ IN EVENT_RING *EvtRing,\r
+ OUT TRB_TEMPLATE **NewEvtTrb\r
)\r
{\r
ASSERT (EvtRing != NULL);\r
//\r
// If the dequeue pointer is beyond the ring, then roll-back it to the begining of the ring.\r
//\r
- if ((UINTN) EvtRing->EventRingDequeue >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {\r
+ if ((UINTN)EvtRing->EventRingDequeue >= ((UINTN)EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {\r
EvtRing->EventRingDequeue = EvtRing->EventRingSeg0;\r
}\r
\r
**/\r
EFI_STATUS\r
XhcPeiSyncEventRing (\r
- IN PEI_XHC_DEV *Xhc,\r
- IN EVENT_RING *EvtRing\r
+ IN PEI_XHC_DEV *Xhc,\r
+ IN EVENT_RING *EvtRing\r
)\r
{\r
- UINTN Index;\r
- TRB_TEMPLATE *EvtTrb;\r
+ UINTN Index;\r
+ TRB_TEMPLATE *EvtTrb;\r
\r
ASSERT (EvtRing != NULL);\r
\r
\r
EvtTrb++;\r
\r
- if ((UINTN) EvtTrb >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {\r
- EvtTrb = EvtRing->EventRingSeg0;\r
+ if ((UINTN)EvtTrb >= ((UINTN)EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {\r
+ EvtTrb = EvtRing->EventRingSeg0;\r
EvtRing->EventRingCCS = (EvtRing->EventRingCCS) ? 0 : 1;\r
}\r
}\r
**/\r
VOID\r
XhcPeiFreeEventRing (\r
- IN PEI_XHC_DEV *Xhc,\r
- IN EVENT_RING *EventRing\r
+ IN PEI_XHC_DEV *Xhc,\r
+ IN EVENT_RING *EventRing\r
)\r
{\r
- if(EventRing->EventRingSeg0 == NULL) {\r
+ if (EventRing->EventRingSeg0 == NULL) {\r
return;\r
}\r
\r
**/\r
VOID\r
XhcPeiCreateEventRing (\r
- IN PEI_XHC_DEV *Xhc,\r
- OUT EVENT_RING *EventRing\r
+ IN PEI_XHC_DEV *Xhc,\r
+ OUT EVENT_RING *EventRing\r
)\r
{\r
- VOID *Buf;\r
- EVENT_RING_SEG_TABLE_ENTRY *ERSTBase;\r
- UINTN Size;\r
- EFI_PHYSICAL_ADDRESS ERSTPhy;\r
- EFI_PHYSICAL_ADDRESS DequeuePhy;\r
+ VOID *Buf;\r
+ EVENT_RING_SEG_TABLE_ENTRY *ERSTBase;\r
+ UINTN Size;\r
+ EFI_PHYSICAL_ADDRESS ERSTPhy;\r
+ EFI_PHYSICAL_ADDRESS DequeuePhy;\r
\r
ASSERT (EventRing != NULL);\r
\r
Size = sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER;\r
- Buf = UsbHcAllocateMem (Xhc->MemPool, Size);\r
+ Buf = UsbHcAllocateMem (Xhc->MemPool, Size);\r
ASSERT (Buf != NULL);\r
- ASSERT (((UINTN) Buf & 0x3F) == 0);\r
+ ASSERT (((UINTN)Buf & 0x3F) == 0);\r
ZeroMem (Buf, Size);\r
\r
DequeuePhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size);\r
\r
- EventRing->EventRingSeg0 = Buf;\r
- EventRing->TrbNumber = EVENT_RING_TRB_NUMBER;\r
- EventRing->EventRingDequeue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;\r
- EventRing->EventRingEnqueue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;\r
+ EventRing->EventRingSeg0 = Buf;\r
+ EventRing->TrbNumber = EVENT_RING_TRB_NUMBER;\r
+ EventRing->EventRingDequeue = (TRB_TEMPLATE *)EventRing->EventRingSeg0;\r
+ EventRing->EventRingEnqueue = (TRB_TEMPLATE *)EventRing->EventRingSeg0;\r
\r
//\r
// Software maintains an Event Ring Consumer Cycle State (CCS) bit, initializing it to '1'\r
EventRing->EventRingCCS = 1;\r
\r
Size = sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER;\r
- Buf = UsbHcAllocateMem (Xhc->MemPool, Size);\r
+ Buf = UsbHcAllocateMem (Xhc->MemPool, Size);\r
ASSERT (Buf != NULL);\r
- ASSERT (((UINTN) Buf & 0x3F) == 0);\r
+ ASSERT (((UINTN)Buf & 0x3F) == 0);\r
ZeroMem (Buf, Size);\r
\r
- ERSTBase = (EVENT_RING_SEG_TABLE_ENTRY *) Buf;\r
+ ERSTBase = (EVENT_RING_SEG_TABLE_ENTRY *)Buf;\r
EventRing->ERSTBase = ERSTBase;\r
ERSTBase->PtrLo = XHC_LOW_32BIT (DequeuePhy);\r
ERSTBase->PtrHi = XHC_HIGH_32BIT (DequeuePhy);\r
XhcPeiWriteRuntimeReg (\r
Xhc,\r
XHC_ERDP_OFFSET,\r
- XHC_LOW_32BIT ((UINT64) (UINTN) DequeuePhy)\r
+ XHC_LOW_32BIT ((UINT64)(UINTN)DequeuePhy)\r
);\r
XhcPeiWriteRuntimeReg (\r
Xhc,\r
XHC_ERDP_OFFSET + 4,\r
- XHC_HIGH_32BIT ((UINT64) (UINTN) DequeuePhy)\r
+ XHC_HIGH_32BIT ((UINT64)(UINTN)DequeuePhy)\r
);\r
//\r
// Program the Interrupter Event Ring Segment Table Base Address (ERSTBA) register (5.5.2.3.2)\r
XhcPeiWriteRuntimeReg (\r
Xhc,\r
XHC_ERSTBA_OFFSET,\r
- XHC_LOW_32BIT ((UINT64) (UINTN) ERSTPhy)\r
+ XHC_LOW_32BIT ((UINT64)(UINTN)ERSTPhy)\r
);\r
XhcPeiWriteRuntimeReg (\r
Xhc,\r
XHC_ERSTBA_OFFSET + 4,\r
- XHC_HIGH_32BIT ((UINT64) (UINTN) ERSTPhy)\r
+ XHC_HIGH_32BIT ((UINT64)(UINTN)ERSTPhy)\r
);\r
//\r
// Need set IMAN IE bit to enable the ring interrupt\r
IN TRANSFER_RING *TrsRing\r
)\r
{\r
- UINTN Index;\r
- TRB_TEMPLATE *TrsTrb;\r
+ UINTN Index;\r
+ TRB_TEMPLATE *TrsTrb;\r
\r
ASSERT (TrsRing != NULL);\r
//\r
if (TrsTrb->CycleBit != (TrsRing->RingPCS & BIT0)) {\r
break;\r
}\r
+\r
TrsTrb++;\r
- if ((UINT8) TrsTrb->Type == TRB_TYPE_LINK) {\r
- ASSERT (((LINK_TRB *) TrsTrb)->TC != 0);\r
+ if ((UINT8)TrsTrb->Type == TRB_TYPE_LINK) {\r
+ ASSERT (((LINK_TRB *)TrsTrb)->TC != 0);\r
//\r
// set cycle bit in Link TRB as normal\r
//\r
- ((LINK_TRB*)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0;\r
+ ((LINK_TRB *)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0;\r
//\r
// Toggle PCS maintained by software\r
//\r
TrsRing->RingPCS = (TrsRing->RingPCS & BIT0) ? 0 : 1;\r
- TrsTrb = (TRB_TEMPLATE *) TrsRing->RingSeg0; // Use host address\r
+ TrsTrb = (TRB_TEMPLATE *)TrsRing->RingSeg0; // Use host address\r
}\r
}\r
\r
**/\r
VOID\r
XhcPeiCreateTransferRing (\r
- IN PEI_XHC_DEV *Xhc,\r
- IN UINTN TrbNum,\r
- OUT TRANSFER_RING *TransferRing\r
+ IN PEI_XHC_DEV *Xhc,\r
+ IN UINTN TrbNum,\r
+ OUT TRANSFER_RING *TransferRing\r
)\r
{\r
VOID *Buf;\r
\r
Buf = UsbHcAllocateMem (Xhc->MemPool, sizeof (TRB_TEMPLATE) * TrbNum);\r
ASSERT (Buf != NULL);\r
- ASSERT (((UINTN) Buf & 0x3F) == 0);\r
+ ASSERT (((UINTN)Buf & 0x3F) == 0);\r
ZeroMem (Buf, sizeof (TRB_TEMPLATE) * TrbNum);\r
\r
- TransferRing->RingSeg0 = Buf;\r
- TransferRing->TrbNumber = TrbNum;\r
- TransferRing->RingEnqueue = (TRB_TEMPLATE *) TransferRing->RingSeg0;\r
- TransferRing->RingDequeue = (TRB_TEMPLATE *) TransferRing->RingSeg0;\r
- TransferRing->RingPCS = 1;\r
+ TransferRing->RingSeg0 = Buf;\r
+ TransferRing->TrbNumber = TrbNum;\r
+ TransferRing->RingEnqueue = (TRB_TEMPLATE *)TransferRing->RingSeg0;\r
+ TransferRing->RingDequeue = (TRB_TEMPLATE *)TransferRing->RingSeg0;\r
+ TransferRing->RingPCS = 1;\r
//\r
// 4.9.2 Transfer Ring Management\r
// To form a ring (or circular queue) a Link TRB may be inserted at the end of a ring to\r
// point to the first TRB in the ring.\r
//\r
- EndTrb = (LINK_TRB *) ((UINTN) Buf + sizeof (TRB_TEMPLATE) * (TrbNum - 1));\r
+ EndTrb = (LINK_TRB *)((UINTN)Buf + sizeof (TRB_TEMPLATE) * (TrbNum - 1));\r
EndTrb->Type = TRB_TYPE_LINK;\r
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof (TRB_TEMPLATE) * TrbNum);\r
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof (TRB_TEMPLATE) * TrbNum);\r
EndTrb->PtrLo = XHC_LOW_32BIT (PhyAddr);\r
EndTrb->PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
//\r
// Toggle Cycle (TC). When set to '1', the xHC shall toggle its interpretation of the Cycle bit.\r
//\r
- EndTrb->TC = 1;\r
+ EndTrb->TC = 1;\r
//\r
// Set Cycle bit as other TRB PCS init value\r
//\r
**/\r
VOID\r
XhcPeiInitSched (\r
- IN PEI_XHC_DEV *Xhc\r
+ IN PEI_XHC_DEV *Xhc\r
)\r
{\r
VOID *Dcbaa;\r
// The Device Context Base Address Array shall contain MaxSlotsEn + 1 entries.\r
// Software shall set Device Context Base Address Array entries for unallocated Device Slots to '0'.\r
//\r
- Size = (Xhc->MaxSlotsEn + 1) * sizeof (UINT64);\r
+ Size = (Xhc->MaxSlotsEn + 1) * sizeof (UINT64);\r
Dcbaa = UsbHcAllocateMem (Xhc->MemPool, Size);\r
ASSERT (Dcbaa != NULL);\r
\r
Xhc->ScratchEntry = ScratchEntry;\r
\r
ScratchPhy = 0;\r
- Status = UsbHcAllocateAlignedPages (\r
- EFI_SIZE_TO_PAGES (MaxScratchpadBufs * sizeof (UINT64)),\r
- Xhc->PageSize,\r
- (VOID **) &ScratchBuf,\r
- &ScratchPhy,\r
- &Xhc->ScratchMap\r
- );\r
+ Status = UsbHcAllocateAlignedPages (\r
+ EFI_SIZE_TO_PAGES (MaxScratchpadBufs * sizeof (UINT64)),\r
+ Xhc->PageSize,\r
+ (VOID **)&ScratchBuf,\r
+ &ScratchPhy,\r
+ &Xhc->ScratchMap\r
+ );\r
ASSERT_EFI_ERROR (Status);\r
\r
ZeroMem (ScratchBuf, MaxScratchpadBufs * sizeof (UINT64));\r
//\r
for (Index = 0; Index < MaxScratchpadBufs; Index++) {\r
ScratchEntryPhy = 0;\r
- Status = UsbHcAllocateAlignedPages (\r
- EFI_SIZE_TO_PAGES (Xhc->PageSize),\r
- Xhc->PageSize,\r
- (VOID **) &ScratchEntry[Index],\r
- &ScratchEntryPhy,\r
- (VOID **) &ScratchEntryMap[Index]\r
- );\r
+ Status = UsbHcAllocateAlignedPages (\r
+ EFI_SIZE_TO_PAGES (Xhc->PageSize),\r
+ Xhc->PageSize,\r
+ (VOID **)&ScratchEntry[Index],\r
+ &ScratchEntryPhy,\r
+ (VOID **)&ScratchEntryMap[Index]\r
+ );\r
ASSERT_EFI_ERROR (Status);\r
- ZeroMem ((VOID *) (UINTN) ScratchEntry[Index], Xhc->PageSize);\r
+ ZeroMem ((VOID *)(UINTN)ScratchEntry[Index], Xhc->PageSize);\r
//\r
// Fill with the PCI device address\r
//\r
*ScratchBuf++ = ScratchEntryPhy;\r
}\r
+\r
//\r
// The Scratchpad Buffer Array contains pointers to the Scratchpad Buffers. Entry 0 of the\r
// Device Context Base Address Array points to the Scratchpad Buffer Array.\r
//\r
- *(UINT64 *) Dcbaa = (UINT64) (UINTN) ScratchPhy;\r
+ *(UINT64 *)Dcbaa = (UINT64)(UINTN)ScratchPhy;\r
}\r
\r
//\r
// Program the Device Context Base Address Array Pointer (DCBAAP) register (5.4.6) with\r
// a 64-bit address pointing to where the Device Context Base Address Array is located.\r
//\r
- Xhc->DCBAA = (UINT64 *) (UINTN) Dcbaa;\r
+ Xhc->DCBAA = (UINT64 *)(UINTN)Dcbaa;\r
//\r
// Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r
// So divide it to two 32-bytes width register access.\r
**/\r
VOID\r
XhcPeiFreeSched (\r
- IN PEI_XHC_DEV *Xhc\r
+ IN PEI_XHC_DEV *Xhc\r
)\r
{\r
- UINT32 Index;\r
- UINT64 *ScratchEntry;\r
+ UINT32 Index;\r
+ UINT64 *ScratchEntry;\r
\r
if (Xhc->ScratchBuf != NULL) {\r
ScratchEntry = Xhc->ScratchEntry;\r
//\r
// Free Scratchpad Buffers\r
//\r
- UsbHcFreeAlignedPages ((VOID*) (UINTN) ScratchEntry[Index], EFI_SIZE_TO_PAGES (Xhc->PageSize), (VOID *) Xhc->ScratchEntryMap[Index]);\r
+ UsbHcFreeAlignedPages ((VOID *)(UINTN)ScratchEntry[Index], EFI_SIZE_TO_PAGES (Xhc->PageSize), (VOID *)Xhc->ScratchEntryMap[Index]);\r
}\r
+\r
//\r
// Free Scratchpad Buffer Array\r
//\r
Xhc->CmdRing.RingSeg0 = NULL;\r
}\r
\r
- XhcPeiFreeEventRing (Xhc,&Xhc->EventRing);\r
+ XhcPeiFreeEventRing (Xhc, &Xhc->EventRing);\r
\r
if (Xhc->DCBAA != NULL) {\r
UsbHcFreeMem (Xhc->MemPool, Xhc->DCBAA, (Xhc->MaxSlotsEn + 1) * sizeof (UINT64));\r
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