/** @file\r
- Ia32-specifc functionality for DxeLoad.\r
+ Ia32-specific functionality for DxeLoad.\r
\r
Copyright (c) 2006 - 2008, Intel Corporation. <BR>\r
All rights reserved. This program and the accompanying materials\r
//\r
// Global Descriptor Table (GDT)\r
//\r
-GLOBAL_REMOVE_IF_UNREFERENCED IA32_GDT gGdtEntries [] = {\r
+GLOBAL_REMOVE_IF_UNREFERENCED IA32_GDT gGdtEntries[] = {\r
/* selector { Global Segment Descriptor } */ \r
/* 0x00 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, //null descriptor \r
/* 0x08 */ {{0xffff, 0, 0, 0x2, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}}, //linear data segment descriptor\r
0\r
};\r
\r
-\r
-\r
-\r
-\r
/**\r
Transfers control to DxeCore.\r
\r
This function performs a CPU architecture specific operations to execute\r
the entry point of DxeCore with the parameters of HobList.\r
- It also intalls EFI_END_OF_PEI_PPI to signal the end of PEI phase.\r
+ It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.\r
\r
- @param DxeCoreEntryPoint The entrypoint of DxeCore.\r
+ @param DxeCoreEntryPoint The entry point of DxeCore.\r
@param HobList The start of HobList passed to DxeCore.\r
- @param EndOfPeiSignal The PPI descriptor for EFI_END_OF_PEI_PPI.\r
\r
**/\r
VOID\r
HandOffToDxeCore (\r
IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,\r
- IN EFI_PEI_HOB_POINTERS HobList,\r
- IN EFI_PEI_PPI_DESCRIPTOR *EndOfPeiSignal\r
+ IN EFI_PEI_HOB_POINTERS HobList\r
)\r
{\r
EFI_STATUS Status;\r
TopOfStack = BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - 32;\r
\r
//\r
- // X64 Calling Conventions requires that the stack must be aligned to 16 bytes\r
+ // x64 Calling Conventions requires that the stack must be aligned to 16 bytes\r
//\r
TopOfStack = (EFI_PHYSICAL_ADDRESS) (UINTN) ALIGN_POINTER (TopOfStack, 16);\r
\r
PageTables = CreateIdentityMappingPageTables ();\r
\r
//\r
- // End of PEI phase singal\r
+ // End of PEI phase signal\r
//\r
- Status = PeiServicesInstallPpi (EndOfPeiSignal);\r
+ Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);\r
ASSERT_EFI_ERROR (Status);\r
\r
AsmWriteCr3 (PageTables);\r
// \r
UpdateStackHob (BaseOfStack, STACK_SIZE);\r
\r
- if (FeaturePcdGet (PcdDxeIplEnableIdt)) {\r
- SizeOfTemplate = AsmGetVectorTemplatInfo (&TemplateBase);\r
- \r
- Status = PeiServicesAllocatePages (\r
- EfiBootServicesData, \r
- EFI_SIZE_TO_PAGES((SizeOfTemplate + sizeof (X64_IDT_GATE_DESCRIPTOR)) * 32), \r
- &VectorAddress\r
- );\r
- \r
- ASSERT_EFI_ERROR (Status);\r
- \r
- IdtTable = (X64_IDT_GATE_DESCRIPTOR *) (UINTN) (VectorAddress + SizeOfTemplate * 32);\r
- for (Index = 0; Index < 32; Index++) {\r
- IdtTable[Index].Ia32IdtEntry.Bits.GateType = 0x8e;\r
- IdtTable[Index].Ia32IdtEntry.Bits.Reserved_0 = 0;\r
- IdtTable[Index].Ia32IdtEntry.Bits.Selector = SYS_CODE64_SEL;\r
- \r
- IdtTable[Index].Ia32IdtEntry.Bits.OffsetLow = (UINT16) VectorAddress;\r
- IdtTable[Index].Ia32IdtEntry.Bits.OffsetHigh = (UINT16) (RShiftU64 (VectorAddress, 16));\r
- IdtTable[Index].Offset32To63 = (UINT32) (RShiftU64 (VectorAddress, 32));\r
- IdtTable[Index].Reserved = 0;\r
- \r
- CopyMem ((VOID *) (UINTN) VectorAddress, TemplateBase, SizeOfTemplate);\r
- AsmVectorFixup ((VOID *) (UINTN) VectorAddress, (UINT8) Index);\r
- \r
- VectorAddress += SizeOfTemplate;\r
- }\r
- \r
- gLidtDescriptor.Base = (UINTN) IdtTable;\r
- AsmWriteIdtr (&gLidtDescriptor);\r
+ SizeOfTemplate = AsmGetVectorTemplatInfo (&TemplateBase);\r
+\r
+ Status = PeiServicesAllocatePages (\r
+ EfiBootServicesData, \r
+ EFI_SIZE_TO_PAGES((SizeOfTemplate + sizeof (X64_IDT_GATE_DESCRIPTOR)) * 32), \r
+ &VectorAddress\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ IdtTable = (X64_IDT_GATE_DESCRIPTOR *) (UINTN) (VectorAddress + SizeOfTemplate * 32);\r
+ for (Index = 0; Index < 32; Index++) {\r
+ IdtTable[Index].Ia32IdtEntry.Bits.GateType = 0x8e;\r
+ IdtTable[Index].Ia32IdtEntry.Bits.Reserved_0 = 0;\r
+ IdtTable[Index].Ia32IdtEntry.Bits.Selector = SYS_CODE64_SEL;\r
+\r
+ IdtTable[Index].Ia32IdtEntry.Bits.OffsetLow = (UINT16) VectorAddress;\r
+ IdtTable[Index].Ia32IdtEntry.Bits.OffsetHigh = (UINT16) (RShiftU64 (VectorAddress, 16));\r
+ IdtTable[Index].Offset32To63 = (UINT32) (RShiftU64 (VectorAddress, 32));\r
+ IdtTable[Index].Reserved = 0;\r
+\r
+ CopyMem ((VOID *) (UINTN) VectorAddress, TemplateBase, SizeOfTemplate);\r
+ AsmVectorFixup ((VOID *) (UINTN) VectorAddress, (UINT8) Index);\r
+\r
+ VectorAddress += SizeOfTemplate;\r
}\r
+\r
+ gLidtDescriptor.Base = (UINTN) IdtTable;\r
+ AsmWriteIdtr (&gLidtDescriptor);\r
+\r
+ \r
//\r
- // Go to Long Mode. Interrupts will not get turned on until the CPU AP is loaded.\r
+ // Go to Long Mode and transfer control to DxeCore.\r
+ // Interrupts will not get turned on until the CPU AP is loaded.\r
// Call x64 drivers passing in single argument, a pointer to the HOBs.\r
// \r
AsmEnablePaging64 (\r
TopOfStack = (EFI_PHYSICAL_ADDRESS) (UINTN) ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT);\r
\r
//\r
- // End of PEI phase singal\r
+ // End of PEI phase signal\r
//\r
- Status = PeiServicesInstallPpi (EndOfPeiSignal);\r
+ Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);\r
ASSERT_EFI_ERROR (Status);\r
\r
//\r
// Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore.\r
// \r
UpdateStackHob (BaseOfStack, STACK_SIZE);\r
-\r
+ \r
+ //\r
+ // Transfer the control to the entry point of DxeCore.\r
+ //\r
SwitchStack (\r
(SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,\r
HobList.Raw,\r