/** @file\r
SMM IPL that produces SMM related runtime protocols and load the SMM Core into SMRAM\r
\r
- Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials are licensed and made available \r
under the terms and conditions of the BSD License which accompanies this \r
distribution. The full text of the license may be found at \r
//\r
{ TRUE, FALSE, &gEfiSmmConfigurationProtocolGuid, SmmIplSmmConfigurationEventNotify, &gEfiSmmConfigurationProtocolGuid, TPL_NOTIFY, NULL },\r
//\r
- // Declare protocl notification on DxeSmmReadyToLock protocols. When this notification is etablished, \r
+ // Declare protocol notification on DxeSmmReadyToLock protocols. When this notification is established, \r
// the associated event is immediately signalled, so the notification function will be executed and the \r
// DXE SMM Ready To Lock Protocol will be found if it is already in the handle database.\r
//\r
{ TRUE, TRUE, &gEfiDxeSmmReadyToLockProtocolGuid, SmmIplReadyToLockEventNotify, &gEfiDxeSmmReadyToLockProtocolGuid, TPL_CALLBACK, NULL },\r
//\r
+ // Declare event notification on EndOfDxe event. When this notification is etablished, \r
+ // the associated event is immediately signalled, so the notification function will be executed and the \r
+ // SMM End Of Dxe Protocol will be found if it is already in the handle database.\r
+ //\r
+ { FALSE, FALSE, &gEfiEndOfDxeEventGroupGuid, SmmIplGuidedEventNotify, &gEfiEndOfDxeEventGroupGuid, TPL_CALLBACK, NULL },\r
+ //\r
// Declare event notification on the DXE Dispatch Event Group. This event is signaled by the DXE Core\r
// each time the DXE Core dispatcher has completed its work. When this event is signalled, the SMM Core\r
// if notified, so the SMM Core can dispatch SMM drivers.\r
//\r
gSmmCorePrivate->InSmm = OldInSmm;\r
\r
- return (Status == EFI_WARN_INTERRUPT_SOURCE_QUIESCED) ? EFI_SUCCESS : EFI_NOT_FOUND;\r
+ return (Status == EFI_SUCCESS) ? EFI_SUCCESS : EFI_NOT_FOUND;\r
}\r
\r
/**\r
\r
/**\r
Event notification that is fired every time a DxeSmmReadyToLock protocol is added\r
- or if gEfiEventReadyToBootGuid is signalled.\r
+ or if gEfiEventReadyToBootGuid is signaled.\r
\r
@param Event The Event that is being processed, not used.\r
@param Context Event Context, not used.\r
} else {\r
//\r
// If SMM is not locked yet and we got here from gEfiEventReadyToBootGuid being \r
- // signalled, then gEfiDxeSmmReadyToLockProtocolGuid was not installed as expected.\r
+ // signaled, then gEfiDxeSmmReadyToLockProtocolGuid was not installed as expected.\r
// Print a warning on debug builds.\r
//\r
DEBUG ((DEBUG_WARN, "SMM IPL! DXE SMM Ready To Lock Protocol not installed before Ready To Boot signal\n"));\r
// Allocate memory for the image being loaded from the EFI_SRAM_DESCRIPTOR \r
// specified by SmramRange\r
//\r
- PageCount = (UINTN)EFI_SIZE_TO_PAGES(ImageContext.ImageSize + ImageContext.SectionAlignment);\r
+ PageCount = (UINTN)EFI_SIZE_TO_PAGES((UINTN)ImageContext.ImageSize + ImageContext.SectionAlignment);\r
\r
ASSERT ((SmramRange->PhysicalSize & EFI_PAGE_MASK) == 0);\r
ASSERT (SmramRange->PhysicalSize > EFI_PAGES_TO_SIZE (PageCount));\r
// Allocate memory for the image being loaded from the EFI_SRAM_DESCRIPTOR \r
// specified by SmramRange\r
//\r
- PageCount = (UINTN)EFI_SIZE_TO_PAGES(ImageContext.ImageSize + ImageContext.SectionAlignment);\r
+ PageCount = (UINTN)EFI_SIZE_TO_PAGES((UINTN)ImageContext.ImageSize + ImageContext.SectionAlignment);\r
\r
ASSERT ((SmramRange->PhysicalSize & EFI_PAGE_MASK) == 0);\r
ASSERT (SmramRange->PhysicalSize > EFI_PAGES_TO_SIZE (PageCount));\r
}\r
\r
ImageContext.ImageAddress += ImageContext.SectionAlignment - 1;\r
- ImageContext.ImageAddress &= ~(ImageContext.SectionAlignment - 1);\r
+ ImageContext.ImageAddress &= ~((EFI_PHYSICAL_ADDRESS)(ImageContext.SectionAlignment - 1));\r
\r
//\r
// Print debug message showing SMM Core load address.\r
//\r
DEBUG ((DEBUG_INFO, "SMM IPL calling SMM Core at SMRAM address %p\n", (VOID *)(UINTN)ImageContext.EntryPoint));\r
\r
+ gSmmCorePrivate->PiSmmCoreImageBase = ImageContext.ImageAddress;\r
+ gSmmCorePrivate->PiSmmCoreImageSize = ImageContext.ImageSize;\r
+ DEBUG ((DEBUG_INFO, "PiSmmCoreImageBase - 0x%016lx\n", gSmmCorePrivate->PiSmmCoreImageBase));\r
+ DEBUG ((DEBUG_INFO, "PiSmmCoreImageSize - 0x%016lx\n", gSmmCorePrivate->PiSmmCoreImageSize));\r
+\r
+ gSmmCorePrivate->PiSmmCoreEntryPoint = ImageContext.EntryPoint;\r
+\r
//\r
// Execute image\r
//\r
UINT64 SmmCodeSize;\r
EFI_LOAD_FIXED_ADDRESS_CONFIGURATION_TABLE *LMFAConfigurationTable;\r
EFI_CPU_ARCH_PROTOCOL *CpuArch;\r
+ EFI_STATUS SetAttrStatus;\r
\r
//\r
// Fill in the image handle of the SMM IPL so the SMM Core can use this as the \r
\r
gSmmCorePrivate->SmramRangeCount = Size / sizeof (EFI_SMRAM_DESCRIPTOR);\r
\r
+ //\r
+ // Save a full copy\r
+ //\r
+ gSmmCorePrivate->FullSmramRangeCount = gSmmCorePrivate->SmramRangeCount;\r
+ gSmmCorePrivate->FullSmramRanges = (EFI_SMRAM_DESCRIPTOR *) AllocatePool (Size);\r
+ ASSERT (gSmmCorePrivate->FullSmramRanges != NULL);\r
+ CopyMem (gSmmCorePrivate->FullSmramRanges, gSmmCorePrivate->SmramRanges, Size);\r
+\r
//\r
// Open all SMRAM ranges\r
//\r
// Attempt to reset SMRAM cacheability to UC\r
//\r
if (CpuArch != NULL) {\r
- Status = gDS->SetMemorySpaceAttributes(\r
- mSmramCacheBase, \r
- mSmramCacheSize,\r
- EFI_MEMORY_UC\r
- );\r
- if (EFI_ERROR (Status)) {\r
+ SetAttrStatus = gDS->SetMemorySpaceAttributes(\r
+ mSmramCacheBase, \r
+ mSmramCacheSize,\r
+ EFI_MEMORY_UC\r
+ );\r
+ if (EFI_ERROR (SetAttrStatus)) {\r
DEBUG ((DEBUG_WARN, "SMM IPL failed to reset SMRAM window to EFI_MEMORY_UC\n"));\r
} \r
}\r
// Free all allocated resources\r
//\r
FreePool (gSmmCorePrivate->SmramRanges);\r
- \r
+ FreePool (gSmmCorePrivate->FullSmramRanges);\r
+\r
return EFI_UNSUPPORTED;\r
}\r
\r