the platform specific information about the PCI Host Bridge.\r
\r
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials are\r
- licensed and made available under the terms and conditions of\r
- the BSD License which accompanies this distribution. The full\r
- text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
+\r
#ifndef __PCI_HOST_BRIDGE_LIB_H__\r
#define __PCI_HOST_BRIDGE_LIB_H__\r
\r
// (Base > Limit) indicates an aperture is not available.\r
//\r
typedef struct {\r
- UINT64 Base;\r
- UINT64 Limit;\r
+ //\r
+ // Base and Limit are the device address instead of host address when\r
+ // Translation is not zero\r
+ //\r
+ UINT64 Base;\r
+ UINT64 Limit;\r
+ //\r
+ // According to UEFI 2.7, Device Address = Host Address + Translation,\r
+ // so Translation = Device Address - Host Address.\r
+ // On platforms where Translation is not zero, the subtraction is probably to\r
+ // be performed with UINT64 wrap-around semantics, for we may translate an\r
+ // above-4G host address into a below-4G device address for legacy PCIe device\r
+ // compatibility.\r
+ //\r
+ // NOTE: The alignment of Translation is required to be larger than any BAR\r
+ // alignment in the same root bridge, so that the same alignment can be\r
+ // applied to both device address and host address, which simplifies the\r
+ // situation and makes the current resource allocation code in generic PCI\r
+ // host bridge driver still work.\r
+ //\r
+ UINT64 Translation;\r
} PCI_ROOT_BRIDGE_APERTURE;\r
\r
typedef struct {\r
- UINT32 Segment; ///< Segment number.\r
- UINT64 Supports; ///< Supported attributes.\r
- ///< Refer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()\r
- ///< and SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- UINT64 Attributes; ///< Initial attributes.\r
- ///< Refer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()\r
- ///< and SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- BOOLEAN DmaAbove4G; ///< DMA above 4GB memory.\r
- ///< Set to TRUE when root bridge supports DMA above 4GB memory.\r
- BOOLEAN NoExtendedConfigSpace; ///< When FALSE, the root bridge supports\r
- ///< Extended (4096-byte) Configuration Space.\r
- ///< When TRUE, the root bridge supports\r
- ///< 256-byte Configuration Space only.\r
- UINT64 AllocationAttributes; ///< Allocation attributes.\r
- ///< Refer to EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM and\r
- ///< EFI_PCI_HOST_BRIDGE_MEM64_DECODE used by GetAllocAttributes()\r
- ///< in EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
- PCI_ROOT_BRIDGE_APERTURE Bus; ///< Bus aperture which can be used by the root bridge.\r
- PCI_ROOT_BRIDGE_APERTURE Io; ///< IO aperture which can be used by the root bridge.\r
- PCI_ROOT_BRIDGE_APERTURE Mem; ///< MMIO aperture below 4GB which can be used by the root bridge.\r
- PCI_ROOT_BRIDGE_APERTURE MemAbove4G; ///< MMIO aperture above 4GB which can be used by the root bridge.\r
- PCI_ROOT_BRIDGE_APERTURE PMem; ///< Prefetchable MMIO aperture below 4GB which can be used by the root bridge.\r
- PCI_ROOT_BRIDGE_APERTURE PMemAbove4G; ///< Prefetchable MMIO aperture above 4GB which can be used by the root bridge.\r
- EFI_DEVICE_PATH_PROTOCOL *DevicePath; ///< Device path.\r
+ UINT32 Segment; ///< Segment number.\r
+ UINT64 Supports; ///< Supported attributes.\r
+ ///< Refer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()\r
+ ///< and SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ UINT64 Attributes; ///< Initial attributes.\r
+ ///< Refer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()\r
+ ///< and SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ BOOLEAN DmaAbove4G; ///< DMA above 4GB memory.\r
+ ///< Set to TRUE when root bridge supports DMA above 4GB memory.\r
+ BOOLEAN NoExtendedConfigSpace; ///< When FALSE, the root bridge supports\r
+ ///< Extended (4096-byte) Configuration Space.\r
+ ///< When TRUE, the root bridge supports\r
+ ///< 256-byte Configuration Space only.\r
+ BOOLEAN ResourceAssigned; ///< Resource assignment status of the root bridge.\r
+ ///< Set to TRUE if Bus/IO/MMIO resources for root bridge have been assigned.\r
+ UINT64 AllocationAttributes; ///< Allocation attributes.\r
+ ///< Refer to EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM and\r
+ ///< EFI_PCI_HOST_BRIDGE_MEM64_DECODE used by GetAllocAttributes()\r
+ ///< in EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
+ PCI_ROOT_BRIDGE_APERTURE Bus; ///< Bus aperture which can be used by the root bridge.\r
+ PCI_ROOT_BRIDGE_APERTURE Io; ///< IO aperture which can be used by the root bridge.\r
+ PCI_ROOT_BRIDGE_APERTURE Mem; ///< MMIO aperture below 4GB which can be used by the root bridge.\r
+ PCI_ROOT_BRIDGE_APERTURE MemAbove4G; ///< MMIO aperture above 4GB which can be used by the root bridge.\r
+ PCI_ROOT_BRIDGE_APERTURE PMem; ///< Prefetchable MMIO aperture below 4GB which can be used by the root bridge.\r
+ PCI_ROOT_BRIDGE_APERTURE PMemAbove4G; ///< Prefetchable MMIO aperture above 4GB which can be used by the root bridge.\r
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath; ///< Device path.\r
} PCI_ROOT_BRIDGE;\r
\r
/**\r
PCI_ROOT_BRIDGE *\r
EFIAPI\r
PciHostBridgeGetRootBridges (\r
- UINTN *Count\r
+ UINTN *Count\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
PciHostBridgeFreeRootBridges (\r
- PCI_ROOT_BRIDGE *Bridges,\r
- UINTN Count\r
+ PCI_ROOT_BRIDGE *Bridges,\r
+ UINTN Count\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
PciHostBridgeResourceConflict (\r
- EFI_HANDLE HostBridgeHandle,\r
- VOID *Configuration\r
+ EFI_HANDLE HostBridgeHandle,\r
+ VOID *Configuration\r
);\r
\r
#endif\r
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