/// This is designed for old generation chipset with PATA/SATA controllers.\r
/// It may be ignored in PPI implementation for new generation chipset without PATA controller.\r
///\r
-#define PEI_ICH_IDE_NONE 0x00\r
+#define PEI_ICH_IDE_NONE 0x00\r
\r
///\r
/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to\r
/// This is designed for old generation chipset with PATA/SATA controllers.\r
/// It may be ignored in PPI implementation for new generation chipset without PATA controller.\r
///\r
-#define PEI_ICH_IDE_PRIMARY 0x01\r
+#define PEI_ICH_IDE_PRIMARY 0x01\r
\r
///\r
/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to\r
/// This is designed for old generation chipset with PATA/SATA controllers.\r
/// It may be ignored in PPI implementation for new generation chipset without PATA controller.\r
///\r
-#define PEI_ICH_IDE_SECONDARY 0x02\r
+#define PEI_ICH_IDE_SECONDARY 0x02\r
\r
///\r
/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to\r
/// This is designed for old generation chipset with PATA/SATA controllers.\r
/// It may be ignored in PPI implementation for new generation chipset without PATA controller.\r
///\r
-#define PEI_ICH_SATA_NONE 0x04\r
+#define PEI_ICH_SATA_NONE 0x04\r
\r
///\r
/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to\r
/// This is designed for old generation chipset with PATA/SATA controllers.\r
/// It may be ignored in PPI implementation for new generation chipset without PATA controller.\r
///\r
-#define PEI_ICH_SATA_PRIMARY 0x08\r
+#define PEI_ICH_SATA_PRIMARY 0x08\r
\r
///\r
/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to\r
///\r
/// Base I/O port address of the IDE controller's command block\r
///\r
- UINT16 CommandBlockBaseAddr;\r
+ UINT16 CommandBlockBaseAddr;\r
///\r
/// Base I/O port address of the IDE controller's control block\r
///\r
- UINT16 ControlBlockBaseAddr;\r
+ UINT16 ControlBlockBaseAddr;\r
} IDE_REGS_BASE_ADDR;\r
\r
/**\r
/// retrieves the base I/O port addresses to the enabled IDE and SATA channels.\r
///\r
struct _PEI_ATA_CONTROLLER_PPI {\r
- PEI_ENABLE_ATA EnableAtaChannel;\r
- GET_IDE_REGS_BASE_ADDR GetIdeRegsBaseAddr;\r
+ PEI_ENABLE_ATA EnableAtaChannel;\r
+ GET_IDE_REGS_BASE_ADDR GetIdeRegsBaseAddr;\r
};\r
\r
-extern EFI_GUID gPeiAtaControllerPpiGuid;\r
+extern EFI_GUID gPeiAtaControllerPpiGuid;\r
\r
#endif\r
-\r
-\r