\r
Set a IDT entry for interrupt vector 3 for debug purpose for x64 platform\r
\r
-Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
+\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
//\r
// Cut the previous uplink if it exists and wasn't overwritten.\r
//\r
- if ((mPageFaultUplink[mPageFaultIndex] != NULL) && ((*mPageFaultUplink[mPageFaultIndex] & mPhyMask) == Address)) {\r
+ if ((mPageFaultUplink[mPageFaultIndex] != NULL) &&\r
+ ((*mPageFaultUplink[mPageFaultIndex] & ~mAddressEncMask & mPhyMask) == Address)) {\r
*mPageFaultUplink[mPageFaultIndex] = 0;\r
}\r
\r
//\r
// Link & Record the current uplink.\r
//\r
- *Uplink = Address | IA32_PG_P | IA32_PG_RW;\r
+ *Uplink = Address | mAddressEncMask | IA32_PG_P | IA32_PG_RW;\r
mPageFaultUplink[mPageFaultIndex] = Uplink;\r
\r
mPageFaultIndex = (mPageFaultIndex + 1) % EXTRA_PAGE_TABLE_PAGES;\r
\r
/**\r
The page fault handler that on-demand read >4G memory/MMIO.\r
- \r
+\r
@retval TRUE The page fault is correctly handled.\r
@retval FALSE The page fault is not handled and is passed through to original handler.\r
\r
UINTN PTIndex;\r
\r
PFAddress = AsmReadCr2 ();\r
- DEBUG ((EFI_D_ERROR, "BootScript - PageFaultHandler: Cr2 - %lx\n", PFAddress));\r
+ DEBUG ((DEBUG_INFO, "BootScript - PageFaultHandler: Cr2 - %lx\n", PFAddress));\r
\r
if (PFAddress >= mPhyMask + SIZE_4KB) {\r
return FALSE;\r
if ((PageTable[PTIndex] & IA32_PG_P) == 0) {\r
AcquirePage (&PageTable[PTIndex]);\r
}\r
- PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & mPhyMask);\r
+ PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & mPhyMask);\r
PTIndex = BitFieldRead64 (PFAddress, 30, 38);\r
// PDPTE\r
if (mPage1GSupport) {\r
- PageTable[PTIndex] = (PFAddress & ~((1ull << 30) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;\r
+ PageTable[PTIndex] = ((PFAddress | mAddressEncMask) & ~((1ull << 30) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;\r
} else {\r
if ((PageTable[PTIndex] & IA32_PG_P) == 0) {\r
AcquirePage (&PageTable[PTIndex]);\r
}\r
- PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & mPhyMask);\r
+ PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & mPhyMask);\r
PTIndex = BitFieldRead64 (PFAddress, 21, 29);\r
// PD\r
- PageTable[PTIndex] = (PFAddress & ~((1ull << 21) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;\r
+ PageTable[PTIndex] = ((PFAddress | mAddressEncMask) & ~((1ull << 21) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;\r
}\r
\r
return TRUE;\r