/** @file\r
The X64 entrypoint is used to process capsule in long mode.\r
\r
-Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
//\r
// Get the IDT Descriptor.\r
//\r
- AsmReadIdtr ((IA32_DESCRIPTOR *) &Idtr); \r
+ AsmReadIdtr ((IA32_DESCRIPTOR *) &Idtr);\r
//\r
// Then get page fault context by IDT Descriptor.\r
//\r
//\r
// Save the IA32 IDT Descriptor\r
//\r
- AsmReadIdtr ((IA32_DESCRIPTOR *) &Ia32Idtr); \r
+ AsmReadIdtr ((IA32_DESCRIPTOR *) &Ia32Idtr);\r
\r
//\r
// Setup X64 IDT table\r
ZeroMem (PageFaultIdtTable.IdtEntryTable, sizeof (IA32_IDT_GATE_DESCRIPTOR) * EXCEPTION_VECTOR_NUMBER);\r
X64Idtr.Base = (UINTN) PageFaultIdtTable.IdtEntryTable;\r
X64Idtr.Limit = (UINT16) (sizeof (IA32_IDT_GATE_DESCRIPTOR) * EXCEPTION_VECTOR_NUMBER - 1);\r
- AsmWriteIdtr ((IA32_DESCRIPTOR *) &X64Idtr); \r
+ AsmWriteIdtr ((IA32_DESCRIPTOR *) &X64Idtr);\r
\r
//\r
// Setup the default CPU exception handlers\r
(VOID **) (UINTN) EntrypointContext->MemoryBase64Ptr,\r
(UINTN *) (UINTN) EntrypointContext->MemorySize64Ptr\r
);\r
- \r
+\r
ReturnContext->ReturnStatus = Status;\r
\r
DEBUG ((\r
//\r
// Restore IA32 IDT table\r
//\r
- AsmWriteIdtr ((IA32_DESCRIPTOR *) &Ia32Idtr); \r
- \r
+ AsmWriteIdtr ((IA32_DESCRIPTOR *) &Ia32Idtr);\r
+\r
//\r
// Finish to coalesce capsule, and return to 32-bit mode.\r
//\r
(UINT32) (UINTN) EntrypointContext,\r
(UINT32) (UINTN) ReturnContext,\r
(UINT32) (EntrypointContext->StackBufferBase + EntrypointContext->StackBufferLength)\r
- ); \r
- \r
+ );\r
+\r
//\r
// Should never be here.\r
//\r