/** @file \r
- ACPI 2.0 definitions from the ACPI Specification, revision 2.0\r
+ ACPI 2.0 definitions from the ACPI Specification, revision 2.0\r
\r
- Copyright (c) 2006 - 2008, Intel Corporation\r
- All rights reserved. This program and the accompanying materials \r
+ Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials \r
are licensed and made available under the terms and conditions of the BSD License \r
which accompanies this distribution. The full text of the license may be found at \r
http://opensource.org/licenses/bsd-license.php \r
\r
#include <IndustryStandard/Acpi10.h>\r
\r
+//\r
+// Define for Desriptor\r
+//\r
+#define ACPI_LARGE_GENERIC_REGISTER_DESCRIPTOR_NAME 0x02\r
+\r
+#define ACPI_GENERIC_REGISTER_DESCRIPTOR 0x82\r
+\r
+//\r
+// Ensure proper structure formats\r
+//\r
+#pragma pack(1)\r
+\r
+///\r
+/// Generic Register Descriptor\r
+///\r
+typedef PACKED struct {\r
+ ACPI_LARGE_RESOURCE_HEADER Header;\r
+ UINT8 AddressSpaceId;\r
+ UINT8 RegisterBitWidth;\r
+ UINT8 RegisterBitOffset;\r
+ UINT8 AddressSize;\r
+ UINT64 RegisterAddress;\r
+} EFI_ACPI_GENERIC_REGISTER_DESCRIPTOR;\r
+\r
+#pragma pack()\r
+\r
//\r
// Ensure proper structure formats\r
//\r
///\r
#define EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x03\r
\r
-///\r
-/// Fixed ACPI Description Table Boot Architecture Flags\r
-/// All other bits are reserved and must be set to 0.\r
-///\r
-#define EFI_ACPI_2_0_LEGACY_DEVICES (1 << 0)\r
-#define EFI_ACPI_2_0_8042 (1 << 1)\r
+//\r
+// Fixed ACPI Description Table Preferred Power Management Profile\r
+//\r
+#define EFI_ACPI_2_0_PM_PROFILE_UNSPECIFIED 0\r
+#define EFI_ACPI_2_0_PM_PROFILE_DESKTOP 1\r
+#define EFI_ACPI_2_0_PM_PROFILE_MOBILE 2\r
+#define EFI_ACPI_2_0_PM_PROFILE_WORKSTATION 3\r
+#define EFI_ACPI_2_0_PM_PROFILE_ENTERPRISE_SERVER 4\r
+#define EFI_ACPI_2_0_PM_PROFILE_SOHO_SERVER 5\r
+#define EFI_ACPI_2_0_PM_PROFILE_APPLIANCE_PC 6\r
+\r
+//\r
+// Fixed ACPI Description Table Boot Architecture Flags\r
+// All other bits are reserved and must be set to 0.\r
+//\r
+#define EFI_ACPI_2_0_LEGACY_DEVICES BIT0\r
+#define EFI_ACPI_2_0_8042 BIT1\r
\r
//\r
// Fixed ACPI Description Table Fixed Feature Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_2_0_WBINVD (1 << 0)\r
-#define EFI_ACPI_2_0_WBINVD_FLUSH (1 << 1)\r
-#define EFI_ACPI_2_0_PROC_C1 (1 << 2)\r
-#define EFI_ACPI_2_0_P_LVL2_UP (1 << 3)\r
-#define EFI_ACPI_2_0_PWR_BUTTON (1 << 4)\r
-#define EFI_ACPI_2_0_SLP_BUTTON (1 << 5)\r
-#define EFI_ACPI_2_0_FIX_RTC (1 << 6)\r
-#define EFI_ACPI_2_0_RTC_S4 (1 << 7)\r
-#define EFI_ACPI_2_0_TMR_VAL_EXT (1 << 8)\r
-#define EFI_ACPI_2_0_DCK_CAP (1 << 9)\r
-#define EFI_ACPI_2_0_RESET_REG_SUP (1 << 10)\r
-#define EFI_ACPI_2_0_SEALED_CASE (1 << 11)\r
-#define EFI_ACPI_2_0_HEADLESS (1 << 12)\r
-#define EFI_ACPI_2_0_CPU_SW_SLP (1 << 13)\r
+#define EFI_ACPI_2_0_WBINVD BIT0\r
+#define EFI_ACPI_2_0_WBINVD_FLUSH BIT1\r
+#define EFI_ACPI_2_0_PROC_C1 BIT2\r
+#define EFI_ACPI_2_0_P_LVL2_UP BIT3\r
+#define EFI_ACPI_2_0_PWR_BUTTON BIT4\r
+#define EFI_ACPI_2_0_SLP_BUTTON BIT5\r
+#define EFI_ACPI_2_0_FIX_RTC BIT6\r
+#define EFI_ACPI_2_0_RTC_S4 BIT7\r
+#define EFI_ACPI_2_0_TMR_VAL_EXT BIT8\r
+#define EFI_ACPI_2_0_DCK_CAP BIT9\r
+#define EFI_ACPI_2_0_RESET_REG_SUP BIT10\r
+#define EFI_ACPI_2_0_SEALED_CASE BIT11\r
+#define EFI_ACPI_2_0_HEADLESS BIT12\r
+#define EFI_ACPI_2_0_CPU_SW_SLP BIT13\r
\r
///\r
/// Firmware ACPI Control Structure\r
/// Firmware Control Structure Feature Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_2_0_S4BIOS_F (1 << 0)\r
+#define EFI_ACPI_2_0_S4BIOS_F BIT0\r
\r
///\r
/// Multiple APIC Description Table header definition. The rest of the table\r
/// Multiple APIC Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_2_0_PCAT_COMPAT (1 << 0)\r
+#define EFI_ACPI_2_0_PCAT_COMPAT BIT0\r
\r
//\r
// Multiple APIC Description Table APIC structure types\r
///\r
/// Local APIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_2_0_LOCAL_APIC_ENABLED (1 << 0)\r
+#define EFI_ACPI_2_0_LOCAL_APIC_ENABLED BIT0\r
\r
///\r
/// IO APIC Structure\r
/// BUGBUG: Don't know where this came from except SR870BN4 uses it.\r
/// #define EFI_ACPI_2_0_MULTIPLE_SAPIC_DESCRIPTION_TABLE_SIGNATURE 0x43495053\r
///\r
-#define EFI_ACPI_2_0_MULTIPLE_SAPIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'I', 'C')\r
+#define EFI_ACPI_2_0_MULTIPLE_SAPIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')\r
\r
///\r
/// "BOOT" MS Simple Boot Spec\r
#define EFI_ACPI_2_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T')\r
\r
///\r
-/// "MCFG" Static Resource Affinity Table\r
+/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table\r
///\r
#define EFI_ACPI_2_0_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')\r
\r