#define PAL_CACHE_PROT_INFO 38\r
\r
typedef struct {\r
- UINT64 ThreadId : 16; /// The thread identifier of the logical\r
- /// processor for which information is being\r
- /// returned. This value will be unique on a per core basis.\r
+ UINT64 ThreadId : 16; ///< The thread identifier of the logical\r
+ ///< processor for which information is being\r
+ ///< returned. This value will be unique on a per core basis.\r
UINT64 Reserved1: 16;\r
- UINT64 CoreId: 16; /// The core identifier of the logical processor\r
- /// for which information is being returned.\r
- /// This value will be unique on a per physical\r
- /// processor package basis.\r
+ UINT64 CoreId: 16; ///< The core identifier of the logical processor\r
+ ///< for which information is being returned.\r
+ ///< This value will be unique on a per physical\r
+ ///< processor package basis.\r
UINT64 Reserved2: 16;\r
} PAL_PCOC_N_CACHE_INFO1;\r
\r
\r
typedef struct {\r
- UINT64 LogicalAddress : 16; /// Logical address: geographical address\r
- /// of the logical processor for which\r
- /// information is being returned. This is\r
- /// the same value that is returned by the\r
- /// PAL_FIXED_ADDR procedure when it is\r
- /// called on the logical processor.\r
+ UINT64 LogicalAddress : 16; ///< Logical address: geographical address\r
+ ///< of the logical processor for which\r
+ ///< information is being returned. This is\r
+ ///< the same value that is returned by the\r
+ ///< PAL_FIXED_ADDR procedure when it is\r
+ ///< called on the logical processor.\r
UINT64 Reserved1: 16;\r
UINT64 Reserved2: 32;\r
} PAL_PCOC_N_CACHE_INFO2;\r
#define PAL_PTCE_INFO 6\r
\r
typedef struct {\r
- UINT64 NumberSets:8; /// Unsigned 8-bit integer denoting the number\r
- /// of hash sets for the specified level\r
- /// (1=fully associative)\r
- UINT64 NumberWays:8; /// Unsigned 8-bit integer denoting the\r
- /// associativity of the specified level\r
- /// (1=direct).\r
- UINT64 NumberEntries:16; /// Unsigned 16-bit integer denoting the\r
- /// number of entries in the specified TC.\r
- UINT64 PageSizeIsOptimized:1; /// Flag denoting whether the\r
- /// specified level is optimized for\r
- /// the region's preferred page size\r
- /// (1=optimized) tc_pages indicates\r
- /// which page sizes are usable by\r
- /// this translation cache.\r
- UINT64 TcIsUnified:1; /// Flag denoting whether the specified TC is\r
- /// unified (1=unified).\r
- UINT64 EntriesReduction:1; /// Flag denoting whether installed\r
- /// translation registers will reduce\r
- /// the number of entries within the\r
- /// specified TC.\r
+ UINT64 NumberSets:8; ///< Unsigned 8-bit integer denoting the number\r
+ ///< of hash sets for the specified level\r
+ ///< (1=fully associative)\r
+ UINT64 NumberWays:8; ///< Unsigned 8-bit integer denoting the\r
+ ///< associativity of the specified level\r
+ ///< (1=direct).\r
+ UINT64 NumberEntries:16; ///< Unsigned 16-bit integer denoting the\r
+ ///< number of entries in the specified TC.\r
+ UINT64 PageSizeIsOptimized:1; ///< Flag denoting whether the\r
+ ///< specified level is optimized for\r
+ ///< the region's preferred page size\r
+ ///< (1=optimized) tc_pages indicates\r
+ ///< which page sizes are usable by\r
+ ///< this translation cache.\r
+ UINT64 TcIsUnified:1; ///< Flag denoting whether the specified TC is\r
+ ///< unified (1=unified).\r
+ UINT64 EntriesReduction:1; ///< Flag denoting whether installed\r
+ ///< translation registers will reduce\r
+ ///< the number of entries within the\r
+ ///< specified TC.\r
} PAL_TC_INFO;\r
\r
/**\r
#define PAL_VM_PAGE_SIZE 34\r
\r
typedef struct {\r
- UINT64 WalkerPresent:1; /// 1-bit flag indicating whether a hardware\r
- /// TLB walker is implemented (1 = walker\r
- /// present).\r
- UINT64 WidthOfPhysicalAddress: 7; /// Unsigned 7-bit integer\r
- /// denoting the number of bits of\r
- /// physical address implemented.\r
- UINT64 WidthOfKey:8; /// Unsigned 8-bit integer denoting the number\r
- /// of bits mplemented in the PKR.key field.\r
- UINT64 MaxPkrIndex:8; /// Unsigned 8-bit integer denoting the\r
- /// maximum PKR index (number of PKRs-1).\r
- UINT64 HashTagId:8; /// Unsigned 8-bit integer which uniquely\r
- /// identifies the processor hash and tag\r
- /// algorithm.\r
- UINT64 MaxDtrIndex:8; /// Unsigned 8 bit integer denoting the\r
- /// maximum data translation register index\r
- /// (number of dtr entries - 1).\r
- UINT64 MaxItrIndex:8; /// Unsigned 8 bit integer denoting the\r
- /// maximum instruction translation register\r
- /// index (number of itr entries - 1).\r
- UINT64 NumberOfUniqueTc:8; /// Unsigned 8-bit integer denoting the\r
- /// number of unique TCs implemented.\r
- /// This is a maximum of\r
- /// 2*num_tc_levels.\r
- UINT64 NumberOfTcLevels:8; /// Unsigned 8-bit integer denoting the\r
- /// number of TC levels.\r
+ UINT64 WalkerPresent:1; ///< 1-bit flag indicating whether a hardware\r
+ ///< TLB walker is implemented (1 = walker\r
+ ///< present).\r
+ UINT64 WidthOfPhysicalAddress: 7; ///< Unsigned 7-bit integer\r
+ ///< denoting the number of bits of\r
+ ///< physical address implemented.\r
+ UINT64 WidthOfKey:8; ///< Unsigned 8-bit integer denoting the number\r
+ ///< of bits mplemented in the PKR.key field.\r
+ UINT64 MaxPkrIndex:8; ///< Unsigned 8-bit integer denoting the\r
+ ///< maximum PKR index (number of PKRs-1).\r
+ UINT64 HashTagId:8; ///< Unsigned 8-bit integer which uniquely\r
+ ///< identifies the processor hash and tag\r
+ ///< algorithm.\r
+ UINT64 MaxDtrIndex:8; ///< Unsigned 8 bit integer denoting the\r
+ ///< maximum data translation register index\r
+ ///< (number of dtr entries - 1).\r
+ UINT64 MaxItrIndex:8; ///< Unsigned 8 bit integer denoting the\r
+ ///< maximum instruction translation register\r
+ ///< index (number of itr entries - 1).\r
+ UINT64 NumberOfUniqueTc:8; ///< Unsigned 8-bit integer denoting the\r
+ ///< number of unique TCs implemented.\r
+ ///< This is a maximum of\r
+ ///< 2*num_tc_levels.\r
+ UINT64 NumberOfTcLevels:8; ///< Unsigned 8-bit integer denoting the\r
+ ///< number of TC levels.\r
} PAL_VM_INFO1;\r
\r
typedef struct {\r
- UINT64 WidthOfVirtualAddress:8; /// Unsigned 8-bit integer denoting\r
- /// is the total number of virtual\r
- /// address bits - 1.\r
- UINT64 WidthOfRid:8; /// Unsigned 8-bit integer denoting the number\r
- /// of bits implemented in the RR.rid field.\r
- UINT64 MaxPurgedTlbs:16; /// Unsigned 16 bit integer denoting the\r
- /// maximum number of concurrent outstanding\r
- /// TLB purges allowed by the processor. A\r
- /// value of 0 indicates one outstanding\r
- /// purge allowed. A value of 216-1\r
- /// indicates no limit on outstanding\r
- /// purges. All other values indicate the\r
- /// actual number of concurrent outstanding\r
- /// purges allowed.\r
+ UINT64 WidthOfVirtualAddress:8; ///< Unsigned 8-bit integer denoting\r
+ ///< is the total number of virtual\r
+ ///< address bits - 1.\r
+ UINT64 WidthOfRid:8; ///< Unsigned 8-bit integer denoting the number\r
+ ///< of bits implemented in the RR.rid field.\r
+ UINT64 MaxPurgedTlbs:16; ///< Unsigned 16 bit integer denoting the\r
+ ///< maximum number of concurrent outstanding\r
+ ///< TLB purges allowed by the processor. A\r
+ ///< value of 0 indicates one outstanding\r
+ ///< purge allowed. A value of 216-1\r
+ ///< indicates no limit on outstanding\r
+ ///< purges. All other values indicate the\r
+ ///< actual number of concurrent outstanding\r
+ ///< purges allowed.\r
UINT64 Reserved:32;\r
} PAL_VM_INFO2;\r
\r
#define PAL_FREQ_RATIOS 14\r
\r
typedef struct {\r
- UINT64 NumberOfLogicalProcessors:16; /// Total number of logical\r
- /// processors on this physical\r
- /// processor package that are\r
- /// enabled.\r
- UINT64 ThreadsPerCore:8; /// Number of threads per core.\r
+ UINT64 NumberOfLogicalProcessors:16; ///< Total number of logical\r
+ ///< processors on this physical\r
+ ///< processor package that are\r
+ ///< enabled.\r
+ UINT64 ThreadsPerCore:8; ///< Number of threads per core.\r
UINT64 Reserved1:8;\r
- UINT64 CoresPerProcessor; /// Total number of cores on this\r
- /// physical processor package.\r
+ UINT64 CoresPerProcessor; ///< Total number of cores on this\r
+ ///< physical processor package.\r
UINT64 Reserved2:8;\r
- UINT64 PhysicalProcessorPackageId:8; /// Physical processor package\r
- /// identifier which was\r
- /// assigned at reset by the\r
- /// platform or bus\r
- /// controller. This value may\r
- /// or may not be unique\r
- /// across the entire platform\r
- /// since it depends on the\r
- /// platform vendor's policy.\r
+ UINT64 PhysicalProcessorPackageId:8; ///< Physical processor package\r
+ ///< identifier which was\r
+ ///< assigned at reset by the\r
+ ///< platform or bus\r
+ ///< controller. This value may\r
+ ///< or may not be unique\r
+ ///< across the entire platform\r
+ ///< since it depends on the\r
+ ///< platform vendor's policy.\r
UINT64 Reserved3:8;\r
} PAL_LOGICAL_PROCESSPR_OVERVIEW;\r
\r
typedef struct {\r
- UINT64 ThreadId:16; /// The thread identifier of the logical\r
- /// processor for which information is being\r
- /// returned. This value will be unique on a per\r
- /// core basis.\r
+ UINT64 ThreadId:16; ///< The thread identifier of the logical\r
+ ///< processor for which information is being\r
+ ///< returned. This value will be unique on a per\r
+ ///< core basis.\r
UINT64 Reserved1:16;\r
- UINT64 CoreId:16; /// The core identifier of the logical processor\r
- /// for which information is being returned.\r
- /// This value will be unique on a per physical\r
- /// processor package basis.\r
+ UINT64 CoreId:16; ///< The core identifier of the logical processor\r
+ ///< for which information is being returned.\r
+ ///< This value will be unique on a per physical\r
+ ///< processor package basis.\r
UINT64 Reserved2:16;\r
} PAL_LOGICAL_PROCESSORN_INFO1;\r
\r
typedef struct {\r
- UINT64 LogicalAddress:16; /// Geographical address of the logical\r
- /// processor for which information is being\r
- /// returned. This is the same value that is\r
- /// returned by the PAL_FIXED_ADDR procedure\r
- /// when it is called on the logical processor.\r
+ UINT64 LogicalAddress:16; ///< Geographical address of the logical\r
+ ///< processor for which information is being\r
+ ///< returned. This is the same value that is\r
+ ///< returned by the PAL_FIXED_ADDR procedure\r
+ ///< when it is called on the logical processor.\r
UINT64 Reserved:48;\r
} PAL_LOGICAL_PROCESSORN_INFO2;\r
\r
#define PAL_LOGICAL_TO_PHYSICAL 42\r
\r
typedef struct {\r
- UINT64 NumberOfPmcPairs:8; /// Unsigned 8-bit number defining the\r
- /// number of generic PMC/PMD pairs.\r
- UINT64 WidthOfCounter:8; /// Unsigned 8-bit number in the range\r
- /// 0:60 defining the number of\r
- /// implemented counter bits.\r
- UINT64 TypeOfCycleCounting:8; /// Unsigned 8-bit number defining the\r
- /// event type for counting processor cycles.\r
- UINT64 TypeOfRetiredInstructionBundle:8; /// Retired Unsigned 8-bit\r
- /// number defining the\r
- /// event type for retired\r
- /// instruction bundles.\r
+ UINT64 NumberOfPmcPairs:8; ///< Unsigned 8-bit number defining the\r
+ ///< number of generic PMC/PMD pairs.\r
+ UINT64 WidthOfCounter:8; ///< Unsigned 8-bit number in the range\r
+ ///< 0:60 defining the number of\r
+ ///< implemented counter bits.\r
+ UINT64 TypeOfCycleCounting:8; ///< Unsigned 8-bit number defining the\r
+ ///< event type for counting processor cycles.\r
+ UINT64 TypeOfRetiredInstructionBundle:8; ///< Retired Unsigned 8-bit\r
+ ///< number defining the\r
+ ///< event type for retired\r
+ ///< instruction bundles.\r
UINT64 Reserved:32;\r
} PAL_PERFORMANCE_INFO;\r
\r
\r
typedef struct {\r
UINT64 Reserved1:36;\r
- UINT64 FaultInUndefinedIns:1; /// Bit36, No Unimplemented\r
- /// instruction address reported as\r
- /// fault. Denotes how the processor\r
- /// reports the detection of\r
- /// unimplemented instruction\r
- /// addresses. When 1, the processor\r
- /// reports an Unimplemented\r
- /// Instruction Address fault on the\r
- /// unimplemented address; when 0, it\r
- /// reports an Unimplemented\r
- /// Instruction Address trap on the\r
- /// previous instruction in program\r
- /// order. This feature may only be\r
- /// interrogated by\r
- /// PAL_PROC_GET_FEATURES. It may not\r
- /// be enabled or disabled by\r
- /// PAL_PROC_SET_FEATURES. The\r
- /// corresponding argument is ignored.\r
+ UINT64 FaultInUndefinedIns:1; ///< Bit36, No Unimplemented\r
+ ///< instruction address reported as\r
+ ///< fault. Denotes how the processor\r
+ ///< reports the detection of\r
+ ///< unimplemented instruction\r
+ ///< addresses. When 1, the processor\r
+ ///< reports an Unimplemented\r
+ ///< Instruction Address fault on the\r
+ ///< unimplemented address; when 0, it\r
+ ///< reports an Unimplemented\r
+ ///< Instruction Address trap on the\r
+ ///< previous instruction in program\r
+ ///< order. This feature may only be\r
+ ///< interrogated by\r
+ ///< PAL_PROC_GET_FEATURES. It may not\r
+ ///< be enabled or disabled by\r
+ ///< PAL_PROC_SET_FEATURES. The\r
+ ///< corresponding argument is ignored.\r
\r
- UINT64 NoPresentPmi:1; /// Bit37, No INIT, PMI, and LINT pins\r
- /// present. Denotes the absence of INIT,\r
- /// PMI, LINT0 and LINT1 pins on the\r
- /// processor. When 1, the pins are absent.\r
- /// When 0, the pins are present. This\r
- /// feature may only be interrogated by\r
- /// PAL_PROC_GET_FEATURES. It may not be\r
- /// enabled or disabled by\r
- /// PAL_PROC_SET_FEATURES. The corresponding\r
- /// argument is ignored.\r
+ UINT64 NoPresentPmi:1; ///< Bit37, No INIT, PMI, and LINT pins\r
+ ///< present. Denotes the absence of INIT,\r
+ ///< PMI, LINT0 and LINT1 pins on the\r
+ ///< processor. When 1, the pins are absent.\r
+ ///< When 0, the pins are present. This\r
+ ///< feature may only be interrogated by\r
+ ///< PAL_PROC_GET_FEATURES. It may not be\r
+ ///< enabled or disabled by\r
+ ///< PAL_PROC_SET_FEATURES. The corresponding\r
+ ///< argument is ignored.\r
\r
- UINT64 NoSimpleImpInUndefinedIns:1; /// Bit38, No Simple\r
- /// implementation of\r
- /// unimplemented instruction\r
- /// addresses. Denotes how an\r
- /// unimplemented instruction\r
- /// address is recorded in IIP\r
- /// on an Unimplemented\r
- /// Instruction Address trap or\r
- /// fault. When 1, the full\r
- /// unimplemented address is\r
- /// recorded in IIP; when 0, the\r
- /// address is sign extended\r
- /// (virtual addresses) or zero\r
- /// extended (physical\r
- /// addresses). This feature may\r
- /// only be interrogated by\r
- /// PAL_PROC_GET_FEATURES. It\r
- /// may not be enabled or\r
- /// disabled by\r
- /// PAL_PROC_SET_FEATURES. The\r
- /// corresponding argument is\r
- /// ignored.\r
-\r
- UINT64 NoVariablePState:1; /// Bit39, No Variable P-state\r
- /// performance: A value of 1, indicates\r
- /// that a processor implements\r
- /// techniques to optimize performance\r
- /// for the given P-state power budget\r
- /// by dynamically varying the\r
- /// frequency, such that maximum\r
- /// performance is achieved for the\r
- /// power budget. A value of 0,\r
- /// indicates that P-states have no\r
- /// frequency variation or very small\r
- /// frequency variations for their given\r
- /// power budget. This feature may only\r
- /// be interrogated by\r
- /// PAL_PROC_GET_FEATURES. it may not be\r
- /// enabled or disabled by\r
- /// PAL_PROC_SET_FEATURES. The\r
- /// corresponding argument is ignored.\r
-\r
- UINT64 NoVM:1; /// Bit40, No Virtual Machine features implemented.\r
- /// Denotes whether PSR.vm is implemented. This\r
- /// feature may only be interrogated by\r
- /// PAL_PROC_GET_FEATURES. It may not be enabled or\r
- /// disabled by PAL_PROC_SET_FEATURES. The\r
- /// corresponding argument is ignored.\r
-\r
- UINT64 NoXipXpsrXfs:1; /// Bit41, No XIP, XPSR, and XFS\r
- /// implemented. Denotes whether XIP, XPSR,\r
- /// and XFS are implemented for machine\r
- /// check recovery. This feature may only be\r
- /// interrogated by PAL_PROC_GET_FEATURES.\r
- /// It may not be enabled or disabled by\r
- /// PAL_PROC_SET_FEATURES. The corresponding\r
- /// argument is ignored.\r
-\r
- UINT64 NoXr1ThroughXr3:1; /// Bit42, No XR1 through XR3 implemented.\r
- /// Denotes whether XR1 XR3 are\r
- /// implemented for machine check\r
- /// recovery. This feature may only be\r
- /// interrogated by PAL_PROC_GET_FEATURES.\r
- /// It may not be enabled or disabled by\r
- /// PAL_PROC_SET_FEATURES. The\r
- /// corresponding argument is ignored.\r
-\r
- UINT64 DisableDynamicPrediction:1; /// Bit43, Disable Dynamic\r
- /// Predicate Prediction. When\r
- /// 0, the processor may predict\r
- /// predicate results and\r
- /// execute speculatively, but\r
- /// may not commit results until\r
- /// the actual predicates are\r
- /// known. When 1, the processor\r
- /// shall not execute predicated\r
- /// instructions until the\r
- /// actual predicates are known.\r
-\r
- UINT64 DisableSpontaneousDeferral:1; /// Bit44, Disable Spontaneous\r
- /// Deferral. When 1, the\r
- /// processor may optionally\r
- /// defer speculative loads\r
- /// that do not encounter any\r
- /// exception conditions, but\r
- /// that trigger other\r
- /// implementation-dependent\r
- /// conditions (e.g., cache\r
- /// miss). When 0, spontaneous\r
- /// deferral is disabled.\r
-\r
- UINT64 DisableDynamicDataCachePrefetch:1; /// Bit45, Disable Dynamic\r
- /// Data Cache Prefetch.\r
- /// When 0, the processor\r
- /// may prefetch into the\r
- /// caches any data which\r
- /// has not been accessed\r
- /// by instruction\r
- /// execution, but which\r
- /// is likely to be\r
- /// accessed. When 1, no\r
- /// data may be fetched\r
- /// until it is needed for\r
- /// instruction execution\r
- /// or is fetched by an\r
- /// lfetch instruction.\r
-\r
- UINT64 DisableDynamicInsCachePrefetch:1; /// Bit46, Disable\r
- /// DynamicInstruction Cache\r
- /// Prefetch. When 0, the\r
- /// processor may prefetch\r
- /// into the caches any\r
- /// instruction which has\r
- /// not been executed, but\r
- /// whose execution is\r
- /// likely. When 1,\r
- /// instructions may not be\r
- /// fetched until needed or\r
- /// hinted for execution.\r
- /// (Prefetch for a hinted\r
- /// branch is allowed even\r
- /// when dynamic instruction\r
- /// cache prefetch is\r
- /// disabled.)\r
-\r
- UINT64 DisableBranchPrediction:1; /// Bit47, Disable Dynamic branch\r
- /// prediction. When 0, the\r
- /// processor may predict branch\r
- /// targets and speculatively\r
- /// execute, but may not commit\r
- /// results. When 1, the processor\r
- /// must wait until branch targets\r
- /// are known to execute.\r
+ UINT64 NoSimpleImpInUndefinedIns:1; ///< Bit38, No Simple\r
+ ///< implementation of\r
+ ///< unimplemented instruction\r
+ ///< addresses. Denotes how an\r
+ ///< unimplemented instruction\r
+ ///< address is recorded in IIP\r
+ ///< on an Unimplemented\r
+ ///< Instruction Address trap or\r
+ ///< fault. When 1, the full\r
+ ///< unimplemented address is\r
+ ///< recorded in IIP; when 0, the\r
+ ///< address is sign extended\r
+ ///< (virtual addresses) or zero\r
+ ///< extended (physical\r
+ ///< addresses). This feature may\r
+ ///< only be interrogated by\r
+ ///< PAL_PROC_GET_FEATURES. It\r
+ ///< may not be enabled or\r
+ ///< disabled by\r
+ ///< PAL_PROC_SET_FEATURES. The\r
+ ///< corresponding argument is\r
+ ///< ignored.\r
+\r
+ UINT64 NoVariablePState:1; ///< Bit39, No Variable P-state\r
+ ///< performance: A value of 1, indicates\r
+ ///< that a processor implements\r
+ ///< techniques to optimize performance\r
+ ///< for the given P-state power budget\r
+ ///< by dynamically varying the\r
+ ///< frequency, such that maximum\r
+ ///< performance is achieved for the\r
+ ///< power budget. A value of 0,\r
+ ///< indicates that P-states have no\r
+ ///< frequency variation or very small\r
+ ///< frequency variations for their given\r
+ ///< power budget. This feature may only\r
+ ///< be interrogated by\r
+ ///< PAL_PROC_GET_FEATURES. it may not be\r
+ ///< enabled or disabled by\r
+ ///< PAL_PROC_SET_FEATURES. The\r
+ ///< corresponding argument is ignored.\r
+\r
+ UINT64 NoVM:1; ///< Bit40, No Virtual Machine features implemented.\r
+ ///< Denotes whether PSR.vm is implemented. This\r
+ ///< feature may only be interrogated by\r
+ ///< PAL_PROC_GET_FEATURES. It may not be enabled or\r
+ ///< disabled by PAL_PROC_SET_FEATURES. The\r
+ ///< corresponding argument is ignored.\r
+\r
+ UINT64 NoXipXpsrXfs:1; ///< Bit41, No XIP, XPSR, and XFS\r
+ ///< implemented. Denotes whether XIP, XPSR,\r
+ ///< and XFS are implemented for machine\r
+ ///< check recovery. This feature may only be\r
+ ///< interrogated by PAL_PROC_GET_FEATURES.\r
+ ///< It may not be enabled or disabled by\r
+ ///< PAL_PROC_SET_FEATURES. The corresponding\r
+ ///< argument is ignored.\r
+\r
+ UINT64 NoXr1ThroughXr3:1; ///< Bit42, No XR1 through XR3 implemented.\r
+ ///< Denotes whether XR1 XR3 are\r
+ ///< implemented for machine check\r
+ ///< recovery. This feature may only be\r
+ ///< interrogated by PAL_PROC_GET_FEATURES.\r
+ ///< It may not be enabled or disabled by\r
+ ///< PAL_PROC_SET_FEATURES. The\r
+ ///< corresponding argument is ignored.\r
+\r
+ UINT64 DisableDynamicPrediction:1; ///< Bit43, Disable Dynamic\r
+ ///< Predicate Prediction. When\r
+ ///< 0, the processor may predict\r
+ ///< predicate results and\r
+ ///< execute speculatively, but\r
+ ///< may not commit results until\r
+ ///< the actual predicates are\r
+ ///< known. When 1, the processor\r
+ ///< shall not execute predicated\r
+ ///< instructions until the\r
+ ///< actual predicates are known.\r
+\r
+ UINT64 DisableSpontaneousDeferral:1; ///< Bit44, Disable Spontaneous\r
+ ///< Deferral. When 1, the\r
+ ///< processor may optionally\r
+ ///< defer speculative loads\r
+ ///< that do not encounter any\r
+ ///< exception conditions, but\r
+ ///< that trigger other\r
+ ///< implementation-dependent\r
+ ///< conditions (e.g., cache\r
+ ///< miss). When 0, spontaneous\r
+ ///< deferral is disabled.\r
+\r
+ UINT64 DisableDynamicDataCachePrefetch:1; ///< Bit45, Disable Dynamic\r
+ ///< Data Cache Prefetch.\r
+ ///< When 0, the processor\r
+ ///< may prefetch into the\r
+ ///< caches any data which\r
+ ///< has not been accessed\r
+ ///< by instruction\r
+ ///< execution, but which\r
+ ///< is likely to be\r
+ ///< accessed. When 1, no\r
+ ///< data may be fetched\r
+ ///< until it is needed for\r
+ ///< instruction execution\r
+ ///< or is fetched by an\r
+ ///< lfetch instruction.\r
+\r
+ UINT64 DisableDynamicInsCachePrefetch:1; ///< Bit46, Disable\r
+ ///< DynamicInstruction Cache\r
+ ///< Prefetch. When 0, the\r
+ ///< processor may prefetch\r
+ ///< into the caches any\r
+ ///< instruction which has\r
+ ///< not been executed, but\r
+ ///< whose execution is\r
+ ///< likely. When 1,\r
+ ///< instructions may not be\r
+ ///< fetched until needed or\r
+ ///< hinted for execution.\r
+ ///< (Prefetch for a hinted\r
+ ///< branch is allowed even\r
+ ///< when dynamic instruction\r
+ ///< cache prefetch is\r
+ ///< disabled.)\r
+\r
+ UINT64 DisableBranchPrediction:1; ///< Bit47, Disable Dynamic branch\r
+ ///< prediction. When 0, the\r
+ ///< processor may predict branch\r
+ ///< targets and speculatively\r
+ ///< execute, but may not commit\r
+ ///< results. When 1, the processor\r
+ ///< must wait until branch targets\r
+ ///< are known to execute.\r
UINT64 Reserved2:4;\r
- UINT64 DisablePState:1; /// Bit52, Disable P-states. When 1, the PAL\r
- /// P-state procedures (PAL_PSTATE_INFO,\r
- /// PAL_SET_PSTATE, PAL_GET_PSTATE) will\r
- /// return with a status of -1\r
- /// (Unimplemented procedure).\r
-\r
- UINT64 EnableMcaOnDataPoisoning:1; /// Bit53, Enable MCA signaling\r
- /// on data-poisoning event\r
- /// detection. When 0, a CMCI\r
- /// will be signaled on error\r
- /// detection. When 1, an MCA\r
- /// will be signaled on error\r
- /// detection. If this feature\r
- /// is not supported, then the\r
- /// corresponding argument is\r
- /// ignored when calling\r
- /// PAL_PROC_SET_FEATURES. Note\r
- /// that the functionality of\r
- /// this bit is independent of\r
- /// the setting in bit 60\r
- /// (Enable CMCI promotion), and\r
- /// that the bit 60 setting does\r
- /// not affect CMCI signaling\r
- /// for data-poisoning related\r
- /// events. Volume 2: Processor\r
- /// Abstraction Layer 2:431\r
- /// PAL_PROC_GET_FEATURES\r
-\r
- UINT64 EnableVmsw:1; /// Bit54, Enable the use of the vmsw\r
- /// instruction. When 0, the vmsw instruction\r
- /// causes a Virtualization fault when\r
- /// executed at the most privileged level.\r
- /// When 1, this bit will enable normal\r
- /// operation of the vmsw instruction.\r
-\r
- UINT64 EnableEnvNotification:1; /// Bit55, Enable external\r
- /// notification when the processor\r
- /// detects hardware errors caused\r
- /// by environmental factors that\r
- /// could cause loss of\r
- /// deterministic behavior of the\r
- /// processor. When 1, this bit will\r
- /// enable external notification,\r
- /// when 0 external notification is\r
- /// not provided. The type of\r
- /// external notification of these\r
- /// errors is processor-dependent. A\r
- /// loss of processor deterministic\r
- /// behavior is considered to have\r
- /// occurred if these\r
- /// environmentally induced errors\r
- /// cause the processor to deviate\r
- /// from its normal execution and\r
- /// eventually causes different\r
- /// behavior which can be observed\r
- /// at the processor bus pins.\r
- /// Processor errors that do not\r
- /// have this effects (i.e.,\r
- /// software induced machine checks)\r
- /// may or may not be promoted\r
- /// depending on the processor\r
- /// implementation.\r
-\r
- UINT64 DisableBinitWithTimeout:1; /// Bit56, Disable a BINIT on\r
- /// internal processor time-out.\r
- /// When 0, the processor may\r
- /// generate a BINIT on an\r
- /// internal processor time-out.\r
- /// When 1, the processor will not\r
- /// generate a BINIT on an\r
- /// internal processor time-out.\r
- /// The event is silently ignored.\r
-\r
- UINT64 DisableDPM:1; /// Bit57, Disable Dynamic Power Management\r
- /// (DPM). When 0, the hardware may reduce\r
- /// power consumption by removing the clock\r
- /// input from idle functional units. When 1,\r
- /// all functional units will receive clock\r
- /// input, even when idle.\r
-\r
- UINT64 DisableCoherency:1; /// Bit58, Disable Coherency. When 0,\r
- /// the processor uses normal coherency\r
- /// requests and responses. When 1, the\r
- /// processor answers all requests as if\r
- /// the line were not present.\r
-\r
- UINT64 DisableCache:1; /// Bit59, Disable Cache. When 0, the\r
- /// processor performs cast outs on\r
- /// cacheable pages and issues and responds\r
- /// to coherency requests normally. When 1,\r
- /// the processor performs a memory access\r
- /// for each reference regardless of cache\r
- /// contents and issues no coherence\r
- /// requests and responds as if the line\r
- /// were not present. Cache contents cannot\r
- /// be relied upon when the cache is\r
- /// disabled. WARNING: Semaphore\r
- /// instructions may not be atomic or may\r
- /// cause Unsupported Data Reference faults\r
- /// if caches are disabled.\r
-\r
- UINT64 EnableCmciPromotion:1; /// Bit60, Enable CMCI promotion When\r
- /// 1, Corrected Machine Check\r
- /// Interrupts (CMCI) are promoted to\r
- /// MCAs. They are also further\r
- /// promoted to BERR if bit 39, Enable\r
- /// MCA promotion, is also set and\r
- /// they are promoted to BINIT if bit\r
- /// 38, Enable MCA to BINIT promotion,\r
- /// is also set. This bit has no\r
- /// effect if MCA signalling is\r
- /// disabled (see\r
- /// PAL_BUS_GET/SET_FEATURES)\r
-\r
- UINT64 EnableMcaToBinitPromotion:1; /// Bit61, Enable MCA to BINIT\r
- /// promotion. When 1, machine\r
- /// check aborts (MCAs) are\r
- /// promoted to the Bus\r
- /// Initialization signal, and\r
- /// the BINIT pin is assert on\r
- /// each occurrence of an MCA.\r
- /// Setting this bit has no\r
- /// effect if BINIT signalling\r
- /// is disabled. (See\r
- /// PAL_BUS_GET/SET_FEATURES)\r
-\r
- UINT64 EnableMcaPromotion:1; /// Bit62, Enable MCA promotion. When\r
- /// 1, machine check aborts (MCAs) are\r
- /// promoted to the Bus Error signal,\r
- /// and the BERR pin is assert on each\r
- /// occurrence of an MCA. Setting this\r
- /// bit has no effect if BERR\r
- /// signalling is disabled. (See\r
- /// PAL_BUS_GET/SET_FEATURES)\r
+ UINT64 DisablePState:1; ///< Bit52, Disable P-states. When 1, the PAL\r
+ ///< P-state procedures (PAL_PSTATE_INFO,\r
+ ///< PAL_SET_PSTATE, PAL_GET_PSTATE) will\r
+ ///< return with a status of -1\r
+ ///< (Unimplemented procedure).\r
+\r
+ UINT64 EnableMcaOnDataPoisoning:1; ///< Bit53, Enable MCA signaling\r
+ ///< on data-poisoning event\r
+ ///< detection. When 0, a CMCI\r
+ ///< will be signaled on error\r
+ ///< detection. When 1, an MCA\r
+ ///< will be signaled on error\r
+ ///< detection. If this feature\r
+ ///< is not supported, then the\r
+ ///< corresponding argument is\r
+ ///< ignored when calling\r
+ ///< PAL_PROC_SET_FEATURES. Note\r
+ ///< that the functionality of\r
+ ///< this bit is independent of\r
+ ///< the setting in bit 60\r
+ ///< (Enable CMCI promotion), and\r
+ ///< that the bit 60 setting does\r
+ ///< not affect CMCI signaling\r
+ ///< for data-poisoning related\r
+ ///< events. Volume 2: Processor\r
+ ///< Abstraction Layer 2:431\r
+ ///< PAL_PROC_GET_FEATURES\r
+\r
+ UINT64 EnableVmsw:1; ///< Bit54, Enable the use of the vmsw\r
+ ///< instruction. When 0, the vmsw instruction\r
+ ///< causes a Virtualization fault when\r
+ ///< executed at the most privileged level.\r
+ ///< When 1, this bit will enable normal\r
+ ///< operation of the vmsw instruction.\r
+\r
+ UINT64 EnableEnvNotification:1; ///< Bit55, Enable external\r
+ ///< notification when the processor\r
+ ///< detects hardware errors caused\r
+ ///< by environmental factors that\r
+ ///< could cause loss of\r
+ ///< deterministic behavior of the\r
+ ///< processor. When 1, this bit will\r
+ ///< enable external notification,\r
+ ///< when 0 external notification is\r
+ ///< not provided. The type of\r
+ ///< external notification of these\r
+ ///< errors is processor-dependent. A\r
+ ///< loss of processor deterministic\r
+ ///< behavior is considered to have\r
+ ///< occurred if these\r
+ ///< environmentally induced errors\r
+ ///< cause the processor to deviate\r
+ ///< from its normal execution and\r
+ ///< eventually causes different\r
+ ///< behavior which can be observed\r
+ ///< at the processor bus pins.\r
+ ///< Processor errors that do not\r
+ ///< have this effects (i.e.,\r
+ ///< software induced machine checks)\r
+ ///< may or may not be promoted\r
+ ///< depending on the processor\r
+ ///< implementation.\r
+\r
+ UINT64 DisableBinitWithTimeout:1; ///< Bit56, Disable a BINIT on\r
+ ///< internal processor time-out.\r
+ ///< When 0, the processor may\r
+ ///< generate a BINIT on an\r
+ ///< internal processor time-out.\r
+ ///< When 1, the processor will not\r
+ ///< generate a BINIT on an\r
+ ///< internal processor time-out.\r
+ ///< The event is silently ignored.\r
+\r
+ UINT64 DisableDPM:1; ///< Bit57, Disable Dynamic Power Management\r
+ ///< (DPM). When 0, the hardware may reduce\r
+ ///< power consumption by removing the clock\r
+ ///< input from idle functional units. When 1,\r
+ ///< all functional units will receive clock\r
+ ///< input, even when idle.\r
+\r
+ UINT64 DisableCoherency:1; ///< Bit58, Disable Coherency. When 0,\r
+ ///< the processor uses normal coherency\r
+ ///< requests and responses. When 1, the\r
+ ///< processor answers all requests as if\r
+ ///< the line were not present.\r
+\r
+ UINT64 DisableCache:1; ///< Bit59, Disable Cache. When 0, the\r
+ ///< processor performs cast outs on\r
+ ///< cacheable pages and issues and responds\r
+ ///< to coherency requests normally. When 1,\r
+ ///< the processor performs a memory access\r
+ ///< for each reference regardless of cache\r
+ ///< contents and issues no coherence\r
+ ///< requests and responds as if the line\r
+ ///< were not present. Cache contents cannot\r
+ ///< be relied upon when the cache is\r
+ ///< disabled. WARNING: Semaphore\r
+ ///< instructions may not be atomic or may\r
+ ///< cause Unsupported Data Reference faults\r
+ ///< if caches are disabled.\r
+\r
+ UINT64 EnableCmciPromotion:1; ///< Bit60, Enable CMCI promotion When\r
+ ///< 1, Corrected Machine Check\r
+ ///< Interrupts (CMCI) are promoted to\r
+ ///< MCAs. They are also further\r
+ ///< promoted to BERR if bit 39, Enable\r
+ ///< MCA promotion, is also set and\r
+ ///< they are promoted to BINIT if bit\r
+ ///< 38, Enable MCA to BINIT promotion,\r
+ ///< is also set. This bit has no\r
+ ///< effect if MCA signalling is\r
+ ///< disabled (see\r
+ ///< PAL_BUS_GET/SET_FEATURES)\r
+\r
+ UINT64 EnableMcaToBinitPromotion:1; ///< Bit61, Enable MCA to BINIT\r
+ ///< promotion. When 1, machine\r
+ ///< check aborts (MCAs) are\r
+ ///< promoted to the Bus\r
+ ///< Initialization signal, and\r
+ ///< the BINIT pin is assert on\r
+ ///< each occurrence of an MCA.\r
+ ///< Setting this bit has no\r
+ ///< effect if BINIT signalling\r
+ ///< is disabled. (See\r
+ ///< PAL_BUS_GET/SET_FEATURES)\r
+\r
+ UINT64 EnableMcaPromotion:1; ///< Bit62, Enable MCA promotion. When\r
+ ///< 1, machine check aborts (MCAs) are\r
+ ///< promoted to the Bus Error signal,\r
+ ///< and the BERR pin is assert on each\r
+ ///< occurrence of an MCA. Setting this\r
+ ///< bit has no effect if BERR\r
+ ///< signalling is disabled. (See\r
+ ///< PAL_BUS_GET/SET_FEATURES)\r
\r
- UINT64 EnableBerrPromotion:1; /// Bit63. Enable BERR promotion. When\r
- /// 1, the Bus Error (BERR) signal is\r
- /// promoted to the Bus Initialization\r
- /// (BINIT) signal, and the BINIT pin\r
- /// is asserted on the occurrence of\r
- /// each Bus Error. Setting this bit\r
- /// has no effect if BINIT signalling\r
- /// is disabled. (See\r
- /// PAL_BUS_GET/SET_FEATURES)\r
+ UINT64 EnableBerrPromotion:1; ///< Bit63. Enable BERR promotion. When\r
+ ///< 1, the Bus Error (BERR) signal is\r
+ ///< promoted to the Bus Initialization\r
+ ///< (BINIT) signal, and the BINIT pin\r
+ ///< is asserted on the occurrence of\r
+ ///< each Bus Error. Setting this bit\r
+ ///< has no effect if BINIT signalling\r
+ ///< is disabled. (See\r
+ ///< PAL_BUS_GET/SET_FEATURES)\r
} PAL_PROCESSOR_FEATURES;\r
\r
/**\r
#define PAL_RSE_INFO 19\r
\r
typedef struct {\r
- UINT64 VersionOfPalB:16; /// Is a 16-bit binary coded decimal (BCD)\r
- /// number that provides identification\r
- /// information about the PAL_B firmware.\r
+ UINT64 VersionOfPalB:16; ///< Is a 16-bit binary coded decimal (BCD)\r
+ ///< number that provides identification\r
+ ///< information about the PAL_B firmware.\r
UINT64 Reserved1:8;\r
- UINT64 PalVendor:8; /// Is an unsigned 8-bit integer indicating the\r
- /// vendor of the PAL code.\r
- UINT64 VersionOfPalA:16; /// Is a 16-bit binary coded decimal (BCD)\r
- /// number that provides identification\r
- /// information about the PAL_A firmware. In\r
- /// the split PAL_A model, this return value\r
- /// is the version number of the\r
- /// processor-specific PAL_A. The generic\r
- /// PAL_A version is not returned by this\r
- /// procedure in the split PAL_A model.\r
+ UINT64 PalVendor:8; ///< Is an unsigned 8-bit integer indicating the\r
+ ///< vendor of the PAL code.\r
+ UINT64 VersionOfPalA:16; ///< Is a 16-bit binary coded decimal (BCD)\r
+ ///< number that provides identification\r
+ ///< information about the PAL_A firmware. In\r
+ ///< the split PAL_A model, this return value\r
+ ///< is the version number of the\r
+ ///< processor-specific PAL_A. The generic\r
+ ///< PAL_A version is not returned by this\r
+ ///< procedure in the split PAL_A model.\r
UINT64 Reserved2:16;\r
} PAL_VERSION_INFO;\r
\r
#define PAL_STRUCTURE_SPECIFIC_ERROR 2\r
\r
typedef struct {\r
- UINT64 CoreId:4; /// Bit3:0, Processor core ID (default is 0 for\r
- /// processors with a single core)\r
-\r
- UINT64 ThreadId:4; /// Bit7:4, Logical thread ID (default is 0 for\r
- /// processors that execute a single thread)\r
-\r
- UINT64 InfoOfInsCache:4; /// Bit11:8, Error information is\r
- /// available for 1st, 2nd, 3rd, and 4th\r
- /// level instruction caches.\r
-\r
- UINT64 InfoOfDataCache:4; /// Bit15:12, Error information is\r
- /// available for 1st, 2nd, 3rd, and 4th\r
- /// level data/unified caches.\r
-\r
- UINT64 InfoOfInsTlb:4; /// Bit19:16 Error information is available\r
- /// for 1st, 2nd, 3rd, and 4th level\r
- /// instruction TLB.\r
-\r
- UINT64 InfoOfDataTlb:4; /// Bit23:20, Error information is available\r
- /// for 1st, 2nd, 3rd, and 4th level\r
- /// data/unified TLB\r
-\r
- UINT64 InfoOfProcessorBus:4; /// Bit27:24 Error information is\r
- /// available for the 1st, 2nd, 3rd,\r
- /// and 4th level processor bus\r
- /// hierarchy.\r
- UINT64 InfoOfRegisterFile:4; /// Bit31:28 Error information is\r
- /// available on register file\r
- /// structures.\r
- UINT64 InfoOfMicroArch:4; /// Bit47:32, Error information is\r
- /// available on micro-architectural\r
- /// structures.\r
+ UINT64 CoreId:4; ///< Bit3:0, Processor core ID (default is 0 for\r
+ ///< processors with a single core)\r
+\r
+ UINT64 ThreadId:4; ///< Bit7:4, Logical thread ID (default is 0 for\r
+ ///< processors that execute a single thread)\r
+\r
+ UINT64 InfoOfInsCache:4; ///< Bit11:8, Error information is\r
+ ///< available for 1st, 2nd, 3rd, and 4th\r
+ ///< level instruction caches.\r
+\r
+ UINT64 InfoOfDataCache:4; ///< Bit15:12, Error information is\r
+ ///< available for 1st, 2nd, 3rd, and 4th\r
+ ///< level data/unified caches.\r
+\r
+ UINT64 InfoOfInsTlb:4; ///< Bit19:16 Error information is available\r
+ ///< for 1st, 2nd, 3rd, and 4th level\r
+ ///< instruction TLB.\r
+\r
+ UINT64 InfoOfDataTlb:4; ///< Bit23:20, Error information is available\r
+ ///< for 1st, 2nd, 3rd, and 4th level\r
+ ///< data/unified TLB\r
+\r
+ UINT64 InfoOfProcessorBus:4; ///< Bit27:24 Error information is\r
+ ///< available for the 1st, 2nd, 3rd,\r
+ ///< and 4th level processor bus\r
+ ///< hierarchy.\r
+ UINT64 InfoOfRegisterFile:4; ///< Bit31:28 Error information is\r
+ ///< available on register file\r
+ ///< structures.\r
+ UINT64 InfoOfMicroArch:4; ///< Bit47:32, Error information is\r
+ ///< available on micro-architectural\r
+ ///< structures.\r
UINT64 Reserved:16;\r
} PAL_MC_ERROR_INFO_LEVEL_INDEX;\r
\r
#define PAL_ERR_INFO_PRECISE_INSTRUCTION_POINTER 4\r
\r
typedef struct {\r
- UINT64 Operation:4; /// Bit3:0, Type of cache operation that caused\r
- /// the machine check: 0 - unknown or internal\r
- /// error 1 - load 2 - store 3 - instruction\r
- /// fetch or instruction prefetch 4 - data\r
- /// prefetch (both hardware and software) 5 -\r
- /// snoop (coherency check) 6 - cast out\r
- /// (explicit or implicit write-back of a cache\r
- /// line) 7 - move in (cache line fill)\r
-\r
- UINT64 FailedCacheLevel:2; /// Bit5:4 Level of cache where the\r
- /// error occurred. A value of 0\r
- /// indicates the first level of cache.\r
+ UINT64 Operation:4; ///< Bit3:0, Type of cache operation that caused\r
+ ///< the machine check: 0 - unknown or internal\r
+ ///< error 1 - load 2 - store 3 - instruction\r
+ ///< fetch or instruction prefetch 4 - data\r
+ ///< prefetch (both hardware and software) 5 -\r
+ ///< snoop (coherency check) 6 - cast out\r
+ ///< (explicit or implicit write-back of a cache\r
+ ///< line) 7 - move in (cache line fill)\r
+\r
+ UINT64 FailedCacheLevel:2; ///< Bit5:4 Level of cache where the\r
+ ///< error occurred. A value of 0\r
+ ///< indicates the first level of cache.\r
UINT64 Reserved1:2;\r
- UINT64 FailedInDataPart:1; /// Bit8, Failure located in the data part of the cache line.\r
- UINT64 FailedInTagPart:1; /// Bit9, Failure located in the tag part of the cache line.\r
- UINT64 FailedInDataCache:1; /// Bit10, Failure located in the data cache\r
+ UINT64 FailedInDataPart:1; ///< Bit8, Failure located in the data part of the cache line.\r
+ UINT64 FailedInTagPart:1; ///< Bit9, Failure located in the tag part of the cache line.\r
+ UINT64 FailedInDataCache:1; ///< Bit10, Failure located in the data cache\r
\r
- UINT64 FailedInInsCache:1; /// Bit11, Failure located in the\r
- /// instruction cache.\r
+ UINT64 FailedInInsCache:1; ///< Bit11, Failure located in the\r
+ ///< instruction cache.\r
\r
- UINT64 Mesi:3; /// Bit14:12, 0 - cache line is invalid. 1 - cache\r
- /// line is held shared. 2 - cache line is held\r
- /// exclusive. 3 - cache line is modified. All other\r
- /// values are reserved.\r
+ UINT64 Mesi:3; ///< Bit14:12, 0 - cache line is invalid. 1 - cache\r
+ ///< line is held shared. 2 - cache line is held\r
+ ///< exclusive. 3 - cache line is modified. All other\r
+ ///< values are reserved.\r
\r
- UINT64 MesiIsValid:1; /// Bit15, The mesi field in the cache_check\r
- /// parameter is valid.\r
+ UINT64 MesiIsValid:1; ///< Bit15, The mesi field in the cache_check\r
+ ///< parameter is valid.\r
\r
- UINT64 FailedWay:5; /// Bit20:16, Failure located in the way of\r
- /// the cache indicated by this value.\r
+ UINT64 FailedWay:5; ///< Bit20:16, Failure located in the way of\r
+ ///< the cache indicated by this value.\r
\r
- UINT64 WayIndexIsValid:1; /// Bit21, The way and index field in the\r
- /// cache_check parameter is valid.\r
+ UINT64 WayIndexIsValid:1; ///< Bit21, The way and index field in the\r
+ ///< cache_check parameter is valid.\r
\r
UINT64 Reserved2:1;\r
- UINT64 MultipleBitsError:1; /// Bit23, A multiple-bit error was\r
- /// detected, and data was poisoned for\r
- /// the corresponding cache line during\r
- /// castout.\r
+ UINT64 MultipleBitsError:1; ///< Bit23, A multiple-bit error was\r
+ ///< detected, and data was poisoned for\r
+ ///< the corresponding cache line during\r
+ ///< castout.\r
UINT64 Reserved3:8;\r
- UINT64 IndexOfCacheLineError:20; /// Bit51:32, Index of the cache\r
- /// line where the error occurred.\r
+ UINT64 IndexOfCacheLineError:20; ///< Bit51:32, Index of the cache\r
+ ///< line where the error occurred.\r
UINT64 Reserved4:2;\r
\r
- UINT64 InstructionSet:1; /// Bit54, Instruction set. If this value\r
- /// is set to zero, the instruction that\r
- /// generated the machine check was an\r
- /// Intel Itanium instruction. If this bit\r
- /// is set to one, the instruction that\r
- /// generated the machine check was IA-32\r
- /// instruction.\r
-\r
- UINT64 InstructionSetIsValid:1; /// Bit55, The is field in the\r
- /// cache_check parameter is valid.\r
-\r
- UINT64 PrivilegeLevel:2; /// Bit57:56, Privilege level. The\r
- /// privilege level of the instruction\r
- /// bundle responsible for generating the\r
- /// machine check.\r
-\r
- UINT64 PrivilegeLevelIsValide:1; /// Bit58, The pl field of the\r
- /// cache_check parameter is\r
- /// valid.\r
-\r
- UINT64 McCorrected:1; /// Bit59, Machine check corrected: This bit\r
- /// is set to one to indicate that the machine\r
- /// check has been corrected.\r
-\r
- UINT64 TargetAddressIsValid:1; /// Bit60, Target address is valid:\r
- /// This bit is set to one to\r
- /// indicate that a valid target\r
- /// address has been logged.\r
-\r
- UINT64 RequesterIdentifier:1; /// Bit61, Requester identifier: This\r
- /// bit is set to one to indicate that\r
- /// a valid requester identifier has\r
- /// been logged.\r
-\r
- UINT64 ResponserIdentifier:1; /// Bit62, Responder identifier: This\r
- /// bit is set to one to indicate that\r
- /// a valid responder identifier has\r
- /// been logged.\r
-\r
- UINT64 PreciseInsPointer:1; /// Bit63, Precise instruction pointer.\r
- /// This bit is set to one to indicate\r
- /// that a valid precise instruction\r
- /// pointer has been logged.\r
+ UINT64 InstructionSet:1; ///< Bit54, Instruction set. If this value\r
+ ///< is set to zero, the instruction that\r
+ ///< generated the machine check was an\r
+ ///< Intel Itanium instruction. If this bit\r
+ ///< is set to one, the instruction that\r
+ ///< generated the machine check was IA-32\r
+ ///< instruction.\r
+\r
+ UINT64 InstructionSetIsValid:1; ///< Bit55, The is field in the\r
+ ///< cache_check parameter is valid.\r
+\r
+ UINT64 PrivilegeLevel:2; ///< Bit57:56, Privilege level. The\r
+ ///< privilege level of the instruction\r
+ ///< bundle responsible for generating the\r
+ ///< machine check.\r
+\r
+ UINT64 PrivilegeLevelIsValide:1; ///< Bit58, The pl field of the\r
+ ///< cache_check parameter is\r
+ ///< valid.\r
+\r
+ UINT64 McCorrected:1; ///< Bit59, Machine check corrected: This bit\r
+ ///< is set to one to indicate that the machine\r
+ ///< check has been corrected.\r
+\r
+ UINT64 TargetAddressIsValid:1; ///< Bit60, Target address is valid:\r
+ ///< This bit is set to one to\r
+ ///< indicate that a valid target\r
+ ///< address has been logged.\r
+\r
+ UINT64 RequesterIdentifier:1; ///< Bit61, Requester identifier: This\r
+ ///< bit is set to one to indicate that\r
+ ///< a valid requester identifier has\r
+ ///< been logged.\r
+\r
+ UINT64 ResponserIdentifier:1; ///< Bit62, Responder identifier: This\r
+ ///< bit is set to one to indicate that\r
+ ///< a valid responder identifier has\r
+ ///< been logged.\r
+\r
+ UINT64 PreciseInsPointer:1; ///< Bit63, Precise instruction pointer.\r
+ ///< This bit is set to one to indicate\r
+ ///< that a valid precise instruction\r
+ ///< pointer has been logged.\r
\r
} PAL_CACHE_CHECK_INFO;\r
\r
\r
typedef struct {\r
- UINT64 FailedSlot:8; /// Bit7:0, Slot number of the translation\r
- /// register where the failure occurred.\r
- UINT64 FailedSlotIsValid:1; /// Bit8, The tr_slot field in the\r
- /// TLB_check parameter is valid.\r
+ UINT64 FailedSlot:8; ///< Bit7:0, Slot number of the translation\r
+ ///< register where the failure occurred.\r
+ UINT64 FailedSlotIsValid:1; ///< Bit8, The tr_slot field in the\r
+ ///< TLB_check parameter is valid.\r
UINT64 Reserved1 :1;\r
- UINT64 TlbLevel:2; /// Bit11:10, The level of the TLB where the\r
- /// error occurred. A value of 0 indicates the\r
- /// first level of TLB\r
+ UINT64 TlbLevel:2; ///< Bit11:10, The level of the TLB where the\r
+ ///< error occurred. A value of 0 indicates the\r
+ ///< first level of TLB\r
UINT64 Reserved2 :4;\r
\r
- UINT64 FailedInDataTr:1; /// Bit16, Error occurred in the data\r
- /// translation registers.\r
-\r
- UINT64 FailedInInsTr:1; /// Bit17, Error occurred in the instruction\r
- /// translation registers\r
-\r
- UINT64 FailedInDataTc:1; /// Bit18, Error occurred in data\r
- /// translation cache.\r
-\r
- UINT64 FailedInInsTc:1; /// Bit19, Error occurred in the instruction\r
- /// translation cache.\r
-\r
- UINT64 FailedOperation:4; /// Bit23:20, Type of cache operation that\r
- /// caused the machine check: 0 - unknown\r
- /// 1 - TLB access due to load instruction\r
- /// 2 - TLB access due to store\r
- /// instruction 3 - TLB access due to\r
- /// instruction fetch or instruction\r
- /// prefetch 4 - TLB access due to data\r
- /// prefetch (both hardware and software)\r
- /// 5 - TLB shoot down access 6 - TLB\r
- /// probe instruction (probe, tpa) 7 -\r
- /// move in (VHPT fill) 8 - purge (insert\r
- /// operation that purges entries or a TLB\r
- /// purge instruction) All other values\r
- /// are reserved.\r
+ UINT64 FailedInDataTr:1; ///< Bit16, Error occurred in the data\r
+ ///< translation registers.\r
+\r
+ UINT64 FailedInInsTr:1; ///< Bit17, Error occurred in the instruction\r
+ ///< translation registers\r
+\r
+ UINT64 FailedInDataTc:1; ///< Bit18, Error occurred in data\r
+ ///< translation cache.\r
+\r
+ UINT64 FailedInInsTc:1; ///< Bit19, Error occurred in the instruction\r
+ ///< translation cache.\r
+\r
+ UINT64 FailedOperation:4; ///< Bit23:20, Type of cache operation that\r
+ ///< caused the machine check: 0 - unknown\r
+ ///< 1 - TLB access due to load instruction\r
+ ///< 2 - TLB access due to store\r
+ ///< instruction 3 - TLB access due to\r
+ ///< instruction fetch or instruction\r
+ ///< prefetch 4 - TLB access due to data\r
+ ///< prefetch (both hardware and software)\r
+ ///< 5 - TLB shoot down access 6 - TLB\r
+ ///< probe instruction (probe, tpa) 7 -\r
+ ///< move in (VHPT fill) 8 - purge (insert\r
+ ///< operation that purges entries or a TLB\r
+ ///< purge instruction) All other values\r
+ ///< are reserved.\r
\r
UINT64 Reserved3:30;\r
- UINT64 InstructionSet:1; /// Bit54, Instruction set. If this value\r
- /// is set to zero, the instruction that\r
- /// generated the machine check was an\r
- /// Intel Itanium instruction. If this bit\r
- /// is set to one, the instruction that\r
- /// generated the machine check was IA-32\r
- /// instruction.\r
-\r
- UINT64 InstructionSetIsValid:1; /// Bit55, The is field in the\r
- /// TLB_check parameter is valid.\r
-\r
- UINT64 PrivelegeLevel:2; /// Bit57:56, Privilege level. The\r
- /// privilege level of the instruction\r
- /// bundle responsible for generating the\r
- /// machine check.\r
-\r
- UINT64 PrivelegeLevelIsValid:1; /// Bit58, The pl field of the\r
- /// TLB_check parameter is valid.\r
-\r
- UINT64 McCorrected:1; /// Bit59, Machine check corrected: This bit\r
- /// is set to one to indicate that the machine\r
- /// check has been corrected.\r
-\r
- UINT64 TargetAddressIsValid:1; /// Bit60, Target address is valid:\r
- /// This bit is set to one to\r
- /// indicate that a valid target\r
- /// address has been logged.\r
-\r
- UINT64 RequesterIdentifier:1; /// Bit61 Requester identifier: This\r
- /// bit is set to one to indicate that\r
- /// a valid requester identifier has\r
- /// been logged.\r
-\r
- UINT64 ResponserIdentifier:1; /// Bit62, Responder identifier: This\r
- /// bit is set to one to indicate that\r
- /// a valid responder identifier has\r
- /// been logged.\r
-\r
- UINT64 PreciseInsPointer:1; /// Bit63 Precise instruction pointer.\r
- /// This bit is set to one to indicate\r
- /// that a valid precise instruction\r
- /// pointer has been logged.\r
+ UINT64 InstructionSet:1; ///< Bit54, Instruction set. If this value\r
+ ///< is set to zero, the instruction that\r
+ ///< generated the machine check was an\r
+ ///< Intel Itanium instruction. If this bit\r
+ ///< is set to one, the instruction that\r
+ ///< generated the machine check was IA-32\r
+ ///< instruction.\r
+\r
+ UINT64 InstructionSetIsValid:1; ///< Bit55, The is field in the\r
+ ///< TLB_check parameter is valid.\r
+\r
+ UINT64 PrivelegeLevel:2; ///< Bit57:56, Privilege level. The\r
+ ///< privilege level of the instruction\r
+ ///< bundle responsible for generating the\r
+ ///< machine check.\r
+\r
+ UINT64 PrivelegeLevelIsValid:1; ///< Bit58, The pl field of the\r
+ ///< TLB_check parameter is valid.\r
+\r
+ UINT64 McCorrected:1; ///< Bit59, Machine check corrected: This bit\r
+ ///< is set to one to indicate that the machine\r
+ ///< check has been corrected.\r
+\r
+ UINT64 TargetAddressIsValid:1; ///< Bit60, Target address is valid:\r
+ ///< This bit is set to one to\r
+ ///< indicate that a valid target\r
+ ///< address has been logged.\r
+\r
+ UINT64 RequesterIdentifier:1; ///< Bit61 Requester identifier: This\r
+ ///< bit is set to one to indicate that\r
+ ///< a valid requester identifier has\r
+ ///< been logged.\r
+\r
+ UINT64 ResponserIdentifier:1; ///< Bit62, Responder identifier: This\r
+ ///< bit is set to one to indicate that\r
+ ///< a valid responder identifier has\r
+ ///< been logged.\r
+\r
+ UINT64 PreciseInsPointer:1; ///< Bit63 Precise instruction pointer.\r
+ ///< This bit is set to one to indicate\r
+ ///< that a valid precise instruction\r
+ ///< pointer has been logged.\r
} PAL_TLB_CHECK_INFO;\r
\r
/**\r
#define PAL_TEST_INFO 37\r
\r
typedef struct {\r
- UINT64 BufferSize:56; /// Indicates the size in bytes of the memory\r
- /// buffer that is passed to this procedure.\r
- /// BufferSize must be greater than or equal in\r
- /// size to the bytes_needed return value from\r
- /// PAL_TEST_INFO, otherwise this procedure will\r
- /// return with an invalid argument return\r
- /// value.\r
-\r
- UINT64 TestPhase:8; /// Defines which phase of the processor\r
- /// self-tests are requested to be run. A value\r
- /// of zero indicates to run phase two of the\r
- /// processor self-tests. Phase two of the\r
- /// processor self-tests are ones that require\r
- /// external memory to execute correctly. A\r
- /// value of one indicates to run phase one of\r
- /// the processor self-tests. Phase one of the\r
- /// processor self-tests are tests run during\r
- /// PALE_RESET and do not depend on external\r
- /// memory to run correctly. When the caller\r
- /// requests to have phase one of the processor\r
- /// self-test run via this procedure call, a\r
- /// memory buffer may be needed to save and\r
- /// restore state as required by the PAL calling\r
- /// conventions. The procedure PAL_TEST_INFO\r
- /// informs the caller about the requirements of\r
- /// the memory buffer.\r
+ UINT64 BufferSize:56; ///< Indicates the size in bytes of the memory\r
+ ///< buffer that is passed to this procedure.\r
+ ///< BufferSize must be greater than or equal in\r
+ ///< size to the bytes_needed return value from\r
+ ///< PAL_TEST_INFO, otherwise this procedure will\r
+ ///< return with an invalid argument return\r
+ ///< value.\r
+\r
+ UINT64 TestPhase:8; ///< Defines which phase of the processor\r
+ ///< self-tests are requested to be run. A value\r
+ ///< of zero indicates to run phase two of the\r
+ ///< processor self-tests. Phase two of the\r
+ ///< processor self-tests are ones that require\r
+ ///< external memory to execute correctly. A\r
+ ///< value of one indicates to run phase one of\r
+ ///< the processor self-tests. Phase one of the\r
+ ///< processor self-tests are tests run during\r
+ ///< PALE_RESET and do not depend on external\r
+ ///< memory to run correctly. When the caller\r
+ ///< requests to have phase one of the processor\r
+ ///< self-test run via this procedure call, a\r
+ ///< memory buffer may be needed to save and\r
+ ///< restore state as required by the PAL calling\r
+ ///< conventions. The procedure PAL_TEST_INFO\r
+ ///< informs the caller about the requirements of\r
+ ///< the memory buffer.\r
} PAL_TEST_INFO_INFO;\r
\r
typedef struct {\r
- UINT64 TestControl:47; /// This is an ordered implementation-specific\r
- /// control word that allows the user control\r
- /// over the length and runtime of the\r
- /// processor self-tests. This control word is\r
- /// ordered from the longest running tests up\r
- /// to the shortest running tests with bit 0\r
- /// controlling the longest running test. PAL\r
- /// may not implement all 47-bits of the\r
- /// test_control word. PAL communicates if a\r
- /// bit provides control by placing a zero in\r
- /// that bit. If a bit provides no control,\r
- /// PAL will place a one in it. PAL will have\r
- /// two sets of test_control bits for the two\r
- /// phases of the processor self-test. PAL\r
- /// provides information about implemented\r
- /// test_control bits at the hand-off from PAL\r
- /// to SAL for the firmware recovery check.\r
- /// These test_control bits provide control\r
- /// for phase one of processor self-test. It\r
- /// also provides this information via the PAL\r
- /// procedure call PAL_TEST_INFO for both the\r
- /// phase one and phase two processor tests\r
- /// depending on which information the caller\r
- /// is requesting. PAL interprets these bits\r
- /// as input parameters on two occasions. The\r
- /// first time is when SAL passes control back\r
- /// to PAL after the firmware recovery check.\r
- /// The second time is when a call to\r
- /// PAL_TEST_PROC is made. When PAL interprets\r
- /// these bits it will only interpret\r
- /// implemented test_control bits and will\r
- /// ignore the values located in the\r
- /// unimplemented test_control bits. PAL\r
- /// interprets the implemented bits such that\r
- /// if a bit contains a zero, this indicates\r
- /// to run the test. If a bit contains a one,\r
- /// this indicates to PAL to skip the test. If\r
- /// the cs bit indicates that control is not\r
- /// available, the test_control bits will be\r
- /// ignored or generate an illegal argument in\r
- /// procedure calls if the caller sets these\r
- /// bits.\r
+ UINT64 TestControl:47; ///< This is an ordered implementation-specific\r
+ ///< control word that allows the user control\r
+ ///< over the length and runtime of the\r
+ ///< processor self-tests. This control word is\r
+ ///< ordered from the longest running tests up\r
+ ///< to the shortest running tests with bit 0\r
+ ///< controlling the longest running test. PAL\r
+ ///< may not implement all 47-bits of the\r
+ ///< test_control word. PAL communicates if a\r
+ ///< bit provides control by placing a zero in\r
+ ///< that bit. If a bit provides no control,\r
+ ///< PAL will place a one in it. PAL will have\r
+ ///< two sets of test_control bits for the two\r
+ ///< phases of the processor self-test. PAL\r
+ ///< provides information about implemented\r
+ ///< test_control bits at the hand-off from PAL\r
+ ///< to SAL for the firmware recovery check.\r
+ ///< These test_control bits provide control\r
+ ///< for phase one of processor self-test. It\r
+ ///< also provides this information via the PAL\r
+ ///< procedure call PAL_TEST_INFO for both the\r
+ ///< phase one and phase two processor tests\r
+ ///< depending on which information the caller\r
+ ///< is requesting. PAL interprets these bits\r
+ ///< as input parameters on two occasions. The\r
+ ///< first time is when SAL passes control back\r
+ ///< to PAL after the firmware recovery check.\r
+ ///< The second time is when a call to\r
+ ///< PAL_TEST_PROC is made. When PAL interprets\r
+ ///< these bits it will only interpret\r
+ ///< implemented test_control bits and will\r
+ ///< ignore the values located in the\r
+ ///< unimplemented test_control bits. PAL\r
+ ///< interprets the implemented bits such that\r
+ ///< if a bit contains a zero, this indicates\r
+ ///< to run the test. If a bit contains a one,\r
+ ///< this indicates to PAL to skip the test. If\r
+ ///< the cs bit indicates that control is not\r
+ ///< available, the test_control bits will be\r
+ ///< ignored or generate an illegal argument in\r
+ ///< procedure calls if the caller sets these\r
+ ///< bits.\r
\r
- UINT64 ControlSupport:1; /// This bit defines if an implementation\r
- /// supports control of the PAL self-tests\r
- /// via the self-test control word. If\r
- /// this bit is 0, the implementation does\r
- /// not support control of the processor\r
- /// self-tests via the self-test control\r
- /// word. If this bit is 1, the\r
- /// implementation does support control of\r
- /// the processor self-tests via the\r
- /// self-test control word. If control is\r
- /// not supported, GR37 will be ignored at\r
- /// the hand-off between SAL and PAL after\r
- /// the firmware recovery check and the\r
- /// PAL procedures related to the\r
- /// processor self-tests may return\r
- /// illegal arguments if a user tries to\r
- /// use the self-test control features.\r
+ UINT64 ControlSupport:1; ///< This bit defines if an implementation\r
+ ///< supports control of the PAL self-tests\r
+ ///< via the self-test control word. If\r
+ ///< this bit is 0, the implementation does\r
+ ///< not support control of the processor\r
+ ///< self-tests via the self-test control\r
+ ///< word. If this bit is 1, the\r
+ ///< implementation does support control of\r
+ ///< the processor self-tests via the\r
+ ///< self-test control word. If control is\r
+ ///< not supported, GR37 will be ignored at\r
+ ///< the hand-off between SAL and PAL after\r
+ ///< the firmware recovery check and the\r
+ ///< PAL procedures related to the\r
+ ///< processor self-tests may return\r
+ ///< illegal arguments if a user tries to\r
+ ///< use the self-test control features.\r
UINT64 Reserved:16;\r
} PAL_SELF_TEST_CONTROL;\r
\r
typedef struct {\r
- UINT64 Attributes:8; /// Specifies the memory attributes that are\r
- /// allowed to be used with the memory buffer\r
- /// passed to this procedure. The attributes\r
- /// parameter is a vector where each bit\r
- /// represents one of the virtual memory\r
- /// attributes defined by the architecture.See\r
- /// MEMORY_AATRIBUTES. The caller is required\r
- /// to support the cacheable attribute for the\r
- /// memory buffer, otherwise an invalid\r
- /// argument will be returned.\r
+ UINT64 Attributes:8; ///< Specifies the memory attributes that are\r
+ ///< allowed to be used with the memory buffer\r
+ ///< passed to this procedure. The attributes\r
+ ///< parameter is a vector where each bit\r
+ ///< represents one of the virtual memory\r
+ ///< attributes defined by the architecture.See\r
+ ///< MEMORY_AATRIBUTES. The caller is required\r
+ ///< to support the cacheable attribute for the\r
+ ///< memory buffer, otherwise an invalid\r
+ ///< argument will be returned.\r
UINT64 Reserved:8;\r
- UINT64 TestControl:48; /// Is the self-test control word\r
- /// corresponding to the test_phase passed.\r
- /// This test_control directs the coverage and\r
- /// runtime of the processor self-tests\r
- /// specified by the test_phase input\r
- /// argument. Information on if this\r
- /// feature is implemented and the number of\r
- /// bits supported can be obtained by the\r
- /// PAL_TEST_INFO procedure call. If this\r
- /// feature is implemented by the processor,\r
- /// the caller can selectively skip parts of\r
- /// the processor self-test by setting\r
- /// test_control bits to a one. If a bit has a\r
- /// zero, this test will be run. The values in\r
- /// the unimplemented bits are ignored. If\r
- /// PAL_TEST_INFO indicated that the self-test\r
- /// control word is not implemented, this\r
- /// procedure will return with an invalid\r
- /// argument status if the caller sets any of\r
- /// the test_control bits. See\r
- /// PAL_SELF_TEST_CONTROL.\r
+ UINT64 TestControl:48; ///< Is the self-test control word\r
+ ///< corresponding to the test_phase passed.\r
+ ///< This test_control directs the coverage and\r
+ ///< runtime of the processor self-tests\r
+ ///< specified by the test_phase input\r
+ ///< argument. Information on if this\r
+ ///< feature is implemented and the number of\r
+ ///< bits supported can be obtained by the\r
+ ///< PAL_TEST_INFO procedure call. If this\r
+ ///< feature is implemented by the processor,\r
+ ///< the caller can selectively skip parts of\r
+ ///< the processor self-test by setting\r
+ ///< test_control bits to a one. If a bit has a\r
+ ///< zero, this test will be run. The values in\r
+ ///< the unimplemented bits are ignored. If\r
+ ///< PAL_TEST_INFO indicated that the self-test\r
+ ///< control word is not implemented, this\r
+ ///< procedure will return with an invalid\r
+ ///< argument status if the caller sets any of\r
+ ///< the test_control bits. See\r
+ ///< PAL_SELF_TEST_CONTROL.\r
} PAL_TEST_CONTROL;\r
\r
/**\r
#define PAL_TEST_PROC 258\r
\r
typedef struct {\r
- UINT32 NumberOfInterruptControllers; /// Number of interrupt\r
- /// controllers currently\r
- /// enabled on the system.\r
+ UINT32 NumberOfInterruptControllers; ///< Number of interrupt\r
+ ///< controllers currently\r
+ ///< enabled on the system.\r
\r
- UINT32 NumberOfProcessors; /// Number of processors currently\r
- /// enabled on the system.\r
+ UINT32 NumberOfProcessors; ///< Number of processors currently\r
+ ///< enabled on the system.\r
} PAL_PLATFORM_INFO;\r
\r
/**\r
#define PAL_SET_HW_POLICY 49\r
\r
typedef struct {\r
- UINT64 Mode:3; /// Bit2:0, Indicates the mode of operation for this\r
- /// procedure: 0 - Query mode 1 - Error inject mode\r
- /// (err_inj should also be specified) 2 - Cancel\r
- /// outstanding trigger. All other fields in\r
- /// PAL_MC_ERROR_TYPE_INFO,\r
- /// PAL_MC_ERROR_STRUCTURE_INFO and\r
- /// PAL_MC_ERROR_DATA_BUFFER are ignored. All other\r
- /// values are reserved.\r
-\r
- UINT64 ErrorInjection:3; /// Bit5:3, indicates the mode of error\r
- /// injection: 0 - Error inject only (no\r
- /// error consumption) 1 - Error inject\r
- /// and consume All other values are\r
- /// reserved.\r
-\r
- UINT64 ErrorSeverity:2; /// Bit7:6, indicates the severity desired\r
- /// for error injection/query. Definitions\r
- /// of the different error severity types\r
- /// 0 - Corrected error 1 - Recoverable\r
- /// error 2 - Fatal error 3 - Reserved\r
-\r
- UINT64 ErrorStructure:5; /// Bit12:8, Indicates the structure\r
- /// identification for error\r
- /// injection/query: 0 - Any structure\r
- /// (cannot be used during query mode).\r
- /// When selected, the structure type used\r
- /// for error injection is determined by\r
- /// PAL. 1 - Cache 2 - TLB 3 - Register\r
- /// file 4 - Bus/System interconnect 5-15\r
- /// - Reserved 16-31 - Processor\r
- /// specific error injection\r
- /// capabilities.ErrorDataBuffer is used\r
- /// to specify error types. Please refer\r
- /// to the processor specific\r
- /// documentation for additional details.\r
-\r
- UINT64 StructureHierarchy:3; /// Bit15:13, Indicates the structure\r
- /// hierarchy for error\r
- /// injection/query: 0 - Any level of\r
- /// hierarchy (cannot be used during\r
- /// query mode). When selected, the\r
- /// structure hierarchy used for error\r
- /// injection is determined by PAL. 1\r
- /// - Error structure hierarchy\r
- /// level-1 2 - Error structure\r
- /// hierarchy level-2 3 - Error\r
- /// structure hierarchy level-3 4 -\r
- /// Error structure hierarchy level-4\r
- /// All other values are reserved.\r
- /// Reserved 63:16 Reserved\r
+ UINT64 Mode:3; ///< Bit2:0, Indicates the mode of operation for this\r
+ ///< procedure: 0 - Query mode 1 - Error inject mode\r
+ ///< (err_inj should also be specified) 2 - Cancel\r
+ ///< outstanding trigger. All other fields in\r
+ ///< PAL_MC_ERROR_TYPE_INFO,\r
+ ///< PAL_MC_ERROR_STRUCTURE_INFO and\r
+ ///< PAL_MC_ERROR_DATA_BUFFER are ignored. All other\r
+ ///< values are reserved.\r
+\r
+ UINT64 ErrorInjection:3; ///< Bit5:3, indicates the mode of error\r
+ ///< injection: 0 - Error inject only (no\r
+ ///< error consumption) 1 - Error inject\r
+ ///< and consume All other values are\r
+ ///< reserved.\r
+\r
+ UINT64 ErrorSeverity:2; ///< Bit7:6, indicates the severity desired\r
+ ///< for error injection/query. Definitions\r
+ ///< of the different error severity types\r
+ ///< 0 - Corrected error 1 - Recoverable\r
+ ///< error 2 - Fatal error 3 - Reserved\r
+\r
+ UINT64 ErrorStructure:5; ///< Bit12:8, Indicates the structure\r
+ ///< identification for error\r
+ ///< injection/query: 0 - Any structure\r
+ ///< (cannot be used during query mode).\r
+ ///< When selected, the structure type used\r
+ ///< for error injection is determined by\r
+ ///< PAL. 1 - Cache 2 - TLB 3 - Register\r
+ ///< file 4 - Bus/System interconnect 5-15\r
+ ///< - Reserved 16-31 - Processor\r
+ ///< specific error injection\r
+ ///< capabilities.ErrorDataBuffer is used\r
+ ///< to specify error types. Please refer\r
+ ///< to the processor specific\r
+ ///< documentation for additional details.\r
+\r
+ UINT64 StructureHierarchy:3; ///< Bit15:13, Indicates the structure\r
+ ///< hierarchy for error\r
+ ///< injection/query: 0 - Any level of\r
+ ///< hierarchy (cannot be used during\r
+ ///< query mode). When selected, the\r
+ ///< structure hierarchy used for error\r
+ ///< injection is determined by PAL. 1\r
+ ///< - Error structure hierarchy\r
+ ///< level-1 2 - Error structure\r
+ ///< hierarchy level-2 3 - Error\r
+ ///< structure hierarchy level-3 4 -\r
+ ///< Error structure hierarchy level-4\r
+ ///< All other values are reserved.\r
+ ///< Reserved 63:16 Reserved\r
\r
UINT64 Reserved:48;\r
} PAL_MC_ERROR_TYPE_INFO;\r
\r
typedef struct {\r
- UINT64 StructInfoIsValid:1; /// Bit0 When 1, indicates that the\r
- /// structure information fields\r
- /// (c_t,cl_p,cl_id) are valid and\r
- /// should be used for error injection.\r
- /// When 0, the structure information\r
- /// fields are ignored, and the values\r
- /// of these fields used for error\r
- /// injection are\r
- /// implementation-specific.\r
-\r
- UINT64 CacheType:2; /// Bit2:1 Indicates which cache should be used\r
- /// for error injection: 0 - Reserved 1 -\r
- /// Instruction cache 2 - Data or unified cache\r
- /// 3 - Reserved\r
-\r
- UINT64 PortionOfCacheLine:3; /// Bit5:3 Indicates the portion of the\r
- /// cache line where the error should\r
- /// be injected: 0 - Reserved 1 - Tag\r
- /// 2 - Data 3 - mesi All other\r
- /// values are reserved.\r
-\r
- UINT64 Mechanism:3; /// Bit8:6 Indicates which mechanism is used to\r
- /// identify the cache line to be used for error\r
- /// injection: 0 - Reserved 1 - Virtual address\r
- /// provided in the inj_addr field of the buffer\r
- /// pointed to by err_data_buffer should be used\r
- /// to identify the cache line for error\r
- /// injection. 2 - Physical address provided in\r
- /// the inj_addr field of the buffer pointed to\r
- /// by err_data_buffershould be used to identify\r
- /// the cache line for error injection. 3 - way\r
- /// and index fields provided in err_data_buffer\r
- /// should be used to identify the cache line\r
- /// for error injection. All other values are\r
- /// reserved.\r
-\r
- UINT64 DataPoisonOfCacheLine:1; /// Bit9 When 1, indicates that a\r
- /// multiple bit, non-correctable\r
- /// error should be injected in the\r
- /// cache line specified by cl_id.\r
- /// If this injected error is not\r
- /// consumed, it may eventually\r
- /// cause a data-poisoning event\r
- /// resulting in a corrected error\r
- /// signal, when the associated\r
- /// cache line is cast out (implicit\r
- /// or explicit write-back of the\r
- /// cache line). The error severity\r
- /// specified by err_sev in\r
- /// err_type_info must be set to 0\r
- /// (corrected error) when this bit\r
- /// is set.\r
+ UINT64 StructInfoIsValid:1; ///< Bit0 When 1, indicates that the\r
+ ///< structure information fields\r
+ ///< (c_t,cl_p,cl_id) are valid and\r
+ ///< should be used for error injection.\r
+ ///< When 0, the structure information\r
+ ///< fields are ignored, and the values\r
+ ///< of these fields used for error\r
+ ///< injection are\r
+ ///< implementation-specific.\r
+\r
+ UINT64 CacheType:2; ///< Bit2:1 Indicates which cache should be used\r
+ ///< for error injection: 0 - Reserved 1 -\r
+ ///< Instruction cache 2 - Data or unified cache\r
+ ///< 3 - Reserved\r
+\r
+ UINT64 PortionOfCacheLine:3; ///< Bit5:3 Indicates the portion of the\r
+ ///< cache line where the error should\r
+ ///< be injected: 0 - Reserved 1 - Tag\r
+ ///< 2 - Data 3 - mesi All other\r
+ ///< values are reserved.\r
+\r
+ UINT64 Mechanism:3; ///< Bit8:6 Indicates which mechanism is used to\r
+ ///< identify the cache line to be used for error\r
+ ///< injection: 0 - Reserved 1 - Virtual address\r
+ ///< provided in the inj_addr field of the buffer\r
+ ///< pointed to by err_data_buffer should be used\r
+ ///< to identify the cache line for error\r
+ ///< injection. 2 - Physical address provided in\r
+ ///< the inj_addr field of the buffer pointed to\r
+ ///< by err_data_buffershould be used to identify\r
+ ///< the cache line for error injection. 3 - way\r
+ ///< and index fields provided in err_data_buffer\r
+ ///< should be used to identify the cache line\r
+ ///< for error injection. All other values are\r
+ ///< reserved.\r
+\r
+ UINT64 DataPoisonOfCacheLine:1; ///< Bit9 When 1, indicates that a\r
+ ///< multiple bit, non-correctable\r
+ ///< error should be injected in the\r
+ ///< cache line specified by cl_id.\r
+ ///< If this injected error is not\r
+ ///< consumed, it may eventually\r
+ ///< cause a data-poisoning event\r
+ ///< resulting in a corrected error\r
+ ///< signal, when the associated\r
+ ///< cache line is cast out (implicit\r
+ ///< or explicit write-back of the\r
+ ///< cache line). The error severity\r
+ ///< specified by err_sev in\r
+ ///< err_type_info must be set to 0\r
+ ///< (corrected error) when this bit\r
+ ///< is set.\r
\r
UINT64 Reserved1:22;\r
\r
- UINT64 TrigerInfoIsValid:1; /// Bit32 When 1, indicates that the\r
- /// trigger information fields (trigger,\r
- /// trigger_pl) are valid and should be\r
- /// used for error injection. When 0,\r
- /// the trigger information fields are\r
- /// ignored and error injection is\r
- /// performed immediately.\r
-\r
- UINT64 Triger:4; /// Bit36:33 Indicates the operation type to be\r
- /// used as the error trigger condition. The\r
- /// address corresponding to the trigger is\r
- /// specified in the trigger_addr field of the\r
- /// buffer pointed to by err_data_buffer: 0 -\r
- /// Instruction memory access. The trigger match\r
- /// conditions for this operation type are similar\r
- /// to the IBR address breakpoint match conditions\r
- /// 1 - Data memory access. The trigger match\r
- /// conditions for this operation type are similar\r
- /// to the DBR address breakpoint match conditions\r
- /// All other values are reserved.\r
-\r
- UINT64 PrivilegeOfTriger:3; /// Bit39:37 Indicates the privilege\r
- /// level of the context during which\r
- /// the error should be injected: 0 -\r
- /// privilege level 0 1 - privilege\r
- /// level 1 2 - privilege level 2 3 -\r
- /// privilege level 3 All other values\r
- /// are reserved. If the implementation\r
- /// does not support privilege level\r
- /// qualifier for triggers (i.e. if\r
- /// trigger_pl is 0 in the capabilities\r
- /// vector), this field is ignored and\r
- /// triggers can be taken at any\r
- /// privilege level.\r
+ UINT64 TrigerInfoIsValid:1; ///< Bit32 When 1, indicates that the\r
+ ///< trigger information fields (trigger,\r
+ ///< trigger_pl) are valid and should be\r
+ ///< used for error injection. When 0,\r
+ ///< the trigger information fields are\r
+ ///< ignored and error injection is\r
+ ///< performed immediately.\r
+\r
+ UINT64 Triger:4; ///< Bit36:33 Indicates the operation type to be\r
+ ///< used as the error trigger condition. The\r
+ ///< address corresponding to the trigger is\r
+ ///< specified in the trigger_addr field of the\r
+ ///< buffer pointed to by err_data_buffer: 0 -\r
+ ///< Instruction memory access. The trigger match\r
+ ///< conditions for this operation type are similar\r
+ ///< to the IBR address breakpoint match conditions\r
+ ///< 1 - Data memory access. The trigger match\r
+ ///< conditions for this operation type are similar\r
+ ///< to the DBR address breakpoint match conditions\r
+ ///< All other values are reserved.\r
+\r
+ UINT64 PrivilegeOfTriger:3; ///< Bit39:37 Indicates the privilege\r
+ ///< level of the context during which\r
+ ///< the error should be injected: 0 -\r
+ ///< privilege level 0 1 - privilege\r
+ ///< level 1 2 - privilege level 2 3 -\r
+ ///< privilege level 3 All other values\r
+ ///< are reserved. If the implementation\r
+ ///< does not support privilege level\r
+ ///< qualifier for triggers (i.e. if\r
+ ///< trigger_pl is 0 in the capabilities\r
+ ///< vector), this field is ignored and\r
+ ///< triggers can be taken at any\r
+ ///< privilege level.\r
\r
UINT64 Reserved2:24;\r
} PAL_MC_ERROR_STRUCT_INFO;\r
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