/** @file\r
Support for PCI 2.2 standard.\r
\r
- Copyright (c) 2006 - 2007, Intel Corporation \r
- All rights reserved. This program and the accompanying materials \r
- are licensed and made available under the terms and conditions of the BSD License \r
- which accompanies this distribution. The full text of the license may be found at \r
- http://opensource.org/licenses/bsd-license.php \r
+ This file includes the definitions in the following specifications,\r
+ PCI Local Bus Specification, 2.2\r
+ PCI-to-PCI Bridge Architecture Specification, Revision 1.2\r
+ PC Card Standard, 8.0\r
+ PCI Power Management Interface Specification, Revision 1.2\r
\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2014 - 2015, Hewlett-Packard Development Company, L.P.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
-#ifndef _PCI22_H\r
-#define _PCI22_H\r
-\r
-#define PCI_MAX_SEGMENT 0\r
+#ifndef _PCI22_H_\r
+#define _PCI22_H_\r
\r
#define PCI_MAX_BUS 255\r
-\r
#define PCI_MAX_DEVICE 31\r
#define PCI_MAX_FUNC 7\r
\r
-//\r
-// Command\r
-//\r
-#define PCI_VGA_PALETTE_SNOOP_DISABLED 0x20\r
+#pragma pack(1)\r
\r
-#pragma pack(push, 1)\r
+///\r
+/// Common header region in PCI Configuration Space\r
+/// Section 6.1, PCI Local Bus Specification, 2.2\r
+///\r
typedef struct {\r
- UINT16 VendorId;\r
- UINT16 DeviceId;\r
- UINT16 Command;\r
- UINT16 Status;\r
- UINT8 RevisionID;\r
- UINT8 ClassCode[3];\r
- UINT8 CacheLineSize;\r
- UINT8 LatencyTimer;\r
- UINT8 HeaderType;\r
- UINT8 BIST;\r
+ UINT16 VendorId;\r
+ UINT16 DeviceId;\r
+ UINT16 Command;\r
+ UINT16 Status;\r
+ UINT8 RevisionID;\r
+ UINT8 ClassCode[3];\r
+ UINT8 CacheLineSize;\r
+ UINT8 LatencyTimer;\r
+ UINT8 HeaderType;\r
+ UINT8 BIST;\r
} PCI_DEVICE_INDEPENDENT_REGION;\r
\r
+///\r
+/// PCI Device header region in PCI Configuration Space\r
+/// Section 6.1, PCI Local Bus Specification, 2.2\r
+///\r
typedef struct {\r
- UINT32 Bar[6];\r
- UINT32 CISPtr;\r
- UINT16 SubsystemVendorID;\r
- UINT16 SubsystemID;\r
- UINT32 ExpansionRomBar;\r
- UINT8 CapabilityPtr;\r
- UINT8 Reserved1[3];\r
- UINT32 Reserved2;\r
- UINT8 InterruptLine;\r
- UINT8 InterruptPin;\r
- UINT8 MinGnt;\r
- UINT8 MaxLat;\r
+ UINT32 Bar[6];\r
+ UINT32 CISPtr;\r
+ UINT16 SubsystemVendorID;\r
+ UINT16 SubsystemID;\r
+ UINT32 ExpansionRomBar;\r
+ UINT8 CapabilityPtr;\r
+ UINT8 Reserved1[3];\r
+ UINT32 Reserved2;\r
+ UINT8 InterruptLine;\r
+ UINT8 InterruptPin;\r
+ UINT8 MinGnt;\r
+ UINT8 MaxLat;\r
} PCI_DEVICE_HEADER_TYPE_REGION;\r
\r
+///\r
+/// PCI Device Configuration Space\r
+/// Section 6.1, PCI Local Bus Specification, 2.2\r
+///\r
typedef struct {\r
- PCI_DEVICE_INDEPENDENT_REGION Hdr;\r
- PCI_DEVICE_HEADER_TYPE_REGION Device;\r
+ PCI_DEVICE_INDEPENDENT_REGION Hdr;\r
+ PCI_DEVICE_HEADER_TYPE_REGION Device;\r
} PCI_TYPE00;\r
\r
+///\r
+/// PCI-PCI Bridge header region in PCI Configuration Space\r
+/// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2\r
+///\r
typedef struct {\r
- UINT32 Bar[2];\r
- UINT8 PrimaryBus;\r
- UINT8 SecondaryBus;\r
- UINT8 SubordinateBus;\r
- UINT8 SecondaryLatencyTimer;\r
- UINT8 IoBase;\r
- UINT8 IoLimit;\r
- UINT16 SecondaryStatus;\r
- UINT16 MemoryBase;\r
- UINT16 MemoryLimit;\r
- UINT16 PrefetchableMemoryBase;\r
- UINT16 PrefetchableMemoryLimit;\r
- UINT32 PrefetchableBaseUpper32;\r
- UINT32 PrefetchableLimitUpper32;\r
- UINT16 IoBaseUpper16;\r
- UINT16 IoLimitUpper16;\r
- UINT8 CapabilityPtr;\r
- UINT8 Reserved[3];\r
- UINT32 ExpansionRomBAR;\r
- UINT8 InterruptLine;\r
- UINT8 InterruptPin;\r
- UINT16 BridgeControl;\r
+ UINT32 Bar[2];\r
+ UINT8 PrimaryBus;\r
+ UINT8 SecondaryBus;\r
+ UINT8 SubordinateBus;\r
+ UINT8 SecondaryLatencyTimer;\r
+ UINT8 IoBase;\r
+ UINT8 IoLimit;\r
+ UINT16 SecondaryStatus;\r
+ UINT16 MemoryBase;\r
+ UINT16 MemoryLimit;\r
+ UINT16 PrefetchableMemoryBase;\r
+ UINT16 PrefetchableMemoryLimit;\r
+ UINT32 PrefetchableBaseUpper32;\r
+ UINT32 PrefetchableLimitUpper32;\r
+ UINT16 IoBaseUpper16;\r
+ UINT16 IoLimitUpper16;\r
+ UINT8 CapabilityPtr;\r
+ UINT8 Reserved[3];\r
+ UINT32 ExpansionRomBAR;\r
+ UINT8 InterruptLine;\r
+ UINT8 InterruptPin;\r
+ UINT16 BridgeControl;\r
} PCI_BRIDGE_CONTROL_REGISTER;\r
\r
+///\r
+/// PCI-to-PCI Bridge Configuration Space\r
+/// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2\r
+///\r
typedef struct {\r
- PCI_DEVICE_INDEPENDENT_REGION Hdr;\r
- PCI_BRIDGE_CONTROL_REGISTER Bridge;\r
+ PCI_DEVICE_INDEPENDENT_REGION Hdr;\r
+ PCI_BRIDGE_CONTROL_REGISTER Bridge;\r
} PCI_TYPE01;\r
\r
typedef union {\r
- PCI_TYPE00 Device;\r
- PCI_TYPE01 Bridge;\r
+ PCI_TYPE00 Device;\r
+ PCI_TYPE01 Bridge;\r
} PCI_TYPE_GENERIC;\r
\r
+///\r
+/// CardBus Controller Configuration Space,\r
+/// Section 4.5.1, PC Card Standard. 8.0\r
+///\r
typedef struct {\r
- UINT32 CardBusSocketReg; // Cardus Socket/ExCA Base\r
- // Address Register\r
- //\r
- UINT16 Reserved;\r
- UINT16 SecondaryStatus; // Secondary Status\r
- UINT8 PciBusNumber; // PCI Bus Number\r
- UINT8 CardBusBusNumber; // CardBus Bus Number\r
- UINT8 SubordinateBusNumber; // Subordinate Bus Number\r
- UINT8 CardBusLatencyTimer; // CardBus Latency Timer\r
- UINT32 MemoryBase0; // Memory Base Register 0\r
- UINT32 MemoryLimit0; // Memory Limit Register 0\r
- UINT32 MemoryBase1;\r
- UINT32 MemoryLimit1;\r
- UINT32 IoBase0;\r
- UINT32 IoLimit0; // I/O Base Register 0\r
- UINT32 IoBase1; // I/O Limit Register 0\r
- UINT32 IoLimit1;\r
- UINT8 InterruptLine; // Interrupt Line\r
- UINT8 InterruptPin; // Interrupt Pin\r
- UINT16 BridgeControl; // Bridge Control\r
+ UINT32 CardBusSocketReg; ///< Cardbus Socket/ExCA Base\r
+ UINT8 Cap_Ptr;\r
+ UINT8 Reserved;\r
+ UINT16 SecondaryStatus; ///< Secondary Status\r
+ UINT8 PciBusNumber; ///< PCI Bus Number\r
+ UINT8 CardBusBusNumber; ///< CardBus Bus Number\r
+ UINT8 SubordinateBusNumber; ///< Subordinate Bus Number\r
+ UINT8 CardBusLatencyTimer; ///< CardBus Latency Timer\r
+ UINT32 MemoryBase0; ///< Memory Base Register 0\r
+ UINT32 MemoryLimit0; ///< Memory Limit Register 0\r
+ UINT32 MemoryBase1;\r
+ UINT32 MemoryLimit1;\r
+ UINT32 IoBase0;\r
+ UINT32 IoLimit0; ///< I/O Base Register 0\r
+ UINT32 IoBase1; ///< I/O Limit Register 0\r
+ UINT32 IoLimit1;\r
+ UINT8 InterruptLine; ///< Interrupt Line\r
+ UINT8 InterruptPin; ///< Interrupt Pin\r
+ UINT16 BridgeControl; ///< Bridge Control\r
} PCI_CARDBUS_CONTROL_REGISTER;\r
\r
//\r
// Definitions of PCI class bytes and manipulation macros.\r
//\r
-#define PCI_CLASS_OLD 0x00\r
-#define PCI_CLASS_OLD_OTHER 0x00\r
-#define PCI_CLASS_OLD_VGA 0x01\r
-\r
-#define PCI_CLASS_MASS_STORAGE 0x01\r
-#define PCI_CLASS_MASS_STORAGE_SCSI 0x00\r
-#define PCI_CLASS_MASS_STORAGE_IDE 0x01 // obsolete\r
-#define PCI_CLASS_IDE 0x01\r
-#define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02\r
-#define PCI_CLASS_MASS_STORAGE_IPI 0x03\r
-#define PCI_CLASS_MASS_STORAGE_RAID 0x04\r
-#define PCI_CLASS_MASS_STORAGE_OTHER 0x80\r
-\r
-#define PCI_CLASS_NETWORK 0x02\r
-#define PCI_CLASS_NETWORK_ETHERNET 0x00\r
-#define PCI_CLASS_ETHERNET 0x00 // obsolete\r
-#define PCI_CLASS_NETWORK_TOKENRING 0x01\r
-#define PCI_CLASS_NETWORK_FDDI 0x02\r
-#define PCI_CLASS_NETWORK_ATM 0x03\r
-#define PCI_CLASS_NETWORK_ISDN 0x04\r
-#define PCI_CLASS_NETWORK_OTHER 0x80\r
-\r
-#define PCI_CLASS_DISPLAY 0x03\r
-#define PCI_CLASS_DISPLAY_CTRL 0x03 // obsolete\r
-#define PCI_CLASS_DISPLAY_VGA 0x00\r
-#define PCI_CLASS_VGA 0x00 // obsolete\r
-#define PCI_CLASS_DISPLAY_XGA 0x01\r
-#define PCI_CLASS_DISPLAY_3D 0x02\r
-#define PCI_CLASS_DISPLAY_OTHER 0x80\r
-#define PCI_CLASS_DISPLAY_GFX 0x80\r
-#define PCI_CLASS_GFX 0x80 // obsolete\r
-#define PCI_CLASS_BRIDGE 0x06\r
-#define PCI_CLASS_BRIDGE_HOST 0x00\r
-#define PCI_CLASS_BRIDGE_ISA 0x01\r
-#define PCI_CLASS_ISA 0x01 // obsolete\r
-#define PCI_CLASS_BRIDGE_EISA 0x02\r
-#define PCI_CLASS_BRIDGE_MCA 0x03\r
-#define PCI_CLASS_BRIDGE_P2P 0x04\r
-#define PCI_CLASS_BRIDGE_PCMCIA 0x05\r
-#define PCI_CLASS_BRIDGE_NUBUS 0x06\r
-#define PCI_CLASS_BRIDGE_CARDBUS 0x07\r
-#define PCI_CLASS_BRIDGE_RACEWAY 0x08\r
-#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80\r
-#define PCI_CLASS_ISA_POSITIVE_DECODE 0x80 // obsolete\r
-\r
-#define PCI_CLASS_SCC 0x07 // Simple communications controllers \r
-#define PCI_SUBCLASS_SERIAL 0x00\r
-#define PCI_IF_GENERIC_XT 0x00\r
-#define PCI_IF_16450 0x01\r
-#define PCI_IF_16550 0x02\r
-#define PCI_IF_16650 0x03\r
-#define PCI_IF_16750 0x04\r
-#define PCI_IF_16850 0x05\r
-#define PCI_IF_16950 0x06\r
-#define PCI_SUBCLASS_PARALLEL 0x01\r
-#define PCI_IF_PARALLEL_PORT 0x00\r
-#define PCI_IF_BI_DIR_PARALLEL_PORT 0x01\r
-#define PCI_IF_ECP_PARALLEL_PORT 0x02\r
-#define PCI_IF_1284_CONTROLLER 0x03\r
-#define PCI_IF_1284_DEVICE 0xFE\r
-#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02\r
-#define PCI_SUBCLASS_MODEM 0x03\r
-#define PCI_IF_GENERIC_MODEM 0x00\r
-#define PCI_IF_16450_MODEM 0x01\r
-#define PCI_IF_16550_MODEM 0x02\r
-#define PCI_IF_16650_MODEM 0x03\r
-#define PCI_IF_16750_MODEM 0x04\r
-#define PCI_SUBCLASS_OTHER 0x80\r
-\r
-#define PCI_CLASS_SYSTEM_PERIPHERAL 0x08\r
-#define PCI_SUBCLASS_PIC 0x00\r
-#define PCI_IF_8259_PIC 0x00\r
-#define PCI_IF_ISA_PIC 0x01\r
-#define PCI_IF_EISA_PIC 0x02\r
-#define PCI_IF_APIC_CONTROLLER 0x10 // I/O APIC interrupt controller , 32 bye none-prefectable memory. \r
-#define PCI_IF_APIC_CONTROLLER2 0x20 \r
-#define PCI_SUBCLASS_TIMER 0x02\r
-#define PCI_IF_8254_TIMER 0x00\r
-#define PCI_IF_ISA_TIMER 0x01\r
-#define PCI_EISA_TIMER 0x02\r
-#define PCI_SUBCLASS_RTC 0x03\r
-#define PCI_IF_GENERIC_RTC 0x00\r
-#define PCI_IF_ISA_RTC 0x00\r
-#define PCI_SUBCLASS_PNP_CONTROLLER 0x04 // HotPlug Controller\r
-\r
-#define PCI_CLASS_INPUT_DEVICE 0x09\r
-#define PCI_SUBCLASS_KEYBOARD 0x00\r
-#define PCI_SUBCLASS_PEN 0x01\r
-#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02\r
-#define PCI_SUBCLASS_SCAN_CONTROLLER 0x03\r
-#define PCI_SUBCLASS_GAMEPORT 0x04\r
-\r
-#define PCI_CLASS_DOCKING_STATION 0x0A\r
-\r
-#define PCI_CLASS_PROCESSOR 0x0B\r
-#define PCI_SUBCLASS_PROC_386 0x00\r
-#define PCI_SUBCLASS_PROC_486 0x01\r
-#define PCI_SUBCLASS_PROC_PENTIUM 0x02\r
-#define PCI_SUBCLASS_PROC_ALPHA 0x10\r
-#define PCI_SUBCLASS_PROC_POWERPC 0x20\r
-#define PCI_SUBCLASS_PROC_MIPS 0x30\r
-#define PCI_SUBCLASS_PROC_CO_PORC 0x40 // Co-Processor\r
-\r
-#define PCI_CLASS_SERIAL 0x0C\r
-#define PCI_CLASS_SERIAL_FIREWIRE 0x00\r
-#define PCI_CLASS_SERIAL_ACCESS_BUS 0x01\r
-#define PCI_CLASS_SERIAL_SSA 0x02\r
-#define PCI_CLASS_SERIAL_USB 0x03\r
-#define PCI_IF_EHCI 0x20\r
-#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04\r
-#define PCI_CLASS_SERIAL_SMB 0x05\r
-\r
-#define PCI_CLASS_WIRELESS 0x0D\r
-#define PCI_SUBCLASS_IRDA 0x00\r
-#define PCI_SUBCLASS_IR 0x01\r
-#define PCI_SUBCLASS_RF 0x02\r
-\r
-#define PCI_CLASS_INTELLIGENT_IO 0x0E\r
-\r
-#define PCI_CLASS_SATELLITE 0x0F\r
-#define PCI_SUBCLASS_TV 0x01\r
-#define PCI_SUBCLASS_AUDIO 0x02\r
-#define PCI_SUBCLASS_VOICE 0x03\r
-#define PCI_SUBCLASS_DATA 0x04\r
-\r
-#define PCI_SECURITY_CONTROLLER 0x10 // Encryption and decryption controller\r
-#define PCI_SUBCLASS_NET_COMPUT 0x00\r
-#define PCI_SUBCLASS_ENTERTAINMENT 0x10 \r
-\r
-#define PCI_CLASS_DPIO 0x11\r
-\r
-#define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))\r
-#define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))\r
-#define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))\r
-\r
-#define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)\r
-#define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 0)\r
-#define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 1)\r
-#define IS_PCI_GFX(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_GFX, 0)\r
-#define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)\r
-#define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)\r
-#define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)\r
-#define IS_PCI_SCSI(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI, 0)\r
-#define IS_PCI_RAID(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID, 0)\r
-#define IS_PCI_LPC(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA, 0)\r
-#define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 0)\r
-#define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 1)\r
-#define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)\r
-#define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)\r
-\r
-#define HEADER_TYPE_DEVICE 0x00\r
-#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01\r
-#define HEADER_TYPE_CARDBUS_BRIDGE 0x02\r
-\r
-#define HEADER_TYPE_MULTI_FUNCTION 0x80\r
-#define HEADER_LAYOUT_CODE 0x7f\r
-\r
-#define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))\r
-#define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))\r
-#define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)\r
-\r
-#define PCI_DEVICE_ROMBAR 0x30\r
-#define PCI_BRIDGE_ROMBAR 0x38\r
-\r
-#define PCI_MAX_BAR 0x0006\r
-#define PCI_MAX_CONFIG_OFFSET 0x0100\r
-\r
-#define PCI_VENDOR_ID_OFFSET 0x00\r
-#define PCI_DEVICE_ID_OFFSET 0x02\r
-#define PCI_COMMAND_OFFSET 0x04\r
-#define PCI_PRIMARY_STATUS_OFFSET 0x06\r
-#define PCI_REVISION_ID_OFFSET 0x08\r
-#define PCI_CLASSCODE_OFFSET 0x09\r
-#define PCI_CACHELINE_SIZE_OFFSET 0x0C\r
-#define PCI_LATENCY_TIMER_OFFSET 0x0D\r
-#define PCI_HEADER_TYPE_OFFSET 0x0E\r
-#define PCI_BIST_OFFSET 0x0F\r
-#define PCI_BASE_ADDRESSREG_OFFSET 0x10\r
-#define PCI_CARDBUS_CIS_OFFSET 0x28\r
-#define PCI_SVID_OFFSET 0x2C // SubSystem Vendor id\r
-#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C\r
-#define PCI_SID_OFFSET 0x2E // SubSystem ID\r
-#define PCI_SUBSYSTEM_ID_OFFSET 0x2E\r
-#define PCI_EXPANSION_ROM_BASE 0x30\r
-#define PCI_CAPBILITY_POINTER_OFFSET 0x34\r
-#define PCI_INT_LINE_OFFSET 0x3C // Interrupt Line Register\r
-#define PCI_INT_PIN_OFFSET 0x3D // Interrupt Pin Register\r
-#define PCI_MAXGNT_OFFSET 0x3E // Max Grant Register\r
-#define PCI_MAXLAT_OFFSET 0x3F // Max Latency Register\r
+#define PCI_CLASS_OLD 0x00\r
+#define PCI_CLASS_OLD_OTHER 0x00\r
+#define PCI_CLASS_OLD_VGA 0x01\r
+\r
+#define PCI_CLASS_MASS_STORAGE 0x01\r
+#define PCI_CLASS_MASS_STORAGE_SCSI 0x00\r
+#define PCI_CLASS_MASS_STORAGE_IDE 0x01\r
+#define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02\r
+#define PCI_CLASS_MASS_STORAGE_IPI 0x03\r
+#define PCI_CLASS_MASS_STORAGE_RAID 0x04\r
+#define PCI_CLASS_MASS_STORAGE_OTHER 0x80\r
+\r
+#define PCI_CLASS_NETWORK 0x02\r
+#define PCI_CLASS_NETWORK_ETHERNET 0x00\r
+#define PCI_CLASS_NETWORK_TOKENRING 0x01\r
+#define PCI_CLASS_NETWORK_FDDI 0x02\r
+#define PCI_CLASS_NETWORK_ATM 0x03\r
+#define PCI_CLASS_NETWORK_ISDN 0x04\r
+#define PCI_CLASS_NETWORK_OTHER 0x80\r
+\r
+#define PCI_CLASS_DISPLAY 0x03\r
+#define PCI_CLASS_DISPLAY_VGA 0x00\r
+#define PCI_IF_VGA_VGA 0x00\r
+#define PCI_IF_VGA_8514 0x01\r
+#define PCI_CLASS_DISPLAY_XGA 0x01\r
+#define PCI_CLASS_DISPLAY_3D 0x02\r
+#define PCI_CLASS_DISPLAY_OTHER 0x80\r
+\r
+#define PCI_CLASS_MEDIA 0x04\r
+#define PCI_CLASS_MEDIA_VIDEO 0x00\r
+#define PCI_CLASS_MEDIA_AUDIO 0x01\r
+#define PCI_CLASS_MEDIA_TELEPHONE 0x02\r
+#define PCI_CLASS_MEDIA_OTHER 0x80\r
+\r
+#define PCI_CLASS_MEMORY_CONTROLLER 0x05\r
+#define PCI_CLASS_MEMORY_RAM 0x00\r
+#define PCI_CLASS_MEMORY_FLASH 0x01\r
+#define PCI_CLASS_MEMORY_OTHER 0x80\r
+\r
+#define PCI_CLASS_BRIDGE 0x06\r
+#define PCI_CLASS_BRIDGE_HOST 0x00\r
+#define PCI_CLASS_BRIDGE_ISA 0x01\r
+#define PCI_CLASS_BRIDGE_EISA 0x02\r
+#define PCI_CLASS_BRIDGE_MCA 0x03\r
+#define PCI_CLASS_BRIDGE_P2P 0x04\r
+#define PCI_IF_BRIDGE_P2P 0x00\r
+#define PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01\r
+#define PCI_CLASS_BRIDGE_PCMCIA 0x05\r
+#define PCI_CLASS_BRIDGE_NUBUS 0x06\r
+#define PCI_CLASS_BRIDGE_CARDBUS 0x07\r
+#define PCI_CLASS_BRIDGE_RACEWAY 0x08\r
+#define PCI_CLASS_BRIDGE_OTHER 0x80\r
+#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80\r
+\r
+#define PCI_CLASS_SCC 0x07///< Simple communications controllers\r
+#define PCI_SUBCLASS_SERIAL 0x00\r
+#define PCI_IF_GENERIC_XT 0x00\r
+#define PCI_IF_16450 0x01\r
+#define PCI_IF_16550 0x02\r
+#define PCI_IF_16650 0x03\r
+#define PCI_IF_16750 0x04\r
+#define PCI_IF_16850 0x05\r
+#define PCI_IF_16950 0x06\r
+#define PCI_SUBCLASS_PARALLEL 0x01\r
+#define PCI_IF_PARALLEL_PORT 0x00\r
+#define PCI_IF_BI_DIR_PARALLEL_PORT 0x01\r
+#define PCI_IF_ECP_PARALLEL_PORT 0x02\r
+#define PCI_IF_1284_CONTROLLER 0x03\r
+#define PCI_IF_1284_DEVICE 0xFE\r
+#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02\r
+#define PCI_SUBCLASS_MODEM 0x03\r
+#define PCI_IF_GENERIC_MODEM 0x00\r
+#define PCI_IF_16450_MODEM 0x01\r
+#define PCI_IF_16550_MODEM 0x02\r
+#define PCI_IF_16650_MODEM 0x03\r
+#define PCI_IF_16750_MODEM 0x04\r
+#define PCI_SUBCLASS_SCC_OTHER 0x80\r
+\r
+#define PCI_CLASS_SYSTEM_PERIPHERAL 0x08\r
+#define PCI_SUBCLASS_PIC 0x00\r
+#define PCI_IF_8259_PIC 0x00\r
+#define PCI_IF_ISA_PIC 0x01\r
+#define PCI_IF_EISA_PIC 0x02\r
+#define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 byte none-prefetchable memory.\r
+#define PCI_IF_APIC_CONTROLLER2 0x20\r
+#define PCI_SUBCLASS_DMA 0x01\r
+#define PCI_IF_8237_DMA 0x00\r
+#define PCI_IF_ISA_DMA 0x01\r
+#define PCI_IF_EISA_DMA 0x02\r
+#define PCI_SUBCLASS_TIMER 0x02\r
+#define PCI_IF_8254_TIMER 0x00\r
+#define PCI_IF_ISA_TIMER 0x01\r
+#define PCI_IF_EISA_TIMER 0x02\r
+#define PCI_SUBCLASS_RTC 0x03\r
+#define PCI_IF_GENERIC_RTC 0x00\r
+#define PCI_IF_ISA_RTC 0x01\r
+#define PCI_SUBCLASS_PNP_CONTROLLER 0x04 ///< HotPlug Controller\r
+#define PCI_SUBCLASS_PERIPHERAL_OTHER 0x80\r
+\r
+#define PCI_CLASS_INPUT_DEVICE 0x09\r
+#define PCI_SUBCLASS_KEYBOARD 0x00\r
+#define PCI_SUBCLASS_PEN 0x01\r
+#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02\r
+#define PCI_SUBCLASS_SCAN_CONTROLLER 0x03\r
+#define PCI_SUBCLASS_GAMEPORT 0x04\r
+#define PCI_IF_GAMEPORT 0x00\r
+#define PCI_IF_GAMEPORT1 0x10\r
+#define PCI_SUBCLASS_INPUT_OTHER 0x80\r
+\r
+#define PCI_CLASS_DOCKING_STATION 0x0A\r
+#define PCI_SUBCLASS_DOCKING_GENERIC 0x00\r
+#define PCI_SUBCLASS_DOCKING_OTHER 0x80\r
+\r
+#define PCI_CLASS_PROCESSOR 0x0B\r
+#define PCI_SUBCLASS_PROC_386 0x00\r
+#define PCI_SUBCLASS_PROC_486 0x01\r
+#define PCI_SUBCLASS_PROC_PENTIUM 0x02\r
+#define PCI_SUBCLASS_PROC_ALPHA 0x10\r
+#define PCI_SUBCLASS_PROC_POWERPC 0x20\r
+#define PCI_SUBCLASS_PROC_MIPS 0x30\r
+#define PCI_SUBCLASS_PROC_CO_PORC 0x40 ///< Co-Processor\r
+\r
+#define PCI_CLASS_SERIAL 0x0C\r
+#define PCI_CLASS_SERIAL_FIREWIRE 0x00\r
+#define PCI_IF_1394 0x00\r
+#define PCI_IF_1394_OPEN_HCI 0x10\r
+#define PCI_CLASS_SERIAL_ACCESS_BUS 0x01\r
+#define PCI_CLASS_SERIAL_SSA 0x02\r
+#define PCI_CLASS_SERIAL_USB 0x03\r
+#define PCI_IF_UHCI 0x00\r
+#define PCI_IF_OHCI 0x10\r
+#define PCI_IF_USB_OTHER 0x80\r
+#define PCI_IF_USB_DEVICE 0xFE\r
+#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04\r
+#define PCI_CLASS_SERIAL_SMB 0x05\r
+\r
+#define PCI_CLASS_WIRELESS 0x0D\r
+#define PCI_SUBCLASS_IRDA 0x00\r
+#define PCI_SUBCLASS_IR 0x01\r
+#define PCI_SUBCLASS_RF 0x10\r
+#define PCI_SUBCLASS_WIRELESS_OTHER 0x80\r
+\r
+#define PCI_CLASS_INTELLIGENT_IO 0x0E\r
+\r
+#define PCI_CLASS_SATELLITE 0x0F\r
+#define PCI_SUBCLASS_TV 0x01\r
+#define PCI_SUBCLASS_AUDIO 0x02\r
+#define PCI_SUBCLASS_VOICE 0x03\r
+#define PCI_SUBCLASS_DATA 0x04\r
+\r
+#define PCI_SECURITY_CONTROLLER 0x10 ///< Encryption and decryption controller\r
+#define PCI_SUBCLASS_NET_COMPUT 0x00\r
+#define PCI_SUBCLASS_ENTERTAINMENT 0x10\r
+#define PCI_SUBCLASS_SECURITY_OTHER 0x80\r
+\r
+#define PCI_CLASS_DPIO 0x11\r
+#define PCI_SUBCLASS_DPIO 0x00\r
+#define PCI_SUBCLASS_DPIO_OTHER 0x80\r
+\r
+/**\r
+ Macro that checks whether the Base Class code of device matched.\r
+\r
+ @param _p Specified device.\r
+ @param c Base Class code needs matching.\r
+\r
+ @retval TRUE Base Class code matches the specified device.\r
+ @retval FALSE Base Class code doesn't match the specified device.\r
\r
-#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E\r
-#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E\r
+**/\r
+#define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))\r
+\r
+/**\r
+ Macro that checks whether the Base Class code and Sub-Class code of device matched.\r
+\r
+ @param _p Specified device.\r
+ @param c Base Class code needs matching.\r
+ @param s Sub-Class code needs matching.\r
+\r
+ @retval TRUE Base Class code and Sub-Class code match the specified device.\r
+ @retval FALSE Base Class code and Sub-Class code don't match the specified device.\r
+\r
+**/\r
+#define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))\r
+\r
+/**\r
+ Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched.\r
+\r
+ @param _p Specified device.\r
+ @param c Base Class code needs matching.\r
+ @param s Sub-Class code needs matching.\r
+ @param p Interface code needs matching.\r
+\r
+ @retval TRUE Base Class code, Sub-Class code and Interface code match the specified device.\r
+ @retval FALSE Base Class code, Sub-Class code and Interface code don't match the specified device.\r
+\r
+**/\r
+#define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))\r
+\r
+/**\r
+ Macro that checks whether device is a display controller.\r
+\r
+ @param _p Specified device.\r
+\r
+ @retval TRUE Device is a display controller.\r
+ @retval FALSE Device is not a display controller.\r
+\r
+**/\r
+#define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)\r
+\r
+/**\r
+ Macro that checks whether device is a VGA-compatible controller.\r
+\r
+ @param _p Specified device.\r
+\r
+ @retval TRUE Device is a VGA-compatible controller.\r
+ @retval FALSE Device is not a VGA-compatible controller.\r
+\r
+**/\r
+#define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA)\r
+\r
+/**\r
+ Macro that checks whether device is an 8514-compatible controller.\r
+\r
+ @param _p Specified device.\r
+\r
+ @retval TRUE Device is an 8514-compatible controller.\r
+ @retval FALSE Device is not an 8514-compatible controller.\r
+\r
+**/\r
+#define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514)\r
+\r
+/**\r
+ Macro that checks whether device is built before the Class Code field was defined.\r
+\r
+ @param _p Specified device.\r
+\r
+ @retval TRUE Device is an old device.\r
+ @retval FALSE Device is not an old device.\r
+\r
+**/\r
+#define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)\r
+\r
+/**\r
+ Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined.\r
+\r
+ @param _p Specified device.\r
+\r
+ @retval TRUE Device is an old VGA-compatible device.\r
+ @retval FALSE Device is not an old VGA-compatible device.\r
+\r
+**/\r
+#define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)\r
+\r
+/**\r
+ Macro that checks whether device is an IDE controller.\r
+\r
+ @param _p Specified device.\r
+\r
+ @retval TRUE Device is an IDE controller.\r
+ @retval FALSE Device is not an IDE controller.\r
+\r
+**/\r
+#define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)\r
+\r
+/**\r
+ Macro that checks whether device is a SCSI bus controller.\r
+\r
+ @param _p Specified device.\r
+\r
+ @retval TRUE Device is a SCSI bus controller.\r
+ @retval FALSE Device is not a SCSI bus controller.\r
+\r
+**/\r
+#define IS_PCI_SCSI(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI)\r
+\r
+/**\r
+ Macro that checks whether device is a RAID controller.\r
+\r
+ @param _p Specified device.\r
+\r
+ @retval TRUE Device is a RAID controller.\r
+ @retval FALSE Device is not a RAID controller.\r
+\r
+**/\r
+#define IS_PCI_RAID(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID)\r
+\r
+/**\r
+ Macro that checks whether device is an ISA bridge.\r
+\r
+ @param _p Specified device.\r
+\r
+ @retval TRUE Device is an ISA bridge.\r
+ @retval FALSE Device is not an ISA bridge.\r
+\r
+**/\r
+#define IS_PCI_LPC(_p) IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)\r
+\r
+/**\r
+ Macro that checks whether device is a PCI-to-PCI bridge.\r
+\r
+ @param _p Specified device.\r
+\r
+ @retval TRUE Device is a PCI-to-PCI bridge.\r
+ @retval FALSE Device is not a PCI-to-PCI bridge.\r
+\r
+**/\r
+#define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P)\r
+\r
+/**\r
+ Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge.\r
+\r
+ @param _p Specified device.\r
+\r
+ @retval TRUE Device is a Subtractive Decode PCI-to-PCI bridge.\r
+ @retval FALSE Device is not a Subtractive Decode PCI-to-PCI bridge.\r
+\r
+**/\r
+#define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)\r
+\r
+/**\r
+ Macro that checks whether device is a 16550-compatible serial controller.\r
+\r
+ @param _p Specified device.\r
+\r
+ @retval TRUE Device is a 16550-compatible serial controller.\r
+ @retval FALSE Device is not a 16550-compatible serial controller.\r
+\r
+**/\r
+#define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)\r
+\r
+/**\r
+ Macro that checks whether device is a Universal Serial Bus controller.\r
+\r
+ @param _p Specified device.\r
\r
+ @retval TRUE Device is a Universal Serial Bus controller.\r
+ @retval FALSE Device is not a Universal Serial Bus controller.\r
+\r
+**/\r
+#define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)\r
+\r
+//\r
+// the definition of Header Type\r
+//\r
+#define HEADER_TYPE_DEVICE 0x00\r
+#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01\r
+#define HEADER_TYPE_CARDBUS_BRIDGE 0x02\r
+#define HEADER_TYPE_MULTI_FUNCTION 0x80\r
+//\r
+// Mask of Header type\r
+//\r
+#define HEADER_LAYOUT_CODE 0x7f\r
+\r
+/**\r
+ Macro that checks whether device is a PCI-PCI bridge.\r
+\r
+ @param _p Specified device.\r
+\r
+ @retval TRUE Device is a PCI-PCI bridge.\r
+ @retval FALSE Device is not a PCI-PCI bridge.\r
+\r
+**/\r
+#define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))\r
+\r
+/**\r
+ Macro that checks whether device is a CardBus bridge.\r
+\r
+ @param _p Specified device.\r
+\r
+ @retval TRUE Device is a CardBus bridge.\r
+ @retval FALSE Device is not a CardBus bridge.\r
+\r
+**/\r
+#define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))\r
+\r
+/**\r
+ Macro that checks whether device is a multiple functions device.\r
+\r
+ @param _p Specified device.\r
+\r
+ @retval TRUE Device is a multiple functions device.\r
+ @retval FALSE Device is not a multiple functions device.\r
+\r
+**/\r
+#define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)\r
+\r
+///\r
+/// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecture Specification,\r
+///\r
+#define PCI_BRIDGE_ROMBAR 0x38\r
+\r
+#define PCI_MAX_BAR 0x0006\r
+#define PCI_MAX_CONFIG_OFFSET 0x0100\r
+\r
+#define PCI_VENDOR_ID_OFFSET 0x00\r
+#define PCI_DEVICE_ID_OFFSET 0x02\r
+#define PCI_COMMAND_OFFSET 0x04\r
+#define PCI_PRIMARY_STATUS_OFFSET 0x06\r
+#define PCI_REVISION_ID_OFFSET 0x08\r
+#define PCI_CLASSCODE_OFFSET 0x09\r
+#define PCI_CACHELINE_SIZE_OFFSET 0x0C\r
+#define PCI_LATENCY_TIMER_OFFSET 0x0D\r
+#define PCI_HEADER_TYPE_OFFSET 0x0E\r
+#define PCI_BIST_OFFSET 0x0F\r
+#define PCI_BASE_ADDRESSREG_OFFSET 0x10\r
+#define PCI_CARDBUS_CIS_OFFSET 0x28\r
+#define PCI_SVID_OFFSET 0x2C ///< SubSystem Vendor id\r
+#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C\r
+#define PCI_SID_OFFSET 0x2E ///< SubSystem ID\r
+#define PCI_SUBSYSTEM_ID_OFFSET 0x2E\r
+#define PCI_EXPANSION_ROM_BASE 0x30\r
+#define PCI_CAPBILITY_POINTER_OFFSET 0x34\r
+#define PCI_INT_LINE_OFFSET 0x3C ///< Interrupt Line Register\r
+#define PCI_INT_PIN_OFFSET 0x3D ///< Interrupt Pin Register\r
+#define PCI_MAXGNT_OFFSET 0x3E ///< Max Grant Register\r
+#define PCI_MAXLAT_OFFSET 0x3F ///< Max Latency Register\r
+\r
+//\r
+// defined in PCI-to-PCI Bridge Architecture Specification\r
+//\r
#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18\r
#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19\r
#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a\r
+#define PCI_BRIDGE_SECONDARY_LATENCY_TIMER_OFFSET 0x1b\r
+#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E\r
+#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E\r
\r
-//\r
-// Interrupt Line "Unknown" or "No connection" value defined for x86 based system\r
-//\r
-#define PCI_INT_LINE_UNKNOWN 0xFF \r
+///\r
+/// Interrupt Line "Unknown" or "No connection" value defined for x86 based system\r
+///\r
+#define PCI_INT_LINE_UNKNOWN 0xFF\r
\r
+///\r
+/// PCI Access Data Format\r
+///\r
typedef union {\r
struct {\r
- UINT32 Reg : 8;\r
- UINT32 Func : 3;\r
- UINT32 Dev : 5;\r
- UINT32 Bus : 8;\r
- UINT32 Reserved : 7;\r
- UINT32 Enable : 1;\r
+ UINT32 Reg : 8;\r
+ UINT32 Func : 3;\r
+ UINT32 Dev : 5;\r
+ UINT32 Bus : 8;\r
+ UINT32 Reserved : 7;\r
+ UINT32 Enable : 1;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_CONFIG_ACCESS_CF8;\r
\r
#pragma pack()\r
\r
-#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55\r
-#define PCI_DATA_STRUCTURE_SIGNATURE EFI_SIGNATURE_32 ('P', 'C', 'I', 'R')\r
-#define PCI_CODE_TYPE_PCAT_IMAGE 0x00\r
-#define PCI_CODE_TYPE_EFI_IMAGE 0x03\r
-#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001\r
-\r
-#define EFI_PCI_COMMAND_IO_SPACE 0x0001\r
-#define EFI_PCI_COMMAND_MEMORY_SPACE 0x0002\r
-#define EFI_PCI_COMMAND_BUS_MASTER 0x0004\r
-#define EFI_PCI_COMMAND_SPECIAL_CYCLE 0x0008\r
-#define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE 0x0010\r
-#define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP 0x0020\r
-#define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND 0x0040\r
-#define EFI_PCI_COMMAND_STEPPING_CONTROL 0x0080\r
-#define EFI_PCI_COMMAND_SERR 0x0100\r
-#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK 0x0200\r
-\r
-#define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE 0x0001\r
-#define EFI_PCI_BRIDGE_CONTROL_SERR 0x0002\r
-#define EFI_PCI_BRIDGE_CONTROL_ISA 0x0004\r
-#define EFI_PCI_BRIDGE_CONTROL_VGA 0x0008\r
-#define EFI_PCI_BRIDGE_CONTROL_VGA_16 0x0010\r
-#define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT 0x0020\r
-#define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS 0x0040\r
-#define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK 0x0080\r
-#define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER 0x0100\r
-#define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER 0x0200\r
-#define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS 0x0400\r
-#define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR 0x0800\r
+#define EFI_PCI_COMMAND_IO_SPACE BIT0 ///< 0x0001\r
+#define EFI_PCI_COMMAND_MEMORY_SPACE BIT1 ///< 0x0002\r
+#define EFI_PCI_COMMAND_BUS_MASTER BIT2 ///< 0x0004\r
+#define EFI_PCI_COMMAND_SPECIAL_CYCLE BIT3 ///< 0x0008\r
+#define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE BIT4 ///< 0x0010\r
+#define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP BIT5 ///< 0x0020\r
+#define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND BIT6 ///< 0x0040\r
+#define EFI_PCI_COMMAND_STEPPING_CONTROL BIT7 ///< 0x0080\r
+#define EFI_PCI_COMMAND_SERR BIT8 ///< 0x0100\r
+#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK BIT9 ///< 0x0200\r
+\r
+//\r
+// defined in PCI-to-PCI Bridge Architecture Specification\r
+//\r
+#define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE BIT0 ///< 0x0001\r
+#define EFI_PCI_BRIDGE_CONTROL_SERR BIT1 ///< 0x0002\r
+#define EFI_PCI_BRIDGE_CONTROL_ISA BIT2 ///< 0x0004\r
+#define EFI_PCI_BRIDGE_CONTROL_VGA BIT3 ///< 0x0008\r
+#define EFI_PCI_BRIDGE_CONTROL_VGA_16 BIT4 ///< 0x0010\r
+#define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT BIT5 ///< 0x0020\r
+#define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS BIT6 ///< 0x0040\r
+#define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK BIT7 ///< 0x0080\r
+#define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER BIT8 ///< 0x0100\r
+#define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER BIT9 ///< 0x0200\r
+#define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS BIT10 ///< 0x0400\r
+#define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR BIT11 ///< 0x0800\r
\r
//\r
-// Following are the PCI-CARDBUS bridge control bit\r
+// Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard\r
//\r
-#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE 0x0080\r
-#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE 0x0100\r
-#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE 0x0200\r
-#define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE 0x0400\r
+#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE BIT7 ///< 0x0080\r
+#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE BIT8 ///< 0x0100\r
+#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE BIT9 ///< 0x0200\r
+#define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE BIT10 ///< 0x0400\r
\r
//\r
// Following are the PCI status control bit\r
//\r
-#define EFI_PCI_STATUS_CAPABILITY 0x0010\r
-#define EFI_PCI_STATUS_66MZ_CAPABLE 0x0020\r
-#define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE 0x0080\r
-#define EFI_PCI_MASTER_DATA_PARITY_ERROR 0x0100\r
+#define EFI_PCI_STATUS_CAPABILITY BIT4 ///< 0x0010\r
+#define EFI_PCI_STATUS_66MZ_CAPABLE BIT5 ///< 0x0020\r
+#define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE BIT7 ///< 0x0080\r
+#define EFI_PCI_MASTER_DATA_PARITY_ERROR BIT8 ///< 0x0100\r
\r
-#define EFI_PCI_CAPABILITY_PTR 0x34\r
-#define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14\r
+///\r
+/// defined in PC Card Standard\r
+///\r
+#define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14\r
\r
#pragma pack(1)\r
-typedef struct {\r
- UINT16 Signature; // 0xaa55\r
- UINT8 Reserved[0x16];\r
- UINT16 PcirOffset;\r
-} PCI_EXPANSION_ROM_HEADER;\r
-\r
-typedef struct {\r
- UINT16 Signature; // 0xaa55\r
- UINT8 Size512;\r
- UINT8 InitEntryPoint[3];\r
- UINT8 Reserved[0x12];\r
- UINT16 PcirOffset;\r
-} EFI_LEGACY_EXPANSION_ROM_HEADER;\r
-\r
-typedef struct {\r
- UINT32 Signature; // "PCIR"\r
- UINT16 VendorId;\r
- UINT16 DeviceId;\r
- UINT16 Reserved0;\r
- UINT16 Length;\r
- UINT8 Revision;\r
- UINT8 ClassCode[3];\r
- UINT16 ImageLength;\r
- UINT16 CodeRevision;\r
- UINT8 CodeType;\r
- UINT8 Indicator;\r
- UINT16 Reserved1;\r
-} PCI_DATA_STRUCTURE;\r
-\r
//\r
// PCI Capability List IDs and records\r
//\r
-#define EFI_PCI_CAPABILITY_ID_PMI 0x01\r
-#define EFI_PCI_CAPABILITY_ID_AGP 0x02\r
-#define EFI_PCI_CAPABILITY_ID_VPD 0x03\r
-#define EFI_PCI_CAPABILITY_ID_SLOTID 0x04\r
-#define EFI_PCI_CAPABILITY_ID_MSI 0x05\r
-#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06\r
-#define EFI_PCI_CAPABILITY_ID_PCIX 0x07\r
-\r
+#define EFI_PCI_CAPABILITY_ID_PMI 0x01\r
+#define EFI_PCI_CAPABILITY_ID_AGP 0x02\r
+#define EFI_PCI_CAPABILITY_ID_VPD 0x03\r
+#define EFI_PCI_CAPABILITY_ID_SLOTID 0x04\r
+#define EFI_PCI_CAPABILITY_ID_MSI 0x05\r
+#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06\r
+#define EFI_PCI_CAPABILITY_ID_SHPC 0x0C\r
+\r
+///\r
+/// Capabilities List Header\r
+/// Section 6.7, PCI Local Bus Specification, 2.2\r
+///\r
typedef struct {\r
- UINT8 CapabilityID;\r
- UINT8 NextItemPtr;\r
+ UINT8 CapabilityID;\r
+ UINT8 NextItemPtr;\r
} EFI_PCI_CAPABILITY_HDR;\r
\r
-//\r
-// Capability EFI_PCI_CAPABILITY_ID_PMI\r
-//\r
+///\r
+/// PMC - Power Management Capabilities\r
+/// Section 3.2.3, PCI Power Management Interface Specification, Revision 1.2\r
+///\r
+typedef union {\r
+ struct {\r
+ UINT16 Version : 3;\r
+ UINT16 PmeClock : 1;\r
+ UINT16 Reserved : 1;\r
+ UINT16 DeviceSpecificInitialization : 1;\r
+ UINT16 AuxCurrent : 3;\r
+ UINT16 D1Support : 1;\r
+ UINT16 D2Support : 1;\r
+ UINT16 PmeSupport : 5;\r
+ } Bits;\r
+ UINT16 Data;\r
+} EFI_PCI_PMC;\r
+\r
+#define EFI_PCI_PMC_D3_COLD_MASK (BIT15)\r
+\r
+///\r
+/// PMCSR - Power Management Control/Status\r
+/// Section 3.2.4, PCI Power Management Interface Specification, Revision 1.2\r
+///\r
+typedef union {\r
+ struct {\r
+ UINT16 PowerState : 2;\r
+ UINT16 ReservedForPciExpress : 1;\r
+ UINT16 NoSoftReset : 1;\r
+ UINT16 Reserved : 4;\r
+ UINT16 PmeEnable : 1;\r
+ UINT16 DataSelect : 4;\r
+ UINT16 DataScale : 2;\r
+ UINT16 PmeStatus : 1;\r
+ } Bits;\r
+ UINT16 Data;\r
+} EFI_PCI_PMCSR;\r
+\r
+#define PCI_POWER_STATE_D0 0\r
+#define PCI_POWER_STATE_D1 1\r
+#define PCI_POWER_STATE_D2 2\r
+#define PCI_POWER_STATE_D3_HOT 3\r
+\r
+///\r
+/// PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions\r
+/// Section 3.2.5, PCI Power Management Interface Specification, Revision 1.2\r
+///\r
+typedef union {\r
+ struct {\r
+ UINT8 Reserved : 6;\r
+ UINT8 B2B3 : 1;\r
+ UINT8 BusPowerClockControl : 1;\r
+ } Bits;\r
+ UINT8 Uint8;\r
+} EFI_PCI_PMCSR_BSE;\r
+\r
+///\r
+/// Power Management Register Block Definition\r
+/// Section 3.2, PCI Power Management Interface Specification, Revision 1.2\r
+///\r
typedef struct {\r
- EFI_PCI_CAPABILITY_HDR Hdr;\r
- UINT16 PMC;\r
- UINT16 PMCSR;\r
- UINT8 BridgeExtention;\r
- UINT8 Data;\r
+ EFI_PCI_CAPABILITY_HDR Hdr;\r
+ EFI_PCI_PMC PMC;\r
+ EFI_PCI_PMCSR PMCSR;\r
+ EFI_PCI_PMCSR_BSE BridgeExtention;\r
+ UINT8 Data;\r
} EFI_PCI_CAPABILITY_PMI;\r
\r
-//\r
-// Capability EFI_PCI_CAPABILITY_ID_AGP\r
-//\r
+///\r
+/// A.G.P Capability\r
+/// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0\r
+///\r
typedef struct {\r
- EFI_PCI_CAPABILITY_HDR Hdr;\r
- UINT8 Rev;\r
- UINT8 Reserved;\r
- UINT32 Status;\r
- UINT32 Command;\r
+ EFI_PCI_CAPABILITY_HDR Hdr;\r
+ UINT8 Rev;\r
+ UINT8 Reserved;\r
+ UINT32 Status;\r
+ UINT32 Command;\r
} EFI_PCI_CAPABILITY_AGP;\r
\r
-//\r
-// Capability EFI_PCI_CAPABILITY_ID_VPD\r
-//\r
+///\r
+/// VPD Capability Structure\r
+/// Appendix I, PCI Local Bus Specification, 2.2\r
+///\r
typedef struct {\r
- EFI_PCI_CAPABILITY_HDR Hdr;\r
- UINT16 AddrReg;\r
- UINT32 DataReg;\r
+ EFI_PCI_CAPABILITY_HDR Hdr;\r
+ UINT16 AddrReg;\r
+ UINT32 DataReg;\r
} EFI_PCI_CAPABILITY_VPD;\r
\r
-//\r
-// Capability EFI_PCI_CAPABILITY_ID_SLOTID\r
-//\r
+///\r
+/// Slot Numbering Capabilities Register\r
+/// Section 3.2.6, PCI-to-PCI Bridge Architecture Specification, Revision 1.2\r
+///\r
typedef struct {\r
- EFI_PCI_CAPABILITY_HDR Hdr;\r
- UINT8 ExpnsSlotReg;\r
- UINT8 ChassisNo;\r
+ EFI_PCI_CAPABILITY_HDR Hdr;\r
+ UINT8 ExpnsSlotReg;\r
+ UINT8 ChassisNo;\r
} EFI_PCI_CAPABILITY_SLOTID;\r
\r
-//\r
-// Capability EFI_PCI_CAPABILITY_ID_MSI\r
-//\r
+///\r
+/// Message Capability Structure for 32-bit Message Address\r
+/// Section 6.8.1, PCI Local Bus Specification, 2.2\r
+///\r
typedef struct {\r
- EFI_PCI_CAPABILITY_HDR Hdr;\r
- UINT16 MsgCtrlReg;\r
- UINT32 MsgAddrReg;\r
- UINT16 MsgDataReg;\r
+ EFI_PCI_CAPABILITY_HDR Hdr;\r
+ UINT16 MsgCtrlReg;\r
+ UINT32 MsgAddrReg;\r
+ UINT16 MsgDataReg;\r
} EFI_PCI_CAPABILITY_MSI32;\r
\r
+///\r
+/// Message Capability Structure for 64-bit Message Address\r
+/// Section 6.8.1, PCI Local Bus Specification, 2.2\r
+///\r
typedef struct {\r
- EFI_PCI_CAPABILITY_HDR Hdr;\r
- UINT16 MsgCtrlReg;\r
- UINT32 MsgAddrRegLsdw;\r
- UINT32 MsgAddrRegMsdw;\r
- UINT16 MsgDataReg;\r
+ EFI_PCI_CAPABILITY_HDR Hdr;\r
+ UINT16 MsgCtrlReg;\r
+ UINT32 MsgAddrRegLsdw;\r
+ UINT32 MsgAddrRegMsdw;\r
+ UINT16 MsgDataReg;\r
} EFI_PCI_CAPABILITY_MSI64;\r
\r
-//\r
-// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG\r
-//\r
+///\r
+/// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG,\r
+/// CompactPCI Hot Swap Specification PICMG 2.1, R1.0\r
+///\r
typedef struct {\r
- EFI_PCI_CAPABILITY_HDR Hdr;\r
- //\r
- // not finished - fields need to go here\r
- //\r
+ EFI_PCI_CAPABILITY_HDR Hdr;\r
+ ///\r
+ /// not finished - fields need to go here\r
+ ///\r
} EFI_PCI_CAPABILITY_HOTPLUG;\r
\r
-//\r
-// Capability EFI_PCI_CAPABILITY_ID_PCIX\r
-//\r
+#define PCI_BAR_IDX0 0x00\r
+#define PCI_BAR_IDX1 0x01\r
+#define PCI_BAR_IDX2 0x02\r
+#define PCI_BAR_IDX3 0x03\r
+#define PCI_BAR_IDX4 0x04\r
+#define PCI_BAR_IDX5 0x05\r
+\r
+///\r
+/// EFI PCI Option ROM definitions\r
+///\r
+#define EFI_ROOT_BRIDGE_LIST 'eprb'\r
+#define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1 ///< defined in UEFI Spec.\r
+\r
+#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55\r
+#define PCI_DATA_STRUCTURE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'R')\r
+#define PCI_CODE_TYPE_PCAT_IMAGE 0x00\r
+#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001 ///< defined in UEFI spec.\r
+\r
+///\r
+/// Standard PCI Expansion ROM Header\r
+/// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1\r
+///\r
typedef struct {\r
- EFI_PCI_CAPABILITY_HDR Hdr;\r
- UINT16 CommandReg;\r
- UINT32 StatusReg;\r
-} EFI_PCI_CAPABILITY_PCIX;\r
+ UINT16 Signature; ///< 0xaa55\r
+ UINT8 Reserved[0x16];\r
+ UINT16 PcirOffset;\r
+} PCI_EXPANSION_ROM_HEADER;\r
\r
+///\r
+/// Legacy ROM Header Extensions\r
+/// Section 6.3.3.1, PCI Local Bus Specification, 2.2\r
+///\r
typedef struct {\r
- EFI_PCI_CAPABILITY_HDR Hdr;\r
- UINT16 SecStatusReg;\r
- UINT32 StatusReg;\r
- UINT32 SplitTransCtrlRegUp;\r
- UINT32 SplitTransCtrlRegDn;\r
-} EFI_PCI_CAPABILITY_PCIX_BRDG;\r
-\r
-#define DEVICE_ID_NOCARE 0xFFFF\r
-\r
-#define PCI_ACPI_UNUSED 0\r
-#define PCI_BAR_NOCHANGE 0\r
-#define PCI_BAR_OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL\r
-#define PCI_BAR_EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL\r
-#define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL\r
-#define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL\r
-\r
-#define PCI_BAR_IDX0 0x00\r
-#define PCI_BAR_IDX1 0x01\r
-#define PCI_BAR_IDX2 0x02\r
-#define PCI_BAR_IDX3 0x03\r
-#define PCI_BAR_IDX4 0x04\r
-#define PCI_BAR_IDX5 0x05\r
-#define PCI_BAR_ALL 0xFF\r
-\r
-#pragma pack(pop)\r
+ UINT16 Signature; ///< 0xaa55\r
+ UINT8 Size512;\r
+ UINT8 InitEntryPoint[3];\r
+ UINT8 Reserved[0x12];\r
+ UINT16 PcirOffset;\r
+} EFI_LEGACY_EXPANSION_ROM_HEADER;\r
+\r
+///\r
+/// PCI Data Structure Format\r
+/// Section 6.3.1.2, PCI Local Bus Specification, 2.2\r
+///\r
+typedef struct {\r
+ UINT32 Signature; ///< "PCIR"\r
+ UINT16 VendorId;\r
+ UINT16 DeviceId;\r
+ UINT16 Reserved0;\r
+ UINT16 Length;\r
+ UINT8 Revision;\r
+ UINT8 ClassCode[3];\r
+ UINT16 ImageLength;\r
+ UINT16 CodeRevision;\r
+ UINT8 CodeType;\r
+ UINT8 Indicator;\r
+ UINT16 Reserved1;\r
+} PCI_DATA_STRUCTURE;\r
+\r
+///\r
+/// EFI PCI Expansion ROM Header\r
+/// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1\r
+///\r
+typedef struct {\r
+ UINT16 Signature; ///< 0xaa55\r
+ UINT16 InitializationSize;\r
+ UINT32 EfiSignature; ///< 0x0EF1\r
+ UINT16 EfiSubsystem;\r
+ UINT16 EfiMachineType;\r
+ UINT16 CompressionType;\r
+ UINT8 Reserved[8];\r
+ UINT16 EfiImageHeaderOffset;\r
+ UINT16 PcirOffset;\r
+} EFI_PCI_EXPANSION_ROM_HEADER;\r
+\r
+typedef union {\r
+ UINT8 *Raw;\r
+ PCI_EXPANSION_ROM_HEADER *Generic;\r
+ EFI_PCI_EXPANSION_ROM_HEADER *Efi;\r
+ EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;\r
+} EFI_PCI_ROM_HEADER;\r
+\r
+#pragma pack()\r
\r
#endif\r
projects / mirror_edk2.git / blobdiff