Revert all the #pramga(1) related patches to r6434, we need to review all the updates...

[mirror_edk2.git] / MdePkg / Include / IndustryStandard / Pci22.h

diff --git a/MdePkg/Include/IndustryStandard/Pci22.h b/MdePkg/Include/IndustryStandard/Pci22.h
index 88f39fbae7c03bb935333ff560cd9c5f54700ae0..d88b28f82557b696c92858d6a47dfb93aefaf57c 100644 (file)
--- a/MdePkg/Include/IndustryStandard/Pci22.h
+++ b/MdePkg/Include/IndustryStandard/Pci22.h
@@ -26,6 +26,7 @@
 #define PCI_MAX_FUNC    7\r
 \r
 \r
+#pragma pack(1)\r
 typedef struct {\r
   UINT16  VendorId;\r
   UINT16  DeviceId;\r
@@ -122,9 +123,9 @@ typedef struct {
   UINT16  BridgeControl;        ///< Bridge Control\r
 } PCI_CARDBUS_CONTROL_REGISTER;\r
 \r
-//\r
-// Definitions of PCI class bytes and manipulation macros.\r
-//\r
+///\r
+/// Definitions of PCI class bytes and manipulation macros.\r
+///\r
 #define PCI_CLASS_OLD                 0x00\r
 #define   PCI_CLASS_OLD_OTHER           0x00\r
 #define   PCI_CLASS_OLD_VGA             0x01\r
@@ -349,9 +350,9 @@ typedef struct {
 #define PCI_MAXGNT_OFFSET                           0x3E ///< Max Grant Register\r
 #define PCI_MAXLAT_OFFSET                           0x3F ///< Max Latency Register\r
 \r
-//\r
-// defined in PCI-to-PCI Bridge Architecture Specification\r
-//\r
+///\r
+/// defined in PCI-to-PCI Bridge Architecture Specification\r
+///\r
 #define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET      0x18   \r
 #define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET    0x19   \r
 #define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET  0x1a   \r
@@ -375,6 +376,8 @@ typedef union {
   UINT32  Uint32;\r
 } PCI_CONFIG_ACCESS_CF8;\r
 \r
+#pragma pack()\r
+\r
 #define EFI_PCI_COMMAND_IO_SPACE                        BIT0   ///< 0x0001\r
 #define EFI_PCI_COMMAND_MEMORY_SPACE                    BIT1   ///< 0x0002\r
 #define EFI_PCI_COMMAND_BUS_MASTER                      BIT2   ///< 0x0004\r
@@ -386,9 +389,9 @@ typedef union {
 #define EFI_PCI_COMMAND_SERR                            BIT8   ///< 0x0100\r
 #define EFI_PCI_COMMAND_FAST_BACK_TO_BACK               BIT9   ///< 0x0200\r
 \r
-//\r
-// defined in PCI-to-PCI Bridge Architecture Specification\r
-//\r
+///\r
+/// defined in PCI-to-PCI Bridge Architecture Specification\r
+///\r
 #define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE    BIT0   ///< 0x0001\r
 #define EFI_PCI_BRIDGE_CONTROL_SERR                     BIT1   ///< 0x0002\r
 #define EFI_PCI_BRIDGE_CONTROL_ISA                      BIT2   ///< 0x0004\r
@@ -402,9 +405,9 @@ typedef union {
 #define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS             BIT10  ///< 0x0400\r
 #define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR       BIT11  ///< 0x0800\r
 \r
-//\r
-// Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard\r
-//\r
+///\r
+/// Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard\r
+///\r
 #define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE           BIT7   ///< 0x0080\r
 #define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE       BIT8   ///< 0x0100\r
 #define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE       BIT9   ///< 0x0200\r
@@ -423,6 +426,7 @@ typedef union {
 ///\r
 #define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14\r
 \r
+#pragma pack(1)\r
 //\r
 // PCI Capability List IDs and records\r
 //\r
@@ -432,7 +436,6 @@ typedef union {
 #define EFI_PCI_CAPABILITY_ID_SLOTID  0x04\r
 #define EFI_PCI_CAPABILITY_ID_MSI     0x05\r
 #define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06\r
-\r
 typedef struct {\r
   UINT8 CapabilityID;\r
   UINT8 NextItemPtr;\r
@@ -593,4 +596,6 @@ typedef union {
   EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;\r
 } EFI_PCI_ROM_HEADER;\r
 \r
+#pragma pack()\r
+\r
 #endif\r