#ifndef __PCI30_H__\r
#define __PCI30_H__\r
\r
-\r
#include <IndustryStandard/Pci23.h>\r
\r
///\r
/// PCI_CLASS_MASS_STORAGE, Base Class 01h.\r
///\r
///@{\r
-#define PCI_CLASS_MASS_STORAGE_SATADPA 0x06\r
-#define PCI_IF_MASS_STORAGE_SATA 0x00\r
-#define PCI_IF_MASS_STORAGE_AHCI 0x01\r
+#define PCI_CLASS_MASS_STORAGE_SATADPA 0x06\r
+#define PCI_IF_MASS_STORAGE_SATA 0x00\r
+#define PCI_IF_MASS_STORAGE_AHCI 0x01\r
///@}\r
\r
///\r
/// PCI_CLASS_WIRELESS, Base Class 0Dh.\r
///\r
///@{\r
-#define PCI_SUBCLASS_ETHERNET_80211A 0x20\r
-#define PCI_SUBCLASS_ETHERNET_80211B 0x21\r
+#define PCI_SUBCLASS_ETHERNET_80211A 0x20\r
+#define PCI_SUBCLASS_ETHERNET_80211B 0x21\r
///@}\r
\r
/**\r
@retval FALSE Device is not a SATA controller.\r
\r
**/\r
-#define IS_PCI_SATADPA(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SATADPA)\r
+#define IS_PCI_SATADPA(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SATADPA)\r
\r
///\r
/// PCI Capability List IDs and records\r
/// Section 5.1.2, PCI Firmware Specification, Revision 3.0\r
///\r
typedef struct {\r
- UINT32 Signature; ///< "PCIR"\r
- UINT16 VendorId;\r
- UINT16 DeviceId;\r
- UINT16 DeviceListOffset;\r
- UINT16 Length;\r
- UINT8 Revision;\r
- UINT8 ClassCode[3];\r
- UINT16 ImageLength;\r
- UINT16 CodeRevision;\r
- UINT8 CodeType;\r
- UINT8 Indicator;\r
- UINT16 MaxRuntimeImageLength;\r
- UINT16 ConfigUtilityCodeHeaderOffset;\r
- UINT16 DMTFCLPEntryPointOffset;\r
+ UINT32 Signature; ///< "PCIR"\r
+ UINT16 VendorId;\r
+ UINT16 DeviceId;\r
+ UINT16 DeviceListOffset;\r
+ UINT16 Length;\r
+ UINT8 Revision;\r
+ UINT8 ClassCode[3];\r
+ UINT16 ImageLength;\r
+ UINT16 CodeRevision;\r
+ UINT8 CodeType;\r
+ UINT8 Indicator;\r
+ UINT16 MaxRuntimeImageLength;\r
+ UINT16 ConfigUtilityCodeHeaderOffset;\r
+ UINT16 DMTFCLPEntryPointOffset;\r
} PCI_3_0_DATA_STRUCTURE;\r
\r
#pragma pack()\r