/** @file\r
- Industry Standard Definitions of SMBIOS Table Specification v3.0.0.\r
+ Industry Standard Definitions of SMBIOS Table Specification v3.1.0.\r
\r
-Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
-(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>\r
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
+(C) Copyright 2015-2017 Hewlett Packard Enterprise Development LP<BR>\r
This program and the accompanying materials are licensed and made available under \r
the terms and conditions of the BSD License that accompanies this distribution. \r
The full text of the license may be found at\r
#define SMBIOS_TYPE_ADDITIONAL_INFORMATION 40\r
#define SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION 41\r
#define SMBIOS_TYPE_MANAGEMENT_CONTROLLER_HOST_INTERFACE 42\r
+#define SMBIOS_TYPE_TPM_DEVICE 43\r
\r
///\r
/// Inactive type is added from SMBIOS 2.2. Reference SMBIOS 2.6, chapter 3.3.43.\r
MBCE_SYSTEM_RESERVED SystemReserved;\r
} MISC_BIOS_CHARACTERISTICS_EXTENSION;\r
\r
+///\r
+/// Extended BIOS ROM size.\r
+///\r
+typedef struct {\r
+ UINT16 Size :14;\r
+ UINT16 Unit :2;\r
+} EXTENDED_BIOS_ROM_SIZE;\r
+\r
///\r
/// BIOS Information (Type 0).\r
///\r
UINT8 SystemBiosMinorRelease;\r
UINT8 EmbeddedControllerFirmwareMajorRelease;\r
UINT8 EmbeddedControllerFirmwareMinorRelease;\r
+ //\r
+ // Add for smbios 3.1.0\r
+ //\r
+ EXTENDED_BIOS_ROM_SIZE ExtendedBiosSize;\r
} SMBIOS_TABLE_TYPE0;\r
\r
///\r
MiscChassisBladeEnclosure = 0x1D,\r
MiscChassisTablet = 0x1E,\r
MiscChassisConvertible = 0x1F,\r
- MiscChassisDetachable = 0x20\r
+ MiscChassisDetachable = 0x20,\r
+ MiscChassisIoTGateway = 0x21,\r
+ MiscChassisEmbeddedPc = 0x22,\r
+ MiscChassisMiniPc = 0x23,\r
+ MiscChassisStickPc = 0x24\r
} MISC_CHASSIS_TYPE;\r
\r
///\r
UINT8 NumberofPowerCords;\r
UINT8 ContainedElementCount;\r
UINT8 ContainedElementRecordLength;\r
+ //\r
+ // Can have 0 to (ContainedElementCount * ContainedElementRecordLength) contained elements\r
+ //\r
CONTAINED_ELEMENT ContainedElements[1];\r
+ //\r
+ // Add for smbios 2.7\r
+ //\r
+ // Since ContainedElements has a variable number of entries, must not define SKUNumber in\r
+ // the structure. Need to reference it by starting at offset 0x15 and adding\r
+ // (ContainedElementCount * ContainedElementRecordLength) bytes.\r
+ //\r
+ // SMBIOS_TABLE_STRING SKUNumber;\r
} SMBIOS_TABLE_TYPE3;\r
\r
///\r
ProcessorFamilyIntelCoreSoloMobile = 0x2A,\r
ProcessorFamilyIntelAtom = 0x2B,\r
ProcessorFamilyIntelCoreM = 0x2C,\r
+ ProcessorFamilyIntelCorem3 = 0x2D,\r
+ ProcessorFamilyIntelCorem5 = 0x2E,\r
+ ProcessorFamilyIntelCorem7 = 0x2F,\r
ProcessorFamilyAlpha = 0x30,\r
ProcessorFamilyAlpha21064 = 0x31,\r
ProcessorFamilyAlpha21066 = 0x32,\r
ProcessorFamilyAmdAthlonX4QuadCore = 0x66,\r
ProcessorFamilyAmdOpteronX1000Series = 0x67,\r
ProcessorFamilyAmdOpteronX2000Series = 0x68,\r
+ ProcessorFamilyAmdOpteronASeries = 0x69,\r
+ ProcessorFamilyAmdOpteronX3000Series = 0x6A,\r
+ ProcessorFamilyAmdZen = 0x6B,\r
ProcessorFamilyHobbit = 0x70,\r
ProcessorFamilyCrusoeTM5000 = 0x78,\r
ProcessorFamilyCrusoeTM3000 = 0x79,\r
/// Processor Information2 - Processor Family2.\r
///\r
typedef enum {\r
+ ProcessorFamilyARMv7 = 0x0100,\r
+ ProcessorFamilyARMv8 = 0x0101,\r
ProcessorFamilySH3 = 0x0104,\r
ProcessorFamilySH4 = 0x0105,\r
ProcessorFamilyARM = 0x0118,\r
ProcessorUpgradeSocketLGA1150 = 0x2D,\r
ProcessorUpgradeSocketBGA1168 = 0x2E,\r
ProcessorUpgradeSocketBGA1234 = 0x2F,\r
- ProcessorUpgradeSocketBGA1364 = 0x30\r
+ ProcessorUpgradeSocketBGA1364 = 0x30,\r
+ ProcessorUpgradeSocketAM4 = 0x31,\r
+ ProcessorUpgradeSocketLGA1151 = 0x32,\r
+ ProcessorUpgradeSocketBGA1356 = 0x33,\r
+ ProcessorUpgradeSocketBGA1440 = 0x34,\r
+ ProcessorUpgradeSocketBGA1515 = 0x35,\r
+ ProcessorUpgradeSocketLGA3647_1 = 0x36,\r
+ ProcessorUpgradeSocketSP3 = 0x37,\r
+ ProcessorUpgradeSocketSP3r2 = 0x38\r
} PROCESSOR_UPGRADE;\r
\r
///\r
UINT8 ErrorCorrectionType; ///< The enumeration value from CACHE_ERROR_TYPE_DATA.\r
UINT8 SystemCacheType; ///< The enumeration value from CACHE_TYPE_DATA.\r
UINT8 Associativity; ///< The enumeration value from CACHE_ASSOCIATIVITY_DATA.\r
+ //\r
+ // Add for smbios 3.1.0\r
+ //\r
+ UINT32 MaximumCacheSize2;\r
+ UINT32 InstalledSize2;\r
} SMBIOS_TABLE_TYPE7;\r
\r
///\r
SlotTypeMxm30TypeB = 0x1E,\r
SlotTypePciExpressGen2Sff_8639 = 0x1F,\r
SlotTypePciExpressGen3Sff_8639 = 0x20,\r
+ SlotTypePciExpressMini52pinWithBSKO = 0x21, ///< PCI Express Mini 52-pin (CEM spec. 2.0) with bottom-side keep-outs.\r
+ SlotTypePciExpressMini52pinWithoutBSKO = 0x22, ///< PCI Express Mini 52-pin (CEM spec. 2.0) without bottom-side keep-outs.\r
+ SlotTypePciExpressMini76pin = 0x23, ///< PCI Express Mini 76-pin (CEM spec. 2.0) Corresponds to Display-Mini card.\r
SlotTypePC98C20 = 0xA0,\r
SlotTypePC98C24 = 0xA1,\r
SlotTypePC98E = 0xA2,\r
UINT8 DevFuncNum;\r
} SMBIOS_TABLE_TYPE41;\r
\r
+///\r
+/// Management Controller Host Interface - Interface Types.\r
+/// 00h - 3Fh: MCTP Host Interfaces\r
+///\r
+typedef enum{\r
+ MCHostInterfaceTypeNetworkHostInterface = 0x40,\r
+ MCHostInterfaceTypeOemDefined = 0xF0\r
+} MC_HOST_INTERFACE_TYPE;\r
+\r
+///\r
+/// Management Controller Host Interface - Protocol Types.\r
+///\r
+typedef enum{\r
+ MCHostInterfaceProtocolTypeIPMI = 0x02,\r
+ MCHostInterfaceProtocolTypeMCTP = 0x03,\r
+ MCHostInterfaceProtocolTypeRedfishOverIP = 0x04,\r
+ MCHostInterfaceProtocolTypeOemDefined = 0xF0\r
+} MC_HOST_INTERFACE_PROTOCOL_TYPE;\r
+\r
///\r
/// Management Controller Host Interface (Type 42).\r
///\r
///\r
typedef struct {\r
SMBIOS_STRUCTURE Hdr;\r
- UINT8 InterfaceType;\r
+ UINT8 InterfaceType; ///< The enumeration value from MC_HOST_INTERFACE_TYPE\r
UINT8 MCHostInterfaceData[1]; ///< This field has a minimum of four bytes\r
} SMBIOS_TABLE_TYPE42;\r
\r
+///\r
+/// TPM Device (Type 43).\r
+///\r
+typedef struct {\r
+ SMBIOS_STRUCTURE Hdr;\r
+ UINT8 VendorID[4];\r
+ UINT8 MajorSpecVersion;\r
+ UINT8 MinorSpecVersion;\r
+ UINT32 FirmwareVersion1;\r
+ UINT32 FirmwareVersion2;\r
+ SMBIOS_TABLE_STRING Description;\r
+ UINT64 Characteristics;\r
+ UINT32 OemDefined;\r
+} SMBIOS_TABLE_TYPE43;\r
+\r
///\r
/// Inactive (Type 126)\r
///\r
SMBIOS_TABLE_TYPE40 *Type40;\r
SMBIOS_TABLE_TYPE41 *Type41;\r
SMBIOS_TABLE_TYPE42 *Type42;\r
+ SMBIOS_TABLE_TYPE43 *Type43;\r
SMBIOS_TABLE_TYPE126 *Type126;\r
SMBIOS_TABLE_TYPE127 *Type127;\r
UINT8 *Raw;\r
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