/** @file\r
- Industry Standard Definitions of SMBIOS Table Specification v3.2.0.\r
+ Industry Standard Definitions of SMBIOS Table Specification v3.3.0.\r
\r
-Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
(C) Copyright 2015-2017 Hewlett Packard Enterprise Development LP<BR>\r
+(C) Copyright 2015 - 2019 Hewlett Packard Enterprise Development LP<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
#define SMBIOS_3_0_TABLE_MAX_LENGTH 0xFFFFFFFF\r
\r
//\r
-// SMBIOS type macros which is according to SMBIOS 2.7 specification.\r
+// SMBIOS type macros which is according to SMBIOS 3.3.0 specification.\r
//\r
#define SMBIOS_TYPE_BIOS_INFORMATION 0\r
#define SMBIOS_TYPE_SYSTEM_INFORMATION 1\r
#define SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION 41\r
#define SMBIOS_TYPE_MANAGEMENT_CONTROLLER_HOST_INTERFACE 42\r
#define SMBIOS_TYPE_TPM_DEVICE 43\r
+#define SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION 44\r
\r
///\r
/// Inactive type is added from SMBIOS 2.2. Reference SMBIOS 2.6, chapter 3.3.43.\r
ProcessorFamilyMII = 0x012E,\r
ProcessorFamilyWinChip = 0x0140,\r
ProcessorFamilyDSP = 0x015E,\r
- ProcessorFamilyVideoProcessor = 0x01F4\r
+ ProcessorFamilyVideoProcessor = 0x01F4,\r
+ ProcessorFamilyRiscvRV32 = 0x0200,\r
+ ProcessorFamilyRiscVRV64 = 0x0201,\r
+ ProcessorFamilyRiscVRV128 = 0x0202\r
} PROCESSOR_FAMILY2_DATA;\r
\r
///\r
UINT32 ProcessorReserved4 :2;\r
} PROCESSOR_FEATURE_FLAGS;\r
\r
+typedef struct {\r
+ UINT32 ProcessorReserved1 :1;\r
+ UINT32 ProcessorUnknown :1;\r
+ UINT32 Processor64BitCapble :1;\r
+ UINT32 ProcessorMultiCore :1;\r
+ UINT32 ProcessorHardwareThread :1;\r
+ UINT32 ProcessorExecuteProtection :1;\r
+ UINT32 ProcessorEnhancedVirtulization :1;\r
+ UINT32 ProcessorPowerPerformanceCtrl :1;\r
+ UINT32 Processor128bitCapble :1;\r
+ UINT32 ProcessorReserved2 :7;\r
+} PROCESSOR_CHARACTERISTIC_FLAGS;\r
+\r
typedef struct {\r
PROCESSOR_SIGNATURE Signature;\r
PROCESSOR_FEATURE_FLAGS FeatureFlags;\r
SlotTypePciExpressMini52pinWithBSKO = 0x21, ///< PCI Express Mini 52-pin (CEM spec. 2.0) with bottom-side keep-outs.\r
SlotTypePciExpressMini52pinWithoutBSKO = 0x22, ///< PCI Express Mini 52-pin (CEM spec. 2.0) without bottom-side keep-outs.\r
SlotTypePciExpressMini76pin = 0x23, ///< PCI Express Mini 76-pin (CEM spec. 2.0) Corresponds to Display-Mini card.\r
+ SlotTypeCXLFlexbus10 = 0x30,\r
SlotTypePC98C20 = 0xA0,\r
SlotTypePC98C24 = 0xA1,\r
SlotTypePC98E = 0xA2,\r
SlotTypePciExpressGen3X2 = 0xB3,\r
SlotTypePciExpressGen3X4 = 0xB4,\r
SlotTypePciExpressGen3X8 = 0xB5,\r
- SlotTypePciExpressGen3X16 = 0xB6\r
+ SlotTypePciExpressGen3X16 = 0xB6,\r
+ SlotTypePciExpressGen4 = 0xB8,\r
+ SlotTypePciExpressGen4X1 = 0xB9,\r
+ SlotTypePciExpressGen4X2 = 0xBA,\r
+ SlotTypePciExpressGen4X4 = 0xBB,\r
+ SlotTypePciExpressGen4X8 = 0xBC,\r
+ SlotTypePciExpressGen4X16 = 0xBD\r
} MISC_SLOT_TYPE;\r
\r
///\r
MemoryArrayLocationPc98C20AddonCard = 0xA0,\r
MemoryArrayLocationPc98C24AddonCard = 0xA1,\r
MemoryArrayLocationPc98EAddonCard = 0xA2,\r
- MemoryArrayLocationPc98LocalBusAddonCard = 0xA3\r
+ MemoryArrayLocationPc98LocalBusAddonCard = 0xA3,\r
+ MemoryArrayLocationCXLFlexbus10AddonCard = 0xA4\r
} MEMORY_ARRAY_LOCATION;\r
\r
///\r
MemoryFormFactorRimm = 0x0C,\r
MemoryFormFactorSodimm = 0x0D,\r
MemoryFormFactorSrimm = 0x0E,\r
- MemoryFormFactorFbDimm = 0x0F\r
+ MemoryFormFactorFbDimm = 0x0F,\r
+ MemoryFormFactorDie = 0x10\r
} MEMORY_FORM_FACTOR;\r
\r
///\r
MemoryTypeLpddr2 = 0x1C,\r
MemoryTypeLpddr3 = 0x1D,\r
MemoryTypeLpddr4 = 0x1E,\r
- MemoryTypeLogicalNonVolatileDevice = 0x1F\r
+ MemoryTypeLogicalNonVolatileDevice = 0x1F,\r
+ MemoryTypeHBM = 0x20,\r
+ MemoryTypeHBM2 = 0x21\r
} MEMORY_DEVICE_TYPE;\r
\r
///\r
UINT8 InterfaceTypeSpecificData[4]; ///< This field has a minimum of four bytes\r
} SMBIOS_TABLE_TYPE42;\r
\r
+\r
+///\r
+/// Processor Specific Block - Processor Architecture Type\r
+///\r
+typedef enum{\r
+ ProcessorSpecificBlockArchTypeReserved = 0x00,\r
+ ProcessorSpecificBlockArchTypeIa32 = 0x01,\r
+ ProcessorSpecificBlockArchTypeX64 = 0x02,\r
+ ProcessorSpecificBlockArchTypeItanium = 0x03,\r
+ ProcessorSpecificBlockArchTypeAarch32 = 0x04,\r
+ ProcessorSpecificBlockArchTypeAarch64 = 0x05,\r
+ ProcessorSpecificBlockArchTypeRiscVRV32 = 0x06,\r
+ ProcessorSpecificBlockArchTypeRiscVRV64 = 0x07,\r
+ ProcessorSpecificBlockArchTypeRiscVRV128 = 0x08\r
+} PROCESSOR_SPECIFIC_BLOCK_ARCH_TYPE;\r
+\r
+///\r
+/// Processor Specific Block is the standard container of processor-specific data.\r
+///\r
+typedef struct {\r
+ UINT8 Length;\r
+ UINT8 ProcessorArchType;\r
+ ///\r
+ /// Below followed by Processor-specific data\r
+ ///\r
+ ///\r
+} PROCESSOR_SPECIFIC_BLOCK;\r
+\r
+///\r
+/// Processor Additional Information(Type 44).\r
+///\r
+/// The information in this structure defines the processor additional information in case\r
+/// SMBIOS type 4 is not sufficient to describe processor characteristics.\r
+/// The SMBIOS type 44 structure has a reference handle field to link back to the related\r
+/// SMBIOS type 4 structure. There may be multiple SMBIOS type 44 structures linked to the\r
+/// same SMBIOS type 4 structure. For example, when cores are not identical in a processor,\r
+/// SMBIOS type 44 structures describe different core-specific information.\r
+///\r
+/// SMBIOS type 44 defines the standard header for the processor-specific block, while the\r
+/// contents of processor-specific data are maintained by processor\r
+/// architecture workgroups or vendors in separate documents.\r
+///\r
+typedef struct {\r
+ SMBIOS_STRUCTURE Hdr;\r
+ SMBIOS_HANDLE RefHandle; ///< This field refer to associated SMBIOS type 4\r
+ ///\r
+ /// Below followed by Processor-specific block\r
+ ///\r
+ PROCESSOR_SPECIFIC_BLOCK ProcessorSpecificBlock;\r
+} SMBIOS_TABLE_TYPE44;\r
+\r
///\r
/// TPM Device (Type 43).\r
///\r
SMBIOS_TABLE_TYPE41 *Type41;\r
SMBIOS_TABLE_TYPE42 *Type42;\r
SMBIOS_TABLE_TYPE43 *Type43;\r
+ SMBIOS_TABLE_TYPE44 *Type44;\r
SMBIOS_TABLE_TYPE126 *Type126;\r
SMBIOS_TABLE_TYPE127 *Type127;\r
UINT8 *Raw;\r
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