/** @file\r
Support for PCI 2.2 standard.\r
\r
- Copyright (c) 2006, Intel Corporation \r
+ Copyright (c) 2006 - 2007, Intel Corporation \r
All rights reserved. This program and the accompanying materials \r
are licensed and made available under the terms and conditions of the BSD License \r
which accompanies this distribution. The full text of the license may be found at \r
#define PCI_CLASS_BRIDGE_RACEWAY 0x08\r
#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80\r
#define PCI_CLASS_ISA_POSITIVE_DECODE 0x80 // obsolete\r
+\r
+#define PCI_CLASS_SCC 0x07 // Simple communications controllers \r
+#define PCI_SUBCLASS_SERIAL 0x00\r
+#define PCI_IF_GENERIC_XT 0x00\r
+#define PCI_IF_16450 0x01\r
+#define PCI_IF_16550 0x02\r
+#define PCI_IF_16650 0x03\r
+#define PCI_IF_16750 0x04\r
+#define PCI_IF_16850 0x05\r
+#define PCI_IF_16950 0x06\r
+#define PCI_SUBCLASS_PARALLEL 0x01\r
+#define PCI_IF_PARALLEL_PORT 0x00\r
+#define PCI_IF_BI_DIR_PARALLEL_PORT 0x01\r
+#define PCI_IF_ECP_PARALLEL_PORT 0x02\r
+#define PCI_IF_1284_CONTROLLER 0x03\r
+#define PCI_IF_1284_DEVICE 0xFE\r
+#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02\r
+#define PCI_SUBCLASS_MODEM 0x03\r
+#define PCI_IF_GENERIC_MODEM 0x00\r
+#define PCI_IF_16450_MODEM 0x01\r
+#define PCI_IF_16550_MODEM 0x02\r
+#define PCI_IF_16650_MODEM 0x03\r
+#define PCI_IF_16750_MODEM 0x04\r
+#define PCI_SUBCLASS_OTHER 0x80\r
+\r
+#define PCI_CLASS_SYSTEM_PERIPHERAL 0x08\r
+#define PCI_SUBCLASS_PIC 0x00\r
+#define PCI_IF_8259_PIC 0x00\r
+#define PCI_IF_ISA_PIC 0x01\r
+#define PCI_IF_EISA_PIC 0x02\r
+#define PCI_IF_APIC_CONTROLLER 0x10 // I/O APIC interrupt controller , 32 bye none-prefectable memory. \r
+#define PCI_IF_APIC_CONTROLLER2 0x20 \r
+#define PCI_SUBCLASS_TIMER 0x02\r
+#define PCI_IF_8254_TIMER 0x00\r
+#define PCI_IF_ISA_TIMER 0x01\r
+#define PCI_EISA_TIMER 0x02\r
+#define PCI_SUBCLASS_RTC 0x03\r
+#define PCI_IF_GENERIC_RTC 0x00\r
+#define PCI_IF_ISA_RTC 0x00\r
+#define PCI_SUBCLASS_PNP_CONTROLLER 0x04 // HotPlug Controller\r
+\r
+#define PCI_CLASS_INPUT_DEVICE 0x09\r
+#define PCI_SUBCLASS_KEYBOARD 0x00\r
+#define PCI_SUBCLASS_PEN 0x01\r
+#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02\r
+#define PCI_SUBCLASS_SCAN_CONTROLLER 0x03\r
+#define PCI_SUBCLASS_GAMEPORT 0x04\r
+\r
+#define PCI_CLASS_DOCKING_STATION 0x0A\r
+\r
+#define PCI_CLASS_PROCESSOR 0x0B\r
+#define PCI_SUBCLASS_PROC_386 0x00\r
+#define PCI_SUBCLASS_PROC_486 0x01\r
+#define PCI_SUBCLASS_PROC_PENTIUM 0x02\r
+#define PCI_SUBCLASS_PROC_ALPHA 0x10\r
+#define PCI_SUBCLASS_PROC_POWERPC 0x20\r
+#define PCI_SUBCLASS_PROC_MIPS 0x30\r
+#define PCI_SUBCLASS_PROC_CO_PORC 0x40 // Co-Processor\r
+\r
#define PCI_CLASS_SERIAL 0x0C\r
#define PCI_CLASS_SERIAL_FIREWIRE 0x00\r
#define PCI_CLASS_SERIAL_ACCESS_BUS 0x01\r
#define PCI_CLASS_SERIAL_SSA 0x02\r
#define PCI_CLASS_SERIAL_USB 0x03\r
+#define PCI_IF_EHCI 0x20\r
#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04\r
#define PCI_CLASS_SERIAL_SMB 0x05\r
\r
+#define PCI_CLASS_WIRELESS 0x0D\r
+#define PCI_SUBCLASS_IRDA 0x00\r
+#define PCI_SUBCLASS_IR 0x01\r
+#define PCI_SUBCLASS_RF 0x02\r
+\r
+#define PCI_CLASS_INTELLIGENT_IO 0x0E\r
+\r
+#define PCI_CLASS_SATELLITE 0x0F\r
+#define PCI_SUBCLASS_TV 0x01\r
+#define PCI_SUBCLASS_AUDIO 0x02\r
+#define PCI_SUBCLASS_VOICE 0x03\r
+#define PCI_SUBCLASS_DATA 0x04\r
+\r
+#define PCI_SECURITY_CONTROLLER 0x10 // Encryption and decryption controller\r
+#define PCI_SUBCLASS_NET_COMPUT 0x00\r
+#define PCI_SUBCLASS_ENTERTAINMENT 0x10 \r
+\r
+#define PCI_CLASS_DPIO 0x11\r
+\r
#define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))\r
#define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))\r
#define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))\r
#define IS_PCI_LPC(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA, 0)\r
#define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 0)\r
#define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 1)\r
+#define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)\r
#define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)\r
\r
#define HEADER_TYPE_DEVICE 0x00\r
#define PCI_DEVICE_ROMBAR 0x30\r
#define PCI_BRIDGE_ROMBAR 0x38\r
\r
-#define PCI_MAX_BAR 6\r
-#define PCI_MAX_CONFIG_OFFSET 0x100\r
-//\r
-// bugbug: this is supported in PCI spec v2.3\r
-//\r
-#define PCI_EXP_MAX_CONFIG_OFFSET 0x1000\r
+#define PCI_MAX_BAR 0x0006\r
+#define PCI_MAX_CONFIG_OFFSET 0x0100\r
\r
#define PCI_VENDOR_ID_OFFSET 0x00\r
#define PCI_DEVICE_ID_OFFSET 0x02\r
#define PCI_LATENCY_TIMER_OFFSET 0x0D\r
#define PCI_HEADER_TYPE_OFFSET 0x0E\r
#define PCI_BIST_OFFSET 0x0F\r
+#define PCI_BASE_ADDRESSREG_OFFSET 0x10\r
+#define PCI_CARDBUS_CIS_OFFSET 0x28\r
+#define PCI_SVID_OFFSET 0x2C // SubSystem Vendor id\r
+#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C\r
+#define PCI_SID_OFFSET 0x2E // SubSystem ID\r
+#define PCI_SUBSYSTEM_ID_OFFSET 0x2E\r
+#define PCI_EXPANSION_ROM_BASE 0x30\r
+#define PCI_CAPBILITY_POINTER_OFFSET 0x34\r
+#define PCI_INT_LINE_OFFSET 0x3C // Interrupt Line Register\r
+#define PCI_INT_PIN_OFFSET 0x3D // Interrupt Pin Register\r
+#define PCI_MAXGNT_OFFSET 0x3E // Max Grant Register\r
+#define PCI_MAXLAT_OFFSET 0x3F // Max Latency Register\r
\r
#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E\r
#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E\r
#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19\r
#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a\r
\r
-typedef struct {\r
- UINT8 Register;\r
- UINT8 Function;\r
- UINT8 Device;\r
- UINT8 Bus;\r
- UINT8 Reserved[4];\r
-} DEFIO_PCI_ADDR;\r
+//\r
+// Interrupt Line "Unknown" or "No connection" value defined for x86 based system\r
+//\r
+#define PCI_INT_LINE_UNKNOWN 0xFF \r
\r
typedef union {\r
struct {\r
\r
#pragma pack()\r
\r
-#define EFI_ROOT_BRIDGE_LIST 'eprb'\r
#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55\r
-#define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1\r
#define PCI_DATA_STRUCTURE_SIGNATURE EFI_SIGNATURE_32 ('P', 'C', 'I', 'R')\r
#define PCI_CODE_TYPE_PCAT_IMAGE 0x00\r
#define PCI_CODE_TYPE_EFI_IMAGE 0x03\r
UINT16 PcirOffset;\r
} PCI_EXPANSION_ROM_HEADER;\r
\r
-typedef struct {\r
- UINT16 Signature; // 0xaa55\r
- UINT16 InitializationSize;\r
- UINT32 EfiSignature; // 0x0EF1\r
- UINT16 EfiSubsystem;\r
- UINT16 EfiMachineType;\r
- UINT16 CompressionType;\r
- UINT8 Reserved[8];\r
- UINT16 EfiImageHeaderOffset;\r
- UINT16 PcirOffset;\r
-} EFI_PCI_EXPANSION_ROM_HEADER;\r
-\r
typedef struct {\r
UINT16 Signature; // 0xaa55\r
UINT8 Size512;\r
- UINT8 Reserved[15];\r
+ UINT8 InitEntryPoint[3];\r
+ UINT8 Reserved[0x12];\r
UINT16 PcirOffset;\r
} EFI_LEGACY_EXPANSION_ROM_HEADER;\r
\r
-typedef union {\r
- UINT8 *Raw;\r
- PCI_EXPANSION_ROM_HEADER *Generic;\r
- EFI_PCI_EXPANSION_ROM_HEADER *Efi;\r
- EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;\r
-} EFI_PCI_ROM_HEADER;\r
-\r
typedef struct {\r
UINT32 Signature; // "PCIR"\r
UINT16 VendorId;\r
#define EFI_PCI_CAPABILITY_ID_MSI 0x05\r
#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06\r
#define EFI_PCI_CAPABILITY_ID_PCIX 0x07\r
-//\r
-// bugbug: this ID is defined in PCI spec v2.3\r
-//\r
-#define EFI_PCI_CAPABILITY_ID_PCIEXP 0x10\r
\r
typedef struct {\r
UINT8 CapabilityID;\r
\r
#pragma pack(pop)\r
\r
+//\r
+// NOTE: The following header files are included here for\r
+// compatibility consideration.\r
+//\r
+#include "pci23.h"\r
+#include "pci30.h"\r
+#include "EfiPci.h"\r
+\r
#endif\r
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