\r
#endif // defined (MDE_CPU_IA32)\r
\r
-#if defined (MDE_CPU_IPF)\r
-\r
-///\r
-/// The Itanium architecture context buffer used by SetJump() and LongJump().\r
-///\r
-typedef struct {\r
- UINT64 F2[2];\r
- UINT64 F3[2];\r
- UINT64 F4[2];\r
- UINT64 F5[2];\r
- UINT64 F16[2];\r
- UINT64 F17[2];\r
- UINT64 F18[2];\r
- UINT64 F19[2];\r
- UINT64 F20[2];\r
- UINT64 F21[2];\r
- UINT64 F22[2];\r
- UINT64 F23[2];\r
- UINT64 F24[2];\r
- UINT64 F25[2];\r
- UINT64 F26[2];\r
- UINT64 F27[2];\r
- UINT64 F28[2];\r
- UINT64 F29[2];\r
- UINT64 F30[2];\r
- UINT64 F31[2];\r
- UINT64 R4;\r
- UINT64 R5;\r
- UINT64 R6;\r
- UINT64 R7;\r
- UINT64 SP;\r
- UINT64 BR0;\r
- UINT64 BR1;\r
- UINT64 BR2;\r
- UINT64 BR3;\r
- UINT64 BR4;\r
- UINT64 BR5;\r
- UINT64 InitialUNAT;\r
- UINT64 AfterSpillUNAT;\r
- UINT64 PFS;\r
- UINT64 BSP;\r
- UINT64 Predicates;\r
- UINT64 LoopCount;\r
- UINT64 FPSR;\r
-} BASE_LIBRARY_JUMP_BUFFER;\r
-\r
-#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 0x10\r
-\r
-#endif // defined (MDE_CPU_IPF)\r
-\r
#if defined (MDE_CPU_X64)\r
///\r
/// The x64 architecture context buffer used by SetJump() and LongJump().\r
IN UINT64 OrData\r
);\r
\r
+/**\r
+ Reads a bit field from a 32-bit value, counts and returns\r
+ the number of set bits.\r
+\r
+ Counts the number of set bits in the bit field specified by\r
+ StartBit and EndBit in Operand. The count is returned.\r
+\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+\r
+ @return The number of bits set between StartBit and EndBit.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+BitFieldCountOnes32 (\r
+ IN UINT32 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ );\r
+\r
+/**\r
+ Reads a bit field from a 64-bit value, counts and returns\r
+ the number of set bits.\r
+\r
+ Counts the number of set bits in the bit field specified by\r
+ StartBit and EndBit in Operand. The count is returned.\r
+\r
+ If StartBit is greater than 63, then ASSERT().\r
+ If EndBit is greater than 63, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..63.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..63.\r
+\r
+ @return The number of bits set between StartBit and EndBit.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+BitFieldCountOnes64 (\r
+ IN UINT64 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ );\r
+\r
//\r
// Base Library Checksum Functions\r
//\r
VOID\r
);\r
\r
-#if defined (MDE_CPU_IPF)\r
-\r
-/**\r
- Flush a range of cache lines in the cache coherency domain of the calling\r
- CPU.\r
-\r
- Flushes the cache lines specified by Address and Length. If Address is not aligned\r
- on a cache line boundary, then entire cache line containing Address is flushed.\r
- If Address + Length is not aligned on a cache line boundary, then the entire cache\r
- line containing Address + Length - 1 is flushed. This function may choose to flush\r
- the entire cache if that is more efficient than flushing the specified range. If\r
- Length is 0, the no cache lines are flushed. Address is returned.\r
- This function is only available on Itanium processors.\r
-\r
- If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
+#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)\r
+///\r
+/// IA32 and x64 Specific Functions.\r
+/// Byte packed structure for 16-bit Real Mode EFLAGS.\r
+///\r
+typedef union {\r
+ struct {\r
+ UINT32 CF:1; ///< Carry Flag.\r
+ UINT32 Reserved_0:1; ///< Reserved.\r
+ UINT32 PF:1; ///< Parity Flag.\r
+ UINT32 Reserved_1:1; ///< Reserved.\r
+ UINT32 AF:1; ///< Auxiliary Carry Flag.\r
+ UINT32 Reserved_2:1; ///< Reserved.\r
+ UINT32 ZF:1; ///< Zero Flag.\r
+ UINT32 SF:1; ///< Sign Flag.\r
+ UINT32 TF:1; ///< Trap Flag.\r
+ UINT32 IF:1; ///< Interrupt Enable Flag.\r
+ UINT32 DF:1; ///< Direction Flag.\r
+ UINT32 OF:1; ///< Overflow Flag.\r
+ UINT32 IOPL:2; ///< I/O Privilege Level.\r
+ UINT32 NT:1; ///< Nested Task.\r
+ UINT32 Reserved_3:1; ///< Reserved.\r
+ } Bits;\r
+ UINT16 Uint16;\r
+} IA32_FLAGS16;\r
\r
- @param Address The base address of the instruction lines to invalidate. If\r
- the CPU is in a physical addressing mode, then Address is a\r
- physical address. If the CPU is in a virtual addressing mode,\r
- then Address is a virtual address.\r
+///\r
+/// Byte packed structure for EFLAGS/RFLAGS.\r
+/// 32-bits on IA-32.\r
+/// 64-bits on x64. The upper 32-bits on x64 are reserved.\r
+///\r
+typedef union {\r
+ struct {\r
+ UINT32 CF:1; ///< Carry Flag.\r
+ UINT32 Reserved_0:1; ///< Reserved.\r
+ UINT32 PF:1; ///< Parity Flag.\r
+ UINT32 Reserved_1:1; ///< Reserved.\r
+ UINT32 AF:1; ///< Auxiliary Carry Flag.\r
+ UINT32 Reserved_2:1; ///< Reserved.\r
+ UINT32 ZF:1; ///< Zero Flag.\r
+ UINT32 SF:1; ///< Sign Flag.\r
+ UINT32 TF:1; ///< Trap Flag.\r
+ UINT32 IF:1; ///< Interrupt Enable Flag.\r
+ UINT32 DF:1; ///< Direction Flag.\r
+ UINT32 OF:1; ///< Overflow Flag.\r
+ UINT32 IOPL:2; ///< I/O Privilege Level.\r
+ UINT32 NT:1; ///< Nested Task.\r
+ UINT32 Reserved_3:1; ///< Reserved.\r
+ UINT32 RF:1; ///< Resume Flag.\r
+ UINT32 VM:1; ///< Virtual 8086 Mode.\r
+ UINT32 AC:1; ///< Alignment Check.\r
+ UINT32 VIF:1; ///< Virtual Interrupt Flag.\r
+ UINT32 VIP:1; ///< Virtual Interrupt Pending.\r
+ UINT32 ID:1; ///< ID Flag.\r
+ UINT32 Reserved_4:10; ///< Reserved.\r
+ } Bits;\r
+ UINTN UintN;\r
+} IA32_EFLAGS32;\r
\r
- @param Length The number of bytes to invalidate from the instruction cache.\r
+///\r
+/// Byte packed structure for Control Register 0 (CR0).\r
+/// 32-bits on IA-32.\r
+/// 64-bits on x64. The upper 32-bits on x64 are reserved.\r
+///\r
+typedef union {\r
+ struct {\r
+ UINT32 PE:1; ///< Protection Enable.\r
+ UINT32 MP:1; ///< Monitor Coprocessor.\r
+ UINT32 EM:1; ///< Emulation.\r
+ UINT32 TS:1; ///< Task Switched.\r
+ UINT32 ET:1; ///< Extension Type.\r
+ UINT32 NE:1; ///< Numeric Error.\r
+ UINT32 Reserved_0:10; ///< Reserved.\r
+ UINT32 WP:1; ///< Write Protect.\r
+ UINT32 Reserved_1:1; ///< Reserved.\r
+ UINT32 AM:1; ///< Alignment Mask.\r
+ UINT32 Reserved_2:10; ///< Reserved.\r
+ UINT32 NW:1; ///< Mot Write-through.\r
+ UINT32 CD:1; ///< Cache Disable.\r
+ UINT32 PG:1; ///< Paging.\r
+ } Bits;\r
+ UINTN UintN;\r
+} IA32_CR0;\r
\r
- @return Address.\r
+///\r
+/// Byte packed structure for Control Register 4 (CR4).\r
+/// 32-bits on IA-32.\r
+/// 64-bits on x64. The upper 32-bits on x64 are reserved.\r
+///\r
+typedef union {\r
+ struct {\r
+ UINT32 VME:1; ///< Virtual-8086 Mode Extensions.\r
+ UINT32 PVI:1; ///< Protected-Mode Virtual Interrupts.\r
+ UINT32 TSD:1; ///< Time Stamp Disable.\r
+ UINT32 DE:1; ///< Debugging Extensions.\r
+ UINT32 PSE:1; ///< Page Size Extensions.\r
+ UINT32 PAE:1; ///< Physical Address Extension.\r
+ UINT32 MCE:1; ///< Machine Check Enable.\r
+ UINT32 PGE:1; ///< Page Global Enable.\r
+ UINT32 PCE:1; ///< Performance Monitoring Counter\r
+ ///< Enable.\r
+ UINT32 OSFXSR:1; ///< Operating System Support for\r
+ ///< FXSAVE and FXRSTOR instructions\r
+ UINT32 OSXMMEXCPT:1; ///< Operating System Support for\r
+ ///< Unmasked SIMD Floating Point\r
+ ///< Exceptions.\r
+ UINT32 Reserved_0:2; ///< Reserved.\r
+ UINT32 VMXE:1; ///< VMX Enable\r
+ UINT32 Reserved_1:18; ///< Reserved.\r
+ } Bits;\r
+ UINTN UintN;\r
+} IA32_CR4;\r
\r
-**/\r
-VOID *\r
-EFIAPI\r
-AsmFlushCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
- );\r
+///\r
+/// Byte packed structure for a segment descriptor in a GDT/LDT.\r
+///\r
+typedef union {\r
+ struct {\r
+ UINT32 LimitLow:16;\r
+ UINT32 BaseLow:16;\r
+ UINT32 BaseMid:8;\r
+ UINT32 Type:4;\r
+ UINT32 S:1;\r
+ UINT32 DPL:2;\r
+ UINT32 P:1;\r
+ UINT32 LimitHigh:4;\r
+ UINT32 AVL:1;\r
+ UINT32 L:1;\r
+ UINT32 DB:1;\r
+ UINT32 G:1;\r
+ UINT32 BaseHigh:8;\r
+ } Bits;\r
+ UINT64 Uint64;\r
+} IA32_SEGMENT_DESCRIPTOR;\r
\r
+///\r
+/// Byte packed structure for an IDTR, GDTR, LDTR descriptor.\r
+///\r
+#pragma pack (1)\r
+typedef struct {\r
+ UINT16 Limit;\r
+ UINTN Base;\r
+} IA32_DESCRIPTOR;\r
+#pragma pack ()\r
\r
-/**\r
- Executes an FC instruction.\r
- Executes an FC instruction on the cache line specified by Address.\r
- The cache line size affected is at least 32-bytes (aligned on a 32-byte boundary).\r
- An implementation may flush a larger region. This function is only available on Itanium processors.\r
+#define IA32_IDT_GATE_TYPE_TASK 0x85\r
+#define IA32_IDT_GATE_TYPE_INTERRUPT_16 0x86\r
+#define IA32_IDT_GATE_TYPE_TRAP_16 0x87\r
+#define IA32_IDT_GATE_TYPE_INTERRUPT_32 0x8E\r
+#define IA32_IDT_GATE_TYPE_TRAP_32 0x8F\r
\r
- @param Address The Address of cache line to be flushed.\r
+#define IA32_GDT_TYPE_TSS 0x9\r
+#define IA32_GDT_ALIGNMENT 8\r
\r
- @return The address of FC instruction executed.\r
+#if defined (MDE_CPU_IA32)\r
+///\r
+/// Byte packed structure for an IA-32 Interrupt Gate Descriptor.\r
+///\r
+typedef union {\r
+ struct {\r
+ UINT32 OffsetLow:16; ///< Offset bits 15..0.\r
+ UINT32 Selector:16; ///< Selector.\r
+ UINT32 Reserved_0:8; ///< Reserved.\r
+ UINT32 GateType:8; ///< Gate Type. See #defines above.\r
+ UINT32 OffsetHigh:16; ///< Offset bits 31..16.\r
+ } Bits;\r
+ UINT64 Uint64;\r
+} IA32_IDT_GATE_DESCRIPTOR;\r
\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmFc (\r
- IN UINT64 Address\r
- );\r
-\r
-\r
-/**\r
- Executes an FC.I instruction.\r
- Executes an FC.I instruction on the cache line specified by Address.\r
- The cache line size affected is at least 32-bytes (aligned on a 32-byte boundary).\r
- An implementation may flush a larger region. This function is only available on Itanium processors.\r
-\r
- @param Address The Address of cache line to be flushed.\r
-\r
- @return The address of the FC.I instruction executed.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmFci (\r
- IN UINT64 Address\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of a Processor Identifier Register (CPUID).\r
-\r
- Reads and returns the current value of Processor Identifier Register specified by Index.\r
- The Index of largest implemented CPUID (One less than the number of implemented CPUID\r
- registers) is determined by CPUID [3] bits {7:0}.\r
- No parameter checking is performed on Index. If the Index value is beyond the\r
- implemented CPUID register range, a Reserved Register/Field fault may occur. The caller\r
- must either guarantee that Index is valid, or the caller must set up fault handlers to\r
- catch the faults. This function is only available on Itanium processors.\r
-\r
- @param Index The 8-bit Processor Identifier Register index to read.\r
-\r
- @return The current value of Processor Identifier Register specified by Index.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadCpuid (\r
- IN UINT8 Index\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of 64-bit Processor Status Register (PSR).\r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of PSR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadPsr (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Processor Status Register (PSR).\r
-\r
- No parameter checking is performed on Value. All bits of Value corresponding to\r
- reserved fields of PSR must be 0 or a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Value is valid, or the caller must set up\r
- fault handlers to catch the faults. This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to PSR.\r
-\r
- @return The 64-bit value written to the PSR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWritePsr (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of 64-bit Kernel Register #0 (KR0).\r
-\r
- Reads and returns the current value of KR0.\r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of KR0.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadKr0 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of 64-bit Kernel Register #1 (KR1).\r
-\r
- Reads and returns the current value of KR1.\r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of KR1.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadKr1 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of 64-bit Kernel Register #2 (KR2).\r
-\r
- Reads and returns the current value of KR2.\r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of KR2.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadKr2 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of 64-bit Kernel Register #3 (KR3).\r
-\r
- Reads and returns the current value of KR3.\r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of KR3.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadKr3 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of 64-bit Kernel Register #4 (KR4).\r
-\r
- Reads and returns the current value of KR4.\r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of KR4.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadKr4 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of 64-bit Kernel Register #5 (KR5).\r
-\r
- Reads and returns the current value of KR5.\r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of KR5.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadKr5 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of 64-bit Kernel Register #6 (KR6).\r
-\r
- Reads and returns the current value of KR6.\r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of KR6.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadKr6 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of 64-bit Kernel Register #7 (KR7).\r
-\r
- Reads and returns the current value of KR7.\r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of KR7.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadKr7 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Write the current value of 64-bit Kernel Register #0 (KR0).\r
-\r
- Writes the current value of KR0. The 64-bit value written to\r
- the KR0 is returned. This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to KR0.\r
-\r
- @return The 64-bit value written to the KR0.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteKr0 (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Write the current value of 64-bit Kernel Register #1 (KR1).\r
-\r
- Writes the current value of KR1. The 64-bit value written to\r
- the KR1 is returned. This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to KR1.\r
-\r
- @return The 64-bit value written to the KR1.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteKr1 (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Write the current value of 64-bit Kernel Register #2 (KR2).\r
-\r
- Writes the current value of KR2. The 64-bit value written to\r
- the KR2 is returned. This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to KR2.\r
-\r
- @return The 64-bit value written to the KR2.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteKr2 (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Write the current value of 64-bit Kernel Register #3 (KR3).\r
-\r
- Writes the current value of KR3. The 64-bit value written to\r
- the KR3 is returned. This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to KR3.\r
-\r
- @return The 64-bit value written to the KR3.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteKr3 (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Write the current value of 64-bit Kernel Register #4 (KR4).\r
-\r
- Writes the current value of KR4. The 64-bit value written to\r
- the KR4 is returned. This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to KR4.\r
-\r
- @return The 64-bit value written to the KR4.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteKr4 (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Write the current value of 64-bit Kernel Register #5 (KR5).\r
-\r
- Writes the current value of KR5. The 64-bit value written to\r
- the KR5 is returned. This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to KR5.\r
-\r
- @return The 64-bit value written to the KR5.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteKr5 (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Write the current value of 64-bit Kernel Register #6 (KR6).\r
-\r
- Writes the current value of KR6. The 64-bit value written to\r
- the KR6 is returned. This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to KR6.\r
-\r
- @return The 64-bit value written to the KR6.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteKr6 (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Write the current value of 64-bit Kernel Register #7 (KR7).\r
-\r
- Writes the current value of KR7. The 64-bit value written to\r
- the KR7 is returned. This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to KR7.\r
-\r
- @return The 64-bit value written to the KR7.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteKr7 (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Interval Timer Counter Register (ITC).\r
-\r
- Reads and returns the current value of ITC.\r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of ITC.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadItc (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Interval Timer Vector Register (ITV).\r
-\r
- Reads and returns the current value of ITV.\r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of ITV.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadItv (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Interval Timer Match Register (ITM).\r
-\r
- Reads and returns the current value of ITM.\r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of ITM.\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadItm (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Interval Timer Counter Register (ITC).\r
-\r
- Writes the current value of ITC. The 64-bit value written to the ITC is returned.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to ITC.\r
-\r
- @return The 64-bit value written to the ITC.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteItc (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Interval Timer Match Register (ITM).\r
-\r
- Writes the current value of ITM. The 64-bit value written to the ITM is returned.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to ITM.\r
-\r
- @return The 64-bit value written to the ITM.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteItm (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Interval Timer Vector Register (ITV).\r
-\r
- Writes the current value of ITV. The 64-bit value written to the ITV is returned.\r
- No parameter checking is performed on Value. All bits of Value corresponding to\r
- reserved fields of ITV must be 0 or a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Value is valid, or the caller must set up\r
- fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to ITV.\r
-\r
- @return The 64-bit value written to the ITV.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteItv (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Default Control Register (DCR).\r
-\r
- Reads and returns the current value of DCR. This function is only available on Itanium processors.\r
-\r
- @return The current value of DCR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadDcr (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Interruption Vector Address Register (IVA).\r
-\r
- Reads and returns the current value of IVA. This function is only available on Itanium processors.\r
-\r
- @return The current value of IVA.\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadIva (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Page Table Address Register (PTA).\r
-\r
- Reads and returns the current value of PTA. This function is only available on Itanium processors.\r
-\r
- @return The current value of PTA.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadPta (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Default Control Register (DCR).\r
-\r
- Writes the current value of DCR. The 64-bit value written to the DCR is returned.\r
- No parameter checking is performed on Value. All bits of Value corresponding to\r
- reserved fields of DCR must be 0 or a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Value is valid, or the caller must set up\r
- fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to DCR.\r
-\r
- @return The 64-bit value written to the DCR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteDcr (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Interruption Vector Address Register (IVA).\r
-\r
- Writes the current value of IVA. The 64-bit value written to the IVA is returned.\r
- The size of vector table is 32 K bytes and is 32 K bytes aligned\r
- the low 15 bits of Value is ignored when written.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to IVA.\r
-\r
- @return The 64-bit value written to the IVA.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteIva (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Page Table Address Register (PTA).\r
-\r
- Writes the current value of PTA. The 64-bit value written to the PTA is returned.\r
- No parameter checking is performed on Value. All bits of Value corresponding to\r
- reserved fields of DCR must be 0 or a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Value is valid, or the caller must set up\r
- fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to PTA.\r
-\r
- @return The 64-bit value written to the PTA.\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWritePta (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Local Interrupt ID Register (LID).\r
-\r
- Reads and returns the current value of LID. This function is only available on Itanium processors.\r
-\r
- @return The current value of LID.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadLid (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of External Interrupt Vector Register (IVR).\r
-\r
- Reads and returns the current value of IVR. This function is only available on Itanium processors.\r
-\r
- @return The current value of IVR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadIvr (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Task Priority Register (TPR).\r
-\r
- Reads and returns the current value of TPR. This function is only available on Itanium processors.\r
-\r
- @return The current value of TPR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadTpr (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of External Interrupt Request Register #0 (IRR0).\r
-\r
- Reads and returns the current value of IRR0. This function is only available on Itanium processors.\r
-\r
- @return The current value of IRR0.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadIrr0 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of External Interrupt Request Register #1 (IRR1).\r
-\r
- Reads and returns the current value of IRR1. This function is only available on Itanium processors.\r
-\r
- @return The current value of IRR1.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadIrr1 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of External Interrupt Request Register #2 (IRR2).\r
-\r
- Reads and returns the current value of IRR2. This function is only available on Itanium processors.\r
-\r
- @return The current value of IRR2.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadIrr2 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of External Interrupt Request Register #3 (IRR3).\r
-\r
- Reads and returns the current value of IRR3. This function is only available on Itanium processors.\r
-\r
- @return The current value of IRR3.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadIrr3 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Performance Monitor Vector Register (PMV).\r
-\r
- Reads and returns the current value of PMV. This function is only available on Itanium processors.\r
-\r
- @return The current value of PMV.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadPmv (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Corrected Machine Check Vector Register (CMCV).\r
-\r
- Reads and returns the current value of CMCV. This function is only available on Itanium processors.\r
-\r
- @return The current value of CMCV.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadCmcv (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Local Redirection Register #0 (LRR0).\r
-\r
- Reads and returns the current value of LRR0. This function is only available on Itanium processors.\r
-\r
- @return The current value of LRR0.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadLrr0 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Local Redirection Register #1 (LRR1).\r
-\r
- Reads and returns the current value of LRR1. This function is only available on Itanium processors.\r
-\r
- @return The current value of LRR1.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadLrr1 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Page Local Interrupt ID Register (LID).\r
-\r
- Writes the current value of LID. The 64-bit value written to the LID is returned.\r
- No parameter checking is performed on Value. All bits of Value corresponding to\r
- reserved fields of LID must be 0 or a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Value is valid, or the caller must set up\r
- fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to LID.\r
-\r
- @return The 64-bit value written to the LID.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteLid (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Task Priority Register (TPR).\r
-\r
- Writes the current value of TPR. The 64-bit value written to the TPR is returned.\r
- No parameter checking is performed on Value. All bits of Value corresponding to\r
- reserved fields of TPR must be 0 or a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Value is valid, or the caller must set up\r
- fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to TPR.\r
-\r
- @return The 64-bit value written to the TPR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteTpr (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Performs a write operation on End OF External Interrupt Register (EOI).\r
-\r
- Writes a value of 0 to the EOI Register. This function is only available on Itanium processors.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-AsmWriteEoi (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Performance Monitor Vector Register (PMV).\r
-\r
- Writes the current value of PMV. The 64-bit value written to the PMV is returned.\r
- No parameter checking is performed on Value. All bits of Value corresponding\r
- to reserved fields of PMV must be 0 or a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Value is valid, or the caller must set up\r
- fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to PMV.\r
-\r
- @return The 64-bit value written to the PMV.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWritePmv (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Corrected Machine Check Vector Register (CMCV).\r
-\r
- Writes the current value of CMCV. The 64-bit value written to the CMCV is returned.\r
- No parameter checking is performed on Value. All bits of Value corresponding\r
- to reserved fields of CMCV must be 0 or a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Value is valid, or the caller must set up\r
- fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to CMCV.\r
-\r
- @return The 64-bit value written to the CMCV.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteCmcv (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Local Redirection Register #0 (LRR0).\r
-\r
- Writes the current value of LRR0. The 64-bit value written to the LRR0 is returned.\r
- No parameter checking is performed on Value. All bits of Value corresponding\r
- to reserved fields of LRR0 must be 0 or a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Value is valid, or the caller must set up\r
- fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to LRR0.\r
-\r
- @return The 64-bit value written to the LRR0.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteLrr0 (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Local Redirection Register #1 (LRR1).\r
-\r
- Writes the current value of LRR1. The 64-bit value written to the LRR1 is returned.\r
- No parameter checking is performed on Value. All bits of Value corresponding\r
- to reserved fields of LRR1 must be 0 or a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Value is valid, or the caller must\r
- set up fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to LRR1.\r
-\r
- @return The 64-bit value written to the LRR1.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteLrr1 (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Instruction Breakpoint Register (IBR).\r
-\r
- The Instruction Breakpoint Registers are used in pairs. The even numbered\r
- registers contain breakpoint addresses, and the odd numbered registers contain\r
- breakpoint mask conditions. At least four instruction registers pairs are implemented\r
- on all processor models. Implemented registers are contiguous starting with\r
- register 0. No parameter checking is performed on Index, and if the Index value\r
- is beyond the implemented IBR register range, a Reserved Register/Field fault may\r
- occur. The caller must either guarantee that Index is valid, or the caller must\r
- set up fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Index The 8-bit Instruction Breakpoint Register index to read.\r
-\r
- @return The current value of Instruction Breakpoint Register specified by Index.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadIbr (\r
- IN UINT8 Index\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Data Breakpoint Register (DBR).\r
-\r
- The Data Breakpoint Registers are used in pairs. The even numbered registers\r
- contain breakpoint addresses, and odd numbered registers contain breakpoint\r
- mask conditions. At least four data registers pairs are implemented on all processor\r
- models. Implemented registers are contiguous starting with register 0.\r
- No parameter checking is performed on Index. If the Index value is beyond\r
- the implemented DBR register range, a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Index is valid, or the caller must set up\r
- fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Index The 8-bit Data Breakpoint Register index to read.\r
-\r
- @return The current value of Data Breakpoint Register specified by Index.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadDbr (\r
- IN UINT8 Index\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Performance Monitor Configuration Register (PMC).\r
-\r
- All processor implementations provide at least four performance counters\r
- (PMC/PMD [4]...PMC/PMD [7] pairs), and four performance monitor counter overflow\r
- status registers (PMC [0]... PMC [3]). Processor implementations may provide\r
- additional implementation-dependent PMC and PMD to increase the number of\r
- 'generic' performance counters (PMC/PMD pairs). The remainder of PMC and PMD\r
- register set is implementation dependent. No parameter checking is performed\r
- on Index. If the Index value is beyond the implemented PMC register range,\r
- zero value will be returned.\r
- This function is only available on Itanium processors.\r
-\r
- @param Index The 8-bit Performance Monitor Configuration Register index to read.\r
-\r
- @return The current value of Performance Monitor Configuration Register\r
- specified by Index.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadPmc (\r
- IN UINT8 Index\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Performance Monitor Data Register (PMD).\r
-\r
- All processor implementations provide at least 4 performance counters\r
- (PMC/PMD [4]...PMC/PMD [7] pairs), and 4 performance monitor counter\r
- overflow status registers (PMC [0]... PMC [3]). Processor implementations may\r
- provide additional implementation-dependent PMC and PMD to increase the number\r
- of 'generic' performance counters (PMC/PMD pairs). The remainder of PMC and PMD\r
- register set is implementation dependent. No parameter checking is performed\r
- on Index. If the Index value is beyond the implemented PMD register range,\r
- zero value will be returned.\r
- This function is only available on Itanium processors.\r
-\r
- @param Index The 8-bit Performance Monitor Data Register index to read.\r
-\r
- @return The current value of Performance Monitor Data Register specified by Index.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadPmd (\r
- IN UINT8 Index\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Instruction Breakpoint Register (IBR).\r
-\r
- Writes current value of Instruction Breakpoint Register specified by Index.\r
- The Instruction Breakpoint Registers are used in pairs. The even numbered\r
- registers contain breakpoint addresses, and odd numbered registers contain\r
- breakpoint mask conditions. At least four instruction registers pairs are implemented\r
- on all processor models. Implemented registers are contiguous starting with\r
- register 0. No parameter checking is performed on Index. If the Index value\r
- is beyond the implemented IBR register range, a Reserved Register/Field fault may\r
- occur. The caller must either guarantee that Index is valid, or the caller must\r
- set up fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Index The 8-bit Instruction Breakpoint Register index to write.\r
- @param Value The 64-bit value to write to IBR.\r
-\r
- @return The 64-bit value written to the IBR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteIbr (\r
- IN UINT8 Index,\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Data Breakpoint Register (DBR).\r
-\r
- Writes current value of Data Breakpoint Register specified by Index.\r
- The Data Breakpoint Registers are used in pairs. The even numbered registers\r
- contain breakpoint addresses, and odd numbered registers contain breakpoint\r
- mask conditions. At least four data registers pairs are implemented on all processor\r
- models. Implemented registers are contiguous starting with register 0. No parameter\r
- checking is performed on Index. If the Index value is beyond the implemented\r
- DBR register range, a Reserved Register/Field fault may occur. The caller must\r
- either guarantee that Index is valid, or the caller must set up fault handlers to\r
- catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Index The 8-bit Data Breakpoint Register index to write.\r
- @param Value The 64-bit value to write to DBR.\r
-\r
- @return The 64-bit value written to the DBR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteDbr (\r
- IN UINT8 Index,\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Performance Monitor Configuration Register (PMC).\r
-\r
- Writes current value of Performance Monitor Configuration Register specified by Index.\r
- All processor implementations provide at least four performance counters\r
- (PMC/PMD [4]...PMC/PMD [7] pairs), and four performance monitor counter overflow status\r
- registers (PMC [0]... PMC [3]). Processor implementations may provide additional\r
- implementation-dependent PMC and PMD to increase the number of 'generic' performance\r
- counters (PMC/PMD pairs). The remainder of PMC and PMD register set is implementation\r
- dependent. No parameter checking is performed on Index. If the Index value is\r
- beyond the implemented PMC register range, the write is ignored.\r
- This function is only available on Itanium processors.\r
-\r
- @param Index The 8-bit Performance Monitor Configuration Register index to write.\r
- @param Value The 64-bit value to write to PMC.\r
-\r
- @return The 64-bit value written to the PMC.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWritePmc (\r
- IN UINT8 Index,\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Performance Monitor Data Register (PMD).\r
-\r
- Writes current value of Performance Monitor Data Register specified by Index.\r
- All processor implementations provide at least four performance counters\r
- (PMC/PMD [4]...PMC/PMD [7] pairs), and four performance monitor counter overflow\r
- status registers (PMC [0]... PMC [3]). Processor implementations may provide\r
- additional implementation-dependent PMC and PMD to increase the number of 'generic'\r
- performance counters (PMC/PMD pairs). The remainder of PMC and PMD register set\r
- is implementation dependent. No parameter checking is performed on Index. If the\r
- Index value is beyond the implemented PMD register range, the write is ignored.\r
- This function is only available on Itanium processors.\r
-\r
- @param Index The 8-bit Performance Monitor Data Register index to write.\r
- @param Value The 64-bit value to write to PMD.\r
-\r
- @return The 64-bit value written to the PMD.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWritePmd (\r
- IN UINT8 Index,\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of 64-bit Global Pointer (GP).\r
-\r
- Reads and returns the current value of GP.\r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of GP.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadGp (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Write the current value of 64-bit Global Pointer (GP).\r
-\r
- Writes the current value of GP. The 64-bit value written to the GP is returned.\r
- No parameter checking is performed on Value.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to GP.\r
-\r
- @return The 64-bit value written to the GP.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteGp (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of 64-bit Stack Pointer (SP).\r
-\r
- Reads and returns the current value of SP.\r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of SP.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadSp (\r
- VOID\r
- );\r
-\r
-\r
-///\r
-/// Valid Index value for AsmReadControlRegister().\r
-///\r
-#define IPF_CONTROL_REGISTER_DCR 0\r
-#define IPF_CONTROL_REGISTER_ITM 1\r
-#define IPF_CONTROL_REGISTER_IVA 2\r
-#define IPF_CONTROL_REGISTER_PTA 8\r
-#define IPF_CONTROL_REGISTER_IPSR 16\r
-#define IPF_CONTROL_REGISTER_ISR 17\r
-#define IPF_CONTROL_REGISTER_IIP 19\r
-#define IPF_CONTROL_REGISTER_IFA 20\r
-#define IPF_CONTROL_REGISTER_ITIR 21\r
-#define IPF_CONTROL_REGISTER_IIPA 22\r
-#define IPF_CONTROL_REGISTER_IFS 23\r
-#define IPF_CONTROL_REGISTER_IIM 24\r
-#define IPF_CONTROL_REGISTER_IHA 25\r
-#define IPF_CONTROL_REGISTER_LID 64\r
-#define IPF_CONTROL_REGISTER_IVR 65\r
-#define IPF_CONTROL_REGISTER_TPR 66\r
-#define IPF_CONTROL_REGISTER_EOI 67\r
-#define IPF_CONTROL_REGISTER_IRR0 68\r
-#define IPF_CONTROL_REGISTER_IRR1 69\r
-#define IPF_CONTROL_REGISTER_IRR2 70\r
-#define IPF_CONTROL_REGISTER_IRR3 71\r
-#define IPF_CONTROL_REGISTER_ITV 72\r
-#define IPF_CONTROL_REGISTER_PMV 73\r
-#define IPF_CONTROL_REGISTER_CMCV 74\r
-#define IPF_CONTROL_REGISTER_LRR0 80\r
-#define IPF_CONTROL_REGISTER_LRR1 81\r
-\r
-/**\r
- Reads a 64-bit control register.\r
-\r
- Reads and returns the control register specified by Index. The valid Index valued\r
- are defined above in "Related Definitions".\r
- If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned. This function is only\r
- available on Itanium processors.\r
-\r
- @param Index The index of the control register to read.\r
-\r
- @return The control register specified by Index.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadControlRegister (\r
- IN UINT64 Index\r
- );\r
-\r
-\r
-///\r
-/// Valid Index value for AsmReadApplicationRegister().\r
-///\r
-#define IPF_APPLICATION_REGISTER_K0 0\r
-#define IPF_APPLICATION_REGISTER_K1 1\r
-#define IPF_APPLICATION_REGISTER_K2 2\r
-#define IPF_APPLICATION_REGISTER_K3 3\r
-#define IPF_APPLICATION_REGISTER_K4 4\r
-#define IPF_APPLICATION_REGISTER_K5 5\r
-#define IPF_APPLICATION_REGISTER_K6 6\r
-#define IPF_APPLICATION_REGISTER_K7 7\r
-#define IPF_APPLICATION_REGISTER_RSC 16\r
-#define IPF_APPLICATION_REGISTER_BSP 17\r
-#define IPF_APPLICATION_REGISTER_BSPSTORE 18\r
-#define IPF_APPLICATION_REGISTER_RNAT 19\r
-#define IPF_APPLICATION_REGISTER_FCR 21\r
-#define IPF_APPLICATION_REGISTER_EFLAG 24\r
-#define IPF_APPLICATION_REGISTER_CSD 25\r
-#define IPF_APPLICATION_REGISTER_SSD 26\r
-#define IPF_APPLICATION_REGISTER_CFLG 27\r
-#define IPF_APPLICATION_REGISTER_FSR 28\r
-#define IPF_APPLICATION_REGISTER_FIR 29\r
-#define IPF_APPLICATION_REGISTER_FDR 30\r
-#define IPF_APPLICATION_REGISTER_CCV 32\r
-#define IPF_APPLICATION_REGISTER_UNAT 36\r
-#define IPF_APPLICATION_REGISTER_FPSR 40\r
-#define IPF_APPLICATION_REGISTER_ITC 44\r
-#define IPF_APPLICATION_REGISTER_PFS 64\r
-#define IPF_APPLICATION_REGISTER_LC 65\r
-#define IPF_APPLICATION_REGISTER_EC 66\r
-\r
-/**\r
- Reads a 64-bit application register.\r
-\r
- Reads and returns the application register specified by Index. The valid Index\r
- valued are defined above in "Related Definitions".\r
- If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned. This function is only\r
- available on Itanium processors.\r
-\r
- @param Index The index of the application register to read.\r
-\r
- @return The application register specified by Index.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadApplicationRegister (\r
- IN UINT64 Index\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of a Machine Specific Register (MSR).\r
-\r
- Reads and returns the current value of the Machine Specific Register specified by Index. No\r
- parameter checking is performed on Index, and if the Index value is beyond the implemented MSR\r
- register range, a Reserved Register/Field fault may occur. The caller must either guarantee that\r
- Index is valid, or the caller must set up fault handlers to catch the faults. This function is\r
- only available on Itanium processors.\r
-\r
- @param Index The 8-bit Machine Specific Register index to read.\r
-\r
- @return The current value of the Machine Specific Register specified by Index.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadMsr (\r
- IN UINT8 Index\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of a Machine Specific Register (MSR).\r
-\r
- Writes Value to the Machine Specific Register specified by Index. Value is returned. No\r
- parameter checking is performed on Index, and if the Index value is beyond the implemented MSR\r
- register range, a Reserved Register/Field fault may occur. The caller must either guarantee that\r
- Index is valid, or the caller must set up fault handlers to catch the faults. This function is\r
- only available on Itanium processors.\r
-\r
- @param Index The 8-bit Machine Specific Register index to write.\r
- @param Value The 64-bit value to write to the Machine Specific Register.\r
-\r
- @return The 64-bit value to write to the Machine Specific Register.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteMsr (\r
- IN UINT8 Index,\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Determines if the CPU is currently executing in virtual, physical, or mixed mode.\r
-\r
- Determines the current execution mode of the CPU.\r
- If the CPU is in virtual mode(PSR.RT=1, PSR.DT=1, PSR.IT=1), then 1 is returned.\r
- If the CPU is in physical mode(PSR.RT=0, PSR.DT=0, PSR.IT=0), then 0 is returned.\r
- If the CPU is not in physical mode or virtual mode, then it is in mixed mode,\r
- and -1 is returned.\r
- This function is only available on Itanium processors.\r
-\r
- @retval 1 The CPU is in virtual mode.\r
- @retval 0 The CPU is in physical mode.\r
- @retval -1 The CPU is in mixed mode.\r
-\r
-**/\r
-INT64\r
-EFIAPI\r
-AsmCpuVirtual (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Makes a PAL procedure call.\r
-\r
- This is a wrapper function to make a PAL procedure call. Based on the Index\r
- value this API will make static or stacked PAL call. The following table\r
- describes the usage of PAL Procedure Index Assignment. Architected procedures\r
- may be designated as required or optional. If a PAL procedure is specified\r
- as optional, a unique return code of 0xFFFFFFFFFFFFFFFF is returned in the\r
- Status field of the PAL_CALL_RETURN structure.\r
- This indicates that the procedure is not present in this PAL implementation.\r
- It is the caller's responsibility to check for this return code after calling\r
- any optional PAL procedure.\r
- No parameter checking is performed on the 5 input parameters, but there are\r
- some common rules that the caller should follow when making a PAL call. Any\r
- address passed to PAL as buffers for return parameters must be 8-byte aligned.\r
- Unaligned addresses may cause undefined results. For those parameters defined\r
- as reserved or some fields defined as reserved must be zero filled or the invalid\r
- argument return value may be returned or undefined result may occur during the\r
- execution of the procedure. If the PalEntryPoint does not point to a valid\r
- PAL entry point then the system behavior is undefined. This function is only\r
- available on Itanium processors.\r
-\r
- @param PalEntryPoint The PAL procedure calls entry point.\r
- @param Index The PAL procedure Index number.\r
- @param Arg2 The 2nd parameter for PAL procedure calls.\r
- @param Arg3 The 3rd parameter for PAL procedure calls.\r
- @param Arg4 The 4th parameter for PAL procedure calls.\r
-\r
- @return structure returned from the PAL Call procedure, including the status and return value.\r
-\r
-**/\r
-PAL_CALL_RETURN\r
-EFIAPI\r
-AsmPalCall (\r
- IN UINT64 PalEntryPoint,\r
- IN UINT64 Index,\r
- IN UINT64 Arg2,\r
- IN UINT64 Arg3,\r
- IN UINT64 Arg4\r
- );\r
-#endif // defined (MDE_CPU_IPF)\r
-\r
-#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)\r
-///\r
-/// IA32 and x64 Specific Functions.\r
-/// Byte packed structure for 16-bit Real Mode EFLAGS.\r
-///\r
-typedef union {\r
- struct {\r
- UINT32 CF:1; ///< Carry Flag.\r
- UINT32 Reserved_0:1; ///< Reserved.\r
- UINT32 PF:1; ///< Parity Flag.\r
- UINT32 Reserved_1:1; ///< Reserved.\r
- UINT32 AF:1; ///< Auxiliary Carry Flag.\r
- UINT32 Reserved_2:1; ///< Reserved.\r
- UINT32 ZF:1; ///< Zero Flag.\r
- UINT32 SF:1; ///< Sign Flag.\r
- UINT32 TF:1; ///< Trap Flag.\r
- UINT32 IF:1; ///< Interrupt Enable Flag.\r
- UINT32 DF:1; ///< Direction Flag.\r
- UINT32 OF:1; ///< Overflow Flag.\r
- UINT32 IOPL:2; ///< I/O Privilege Level.\r
- UINT32 NT:1; ///< Nested Task.\r
- UINT32 Reserved_3:1; ///< Reserved.\r
- } Bits;\r
- UINT16 Uint16;\r
-} IA32_FLAGS16;\r
-\r
-///\r
-/// Byte packed structure for EFLAGS/RFLAGS.\r
-/// 32-bits on IA-32.\r
-/// 64-bits on x64. The upper 32-bits on x64 are reserved.\r
-///\r
-typedef union {\r
- struct {\r
- UINT32 CF:1; ///< Carry Flag.\r
- UINT32 Reserved_0:1; ///< Reserved.\r
- UINT32 PF:1; ///< Parity Flag.\r
- UINT32 Reserved_1:1; ///< Reserved.\r
- UINT32 AF:1; ///< Auxiliary Carry Flag.\r
- UINT32 Reserved_2:1; ///< Reserved.\r
- UINT32 ZF:1; ///< Zero Flag.\r
- UINT32 SF:1; ///< Sign Flag.\r
- UINT32 TF:1; ///< Trap Flag.\r
- UINT32 IF:1; ///< Interrupt Enable Flag.\r
- UINT32 DF:1; ///< Direction Flag.\r
- UINT32 OF:1; ///< Overflow Flag.\r
- UINT32 IOPL:2; ///< I/O Privilege Level.\r
- UINT32 NT:1; ///< Nested Task.\r
- UINT32 Reserved_3:1; ///< Reserved.\r
- UINT32 RF:1; ///< Resume Flag.\r
- UINT32 VM:1; ///< Virtual 8086 Mode.\r
- UINT32 AC:1; ///< Alignment Check.\r
- UINT32 VIF:1; ///< Virtual Interrupt Flag.\r
- UINT32 VIP:1; ///< Virtual Interrupt Pending.\r
- UINT32 ID:1; ///< ID Flag.\r
- UINT32 Reserved_4:10; ///< Reserved.\r
- } Bits;\r
- UINTN UintN;\r
-} IA32_EFLAGS32;\r
-\r
-///\r
-/// Byte packed structure for Control Register 0 (CR0).\r
-/// 32-bits on IA-32.\r
-/// 64-bits on x64. The upper 32-bits on x64 are reserved.\r
-///\r
-typedef union {\r
- struct {\r
- UINT32 PE:1; ///< Protection Enable.\r
- UINT32 MP:1; ///< Monitor Coprocessor.\r
- UINT32 EM:1; ///< Emulation.\r
- UINT32 TS:1; ///< Task Switched.\r
- UINT32 ET:1; ///< Extension Type.\r
- UINT32 NE:1; ///< Numeric Error.\r
- UINT32 Reserved_0:10; ///< Reserved.\r
- UINT32 WP:1; ///< Write Protect.\r
- UINT32 Reserved_1:1; ///< Reserved.\r
- UINT32 AM:1; ///< Alignment Mask.\r
- UINT32 Reserved_2:10; ///< Reserved.\r
- UINT32 NW:1; ///< Mot Write-through.\r
- UINT32 CD:1; ///< Cache Disable.\r
- UINT32 PG:1; ///< Paging.\r
- } Bits;\r
- UINTN UintN;\r
-} IA32_CR0;\r
-\r
-///\r
-/// Byte packed structure for Control Register 4 (CR4).\r
-/// 32-bits on IA-32.\r
-/// 64-bits on x64. The upper 32-bits on x64 are reserved.\r
-///\r
-typedef union {\r
- struct {\r
- UINT32 VME:1; ///< Virtual-8086 Mode Extensions.\r
- UINT32 PVI:1; ///< Protected-Mode Virtual Interrupts.\r
- UINT32 TSD:1; ///< Time Stamp Disable.\r
- UINT32 DE:1; ///< Debugging Extensions.\r
- UINT32 PSE:1; ///< Page Size Extensions.\r
- UINT32 PAE:1; ///< Physical Address Extension.\r
- UINT32 MCE:1; ///< Machine Check Enable.\r
- UINT32 PGE:1; ///< Page Global Enable.\r
- UINT32 PCE:1; ///< Performance Monitoring Counter\r
- ///< Enable.\r
- UINT32 OSFXSR:1; ///< Operating System Support for\r
- ///< FXSAVE and FXRSTOR instructions\r
- UINT32 OSXMMEXCPT:1; ///< Operating System Support for\r
- ///< Unmasked SIMD Floating Point\r
- ///< Exceptions.\r
- UINT32 Reserved_0:2; ///< Reserved.\r
- UINT32 VMXE:1; ///< VMX Enable\r
- UINT32 Reserved_1:18; ///< Reserved.\r
- } Bits;\r
- UINTN UintN;\r
-} IA32_CR4;\r
-\r
-///\r
-/// Byte packed structure for a segment descriptor in a GDT/LDT.\r
-///\r
-typedef union {\r
- struct {\r
- UINT32 LimitLow:16;\r
- UINT32 BaseLow:16;\r
- UINT32 BaseMid:8;\r
- UINT32 Type:4;\r
- UINT32 S:1;\r
- UINT32 DPL:2;\r
- UINT32 P:1;\r
- UINT32 LimitHigh:4;\r
- UINT32 AVL:1;\r
- UINT32 L:1;\r
- UINT32 DB:1;\r
- UINT32 G:1;\r
- UINT32 BaseHigh:8;\r
- } Bits;\r
- UINT64 Uint64;\r
-} IA32_SEGMENT_DESCRIPTOR;\r
-\r
-///\r
-/// Byte packed structure for an IDTR, GDTR, LDTR descriptor.\r
-///\r
-#pragma pack (1)\r
-typedef struct {\r
- UINT16 Limit;\r
- UINTN Base;\r
-} IA32_DESCRIPTOR;\r
-#pragma pack ()\r
-\r
-#define IA32_IDT_GATE_TYPE_TASK 0x85\r
-#define IA32_IDT_GATE_TYPE_INTERRUPT_16 0x86\r
-#define IA32_IDT_GATE_TYPE_TRAP_16 0x87\r
-#define IA32_IDT_GATE_TYPE_INTERRUPT_32 0x8E\r
-#define IA32_IDT_GATE_TYPE_TRAP_32 0x8F\r
-\r
-#define IA32_GDT_TYPE_TSS 0x9\r
-#define IA32_GDT_ALIGNMENT 8\r
-\r
-#if defined (MDE_CPU_IA32)\r
-///\r
-/// Byte packed structure for an IA-32 Interrupt Gate Descriptor.\r
-///\r
-typedef union {\r
- struct {\r
- UINT32 OffsetLow:16; ///< Offset bits 15..0.\r
- UINT32 Selector:16; ///< Selector.\r
- UINT32 Reserved_0:8; ///< Reserved.\r
- UINT32 GateType:8; ///< Gate Type. See #defines above.\r
- UINT32 OffsetHigh:16; ///< Offset bits 31..16.\r
- } Bits;\r
- UINT64 Uint64;\r
-} IA32_IDT_GATE_DESCRIPTOR;\r
-\r
-#pragma pack (1)\r
-//\r
-// IA32 Task-State Segment Definition\r
-//\r
-typedef struct {\r
- UINT16 PreviousTaskLink;\r
- UINT16 Reserved_2;\r
- UINT32 ESP0;\r
- UINT16 SS0;\r
- UINT16 Reserved_10;\r
- UINT32 ESP1;\r
- UINT16 SS1;\r
- UINT16 Reserved_18;\r
- UINT32 ESP2;\r
- UINT16 SS2;\r
- UINT16 Reserved_26;\r
- UINT32 CR3;\r
- UINT32 EIP;\r
- UINT32 EFLAGS;\r
- UINT32 EAX;\r
- UINT32 ECX;\r
- UINT32 EDX;\r
- UINT32 EBX;\r
- UINT32 ESP;\r
- UINT32 EBP;\r
- UINT32 ESI;\r
- UINT32 EDI;\r
- UINT16 ES;\r
- UINT16 Reserved_74;\r
- UINT16 CS;\r
- UINT16 Reserved_78;\r
- UINT16 SS;\r
- UINT16 Reserved_82;\r
- UINT16 DS;\r
- UINT16 Reserved_86;\r
- UINT16 FS;\r
- UINT16 Reserved_90;\r
- UINT16 GS;\r
- UINT16 Reserved_94;\r
- UINT16 LDTSegmentSelector;\r
- UINT16 Reserved_98;\r
- UINT16 T;\r
- UINT16 IOMapBaseAddress;\r
-} IA32_TASK_STATE_SEGMENT;\r
+#pragma pack (1)\r
+//\r
+// IA32 Task-State Segment Definition\r
+//\r
+typedef struct {\r
+ UINT16 PreviousTaskLink;\r
+ UINT16 Reserved_2;\r
+ UINT32 ESP0;\r
+ UINT16 SS0;\r
+ UINT16 Reserved_10;\r
+ UINT32 ESP1;\r
+ UINT16 SS1;\r
+ UINT16 Reserved_18;\r
+ UINT32 ESP2;\r
+ UINT16 SS2;\r
+ UINT16 Reserved_26;\r
+ UINT32 CR3;\r
+ UINT32 EIP;\r
+ UINT32 EFLAGS;\r
+ UINT32 EAX;\r
+ UINT32 ECX;\r
+ UINT32 EDX;\r
+ UINT32 EBX;\r
+ UINT32 ESP;\r
+ UINT32 EBP;\r
+ UINT32 ESI;\r
+ UINT32 EDI;\r
+ UINT16 ES;\r
+ UINT16 Reserved_74;\r
+ UINT16 CS;\r
+ UINT16 Reserved_78;\r
+ UINT16 SS;\r
+ UINT16 Reserved_82;\r
+ UINT16 DS;\r
+ UINT16 Reserved_86;\r
+ UINT16 FS;\r
+ UINT16 Reserved_90;\r
+ UINT16 GS;\r
+ UINT16 Reserved_94;\r
+ UINT16 LDTSegmentSelector;\r
+ UINT16 Reserved_98;\r
+ UINT16 T;\r
+ UINT16 IOMapBaseAddress;\r
+} IA32_TASK_STATE_SEGMENT;\r
\r
typedef union {\r
struct {\r
IN UINT16 Selector\r
);\r
\r
+/**\r
+ Performs a serializing operation on all load-from-memory instructions that\r
+ were issued prior the AsmLfence function.\r
+\r
+ Executes a LFENCE instruction. This function is only available on IA-32 and x64.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmLfence (\r
+ VOID\r
+ );\r
+\r
/**\r
Patch the immediate operand of an IA32 or X64 instruction such that the byte,\r
word, dword or qword operand is encoded at the end of the instruction's\r
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