Provides string functions, linked list functions, math functions, synchronization\r
functions, file path functions, and CPU architecture-specific functions.\r
\r
-Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution. The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php.\r
-\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
UINT32 Ebp;\r
UINT32 Esp;\r
UINT32 Eip;\r
+ UINT32 Ssp;\r
} BASE_LIBRARY_JUMP_BUFFER;\r
\r
#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 4\r
\r
#endif // defined (MDE_CPU_IA32)\r
\r
-#if defined (MDE_CPU_IPF)\r
-\r
-///\r
-/// The Itanium architecture context buffer used by SetJump() and LongJump().\r
-///\r
-typedef struct {\r
- UINT64 F2[2];\r
- UINT64 F3[2];\r
- UINT64 F4[2];\r
- UINT64 F5[2];\r
- UINT64 F16[2];\r
- UINT64 F17[2];\r
- UINT64 F18[2];\r
- UINT64 F19[2];\r
- UINT64 F20[2];\r
- UINT64 F21[2];\r
- UINT64 F22[2];\r
- UINT64 F23[2];\r
- UINT64 F24[2];\r
- UINT64 F25[2];\r
- UINT64 F26[2];\r
- UINT64 F27[2];\r
- UINT64 F28[2];\r
- UINT64 F29[2];\r
- UINT64 F30[2];\r
- UINT64 F31[2];\r
- UINT64 R4;\r
- UINT64 R5;\r
- UINT64 R6;\r
- UINT64 R7;\r
- UINT64 SP;\r
- UINT64 BR0;\r
- UINT64 BR1;\r
- UINT64 BR2;\r
- UINT64 BR3;\r
- UINT64 BR4;\r
- UINT64 BR5;\r
- UINT64 InitialUNAT;\r
- UINT64 AfterSpillUNAT;\r
- UINT64 PFS;\r
- UINT64 BSP;\r
- UINT64 Predicates;\r
- UINT64 LoopCount;\r
- UINT64 FPSR;\r
-} BASE_LIBRARY_JUMP_BUFFER;\r
-\r
-#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 0x10\r
-\r
-#endif // defined (MDE_CPU_IPF)\r
-\r
#if defined (MDE_CPU_X64)\r
///\r
/// The x64 architecture context buffer used by SetJump() and LongJump().\r
UINT64 Rip;\r
UINT64 MxCsr;\r
UINT8 XmmBuffer[160]; ///< XMM6-XMM15.\r
+ UINT64 Ssp;\r
} BASE_LIBRARY_JUMP_BUFFER;\r
\r
#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8\r
@retval RETURN_INVALID_PARAMETER If Destination is NULL.\r
If Source is NULL.\r
If PcdMaximumUnicodeStringLength is not zero,\r
- and DestMax is greater than \r
+ and DestMax is greater than\r
PcdMaximumUnicodeStringLength.\r
If DestMax is 0.\r
@retval RETURN_ACCESS_DENIED If Source and Destination overlap.\r
@param Length The maximum number of Unicode characters to copy.\r
\r
@retval RETURN_SUCCESS String is copied.\r
- @retval RETURN_BUFFER_TOO_SMALL If DestMax is NOT greater than \r
+ @retval RETURN_BUFFER_TOO_SMALL If DestMax is NOT greater than\r
MIN(StrLen(Source), Length).\r
@retval RETURN_INVALID_PARAMETER If Destination is NULL.\r
If Source is NULL.\r
If PcdMaximumUnicodeStringLength is not zero,\r
- and DestMax is greater than \r
+ and DestMax is greater than\r
PcdMaximumUnicodeStringLength.\r
If DestMax is 0.\r
@retval RETURN_ACCESS_DENIED If Source and Destination overlap.\r
@param Source A pointer to a Null-terminated Unicode string.\r
\r
@retval RETURN_SUCCESS String is appended.\r
- @retval RETURN_BAD_BUFFER_SIZE If DestMax is NOT greater than \r
+ @retval RETURN_BAD_BUFFER_SIZE If DestMax is NOT greater than\r
StrLen(Destination).\r
@retval RETURN_BUFFER_TOO_SMALL If (DestMax - StrLen(Destination)) is NOT\r
greater than StrLen(Source).\r
@retval RETURN_INVALID_PARAMETER If Destination is NULL.\r
If Source is NULL.\r
If PcdMaximumUnicodeStringLength is not zero,\r
- and DestMax is greater than \r
+ and DestMax is greater than\r
PcdMaximumUnicodeStringLength.\r
If DestMax is 0.\r
@retval RETURN_ACCESS_DENIED If Source and Destination overlap.\r
@retval RETURN_INVALID_PARAMETER If Destination is NULL.\r
If Source is NULL.\r
If PcdMaximumUnicodeStringLength is not zero,\r
- and DestMax is greater than \r
+ and DestMax is greater than\r
PcdMaximumUnicodeStringLength.\r
If DestMax is 0.\r
@retval RETURN_ACCESS_DENIED If Source and Destination overlap.\r
@retval RETURN_INVALID_PARAMETER If Destination is NULL.\r
If Source is NULL.\r
If PcdMaximumAsciiStringLength is not zero,\r
- and DestMax is greater than \r
+ and DestMax is greater than\r
PcdMaximumAsciiStringLength.\r
If DestMax is 0.\r
@retval RETURN_ACCESS_DENIED If Source and Destination overlap.\r
@param Length The maximum number of Ascii characters to copy.\r
\r
@retval RETURN_SUCCESS String is copied.\r
- @retval RETURN_BUFFER_TOO_SMALL If DestMax is NOT greater than \r
+ @retval RETURN_BUFFER_TOO_SMALL If DestMax is NOT greater than\r
MIN(StrLen(Source), Length).\r
@retval RETURN_INVALID_PARAMETER If Destination is NULL.\r
If Source is NULL.\r
If PcdMaximumAsciiStringLength is not zero,\r
- and DestMax is greater than \r
+ and DestMax is greater than\r
PcdMaximumAsciiStringLength.\r
If DestMax is 0.\r
@retval RETURN_ACCESS_DENIED If Source and Destination overlap.\r
@param Source A pointer to a Null-terminated Ascii string.\r
\r
@retval RETURN_SUCCESS String is appended.\r
- @retval RETURN_BAD_BUFFER_SIZE If DestMax is NOT greater than \r
+ @retval RETURN_BAD_BUFFER_SIZE If DestMax is NOT greater than\r
StrLen(Destination).\r
@retval RETURN_BUFFER_TOO_SMALL If (DestMax - StrLen(Destination)) is NOT\r
greater than StrLen(Source).\r
@retval RETURN_INVALID_PARAMETER If Destination is NULL.\r
If Source is NULL.\r
If PcdMaximumAsciiStringLength is not zero,\r
- and DestMax is greater than \r
+ and DestMax is greater than\r
PcdMaximumAsciiStringLength.\r
If DestMax is 0.\r
@retval RETURN_ACCESS_DENIED If Source and Destination overlap.\r
@retval RETURN_INVALID_PARAMETER If Destination is NULL.\r
If Source is NULL.\r
If PcdMaximumAsciiStringLength is not zero,\r
- and DestMax is greater than \r
+ and DestMax is greater than\r
PcdMaximumAsciiStringLength.\r
If DestMax is 0.\r
@retval RETURN_ACCESS_DENIED If Source and Destination overlap.\r
/**\r
[ATTENTION] This function is deprecated for security reason.\r
\r
- Copies up to a specified length from one Null-terminated Unicode string to \r
+ Copies up to a specified length from one Null-terminated Unicode string to\r
another Null-terminated Unicode string and returns the new Unicode string.\r
\r
This function copies the contents of the Unicode string Source to the Unicode\r
If Length > 0 and Source is NULL, then ASSERT().\r
If Length > 0 and Source is not aligned on a 16-bit boundary, then ASSERT().\r
If Source and Destination overlap, then ASSERT().\r
- If PcdMaximumUnicodeStringLength is not zero, and Length is greater than \r
+ If PcdMaximumUnicodeStringLength is not zero, and Length is greater than\r
PcdMaximumUnicodeStringLength, then ASSERT().\r
If PcdMaximumUnicodeStringLength is not zero, and Source contains more than\r
PcdMaximumUnicodeStringLength Unicode characters, not including the Null-terminator,\r
IN CONST CHAR16 *Source,\r
IN UINTN Length\r
);\r
-#endif\r
+#endif // !defined (DISABLE_NEW_DEPRECATED_INTERFACES)\r
\r
/**\r
Returns the length of a Null-terminated Unicode string.\r
Returns the size of a Null-terminated Unicode string in bytes, including the\r
Null terminator.\r
\r
- This function returns the size, in bytes, of the Null-terminated Unicode string \r
+ This function returns the size, in bytes, of the Null-terminated Unicode string\r
specified by String.\r
\r
If String is NULL, then ASSERT().\r
/**\r
Compares up to a specified length the contents of two Null-terminated Unicode strings,\r
and returns the difference between the first mismatched Unicode characters.\r
- \r
+\r
This function compares the Null-terminated Unicode string FirstString to the\r
Null-terminated Unicode string SecondString. At most, Length Unicode\r
characters will be compared. If Length is 0, then 0 is returned. If\r
/**\r
[ATTENTION] This function is deprecated for security reason.\r
\r
- Concatenates up to a specified length one Null-terminated Unicode to the end \r
- of another Null-terminated Unicode string, and returns the concatenated \r
+ Concatenates up to a specified length one Null-terminated Unicode to the end\r
+ of another Null-terminated Unicode string, and returns the concatenated\r
Unicode string.\r
\r
This function concatenates two Null-terminated Unicode strings. The contents\r
If Length > 0 and Source is NULL, then ASSERT().\r
If Length > 0 and Source is not aligned on a 16-bit boundary, then ASSERT().\r
If Source and Destination overlap, then ASSERT().\r
- If PcdMaximumUnicodeStringLength is not zero, and Length is greater than \r
+ If PcdMaximumUnicodeStringLength is not zero, and Length is greater than\r
PcdMaximumUnicodeStringLength, then ASSERT().\r
If PcdMaximumUnicodeStringLength is not zero, and Destination contains more\r
than PcdMaximumUnicodeStringLength Unicode characters, not including the\r
IN CONST CHAR16 *Source,\r
IN UINTN Length\r
);\r
-#endif\r
+#endif // !defined (DISABLE_NEW_DEPRECATED_INTERFACES)\r
\r
/**\r
Returns the first occurrence of a Null-terminated Unicode sub-string\r
StrDecimalToUint64 (\r
IN CONST CHAR16 *String\r
);\r
- \r
+\r
\r
/**\r
Convert a Null-terminated Unicode hexadecimal string to a value of type UINTN.\r
The function will ignore the pad space, which includes spaces or tab characters,\r
before [zeros], [x] or [hexadecimal digit]. The running zero before [x] or\r
[hexadecimal digit] will be ignored. Then, the decoding starts after [x] or the\r
- first valid hexadecimal digit. Then, the function stops at the first character \r
+ first valid hexadecimal digit. Then, the function stops at the first character\r
that is a not a valid hexadecimal character or NULL, whichever one comes first.\r
\r
If String is NULL, then ASSERT().\r
OUT CHAR8 *Destination\r
);\r
\r
-#endif\r
+#endif // !defined (DISABLE_NEW_DEPRECATED_INTERFACES)\r
\r
/**\r
Convert a Null-terminated Unicode string to a Null-terminated\r
/**\r
[ATTENTION] This function is deprecated for security reason.\r
\r
- Copies up to a specified length one Null-terminated ASCII string to another \r
+ Copies up to a specified length one Null-terminated ASCII string to another\r
Null-terminated ASCII string and returns the new ASCII string.\r
\r
This function copies the contents of the ASCII string Source to the ASCII\r
If Destination is NULL, then ASSERT().\r
If Source is NULL, then ASSERT().\r
If Source and Destination overlap, then ASSERT().\r
- If PcdMaximumAsciiStringLength is not zero, and Length is greater than \r
+ If PcdMaximumAsciiStringLength is not zero, and Length is greater than\r
PcdMaximumAsciiStringLength, then ASSERT().\r
If PcdMaximumAsciiStringLength is not zero, and Source contains more than\r
PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,\r
IN CONST CHAR8 *Source,\r
IN UINTN Length\r
);\r
-#endif\r
+#endif // !defined (DISABLE_NEW_DEPRECATED_INTERFACES)\r
\r
/**\r
Returns the length of a Null-terminated ASCII string.\r
\r
If Length > 0 and FirstString is NULL, then ASSERT().\r
If Length > 0 and SecondString is NULL, then ASSERT().\r
- If PcdMaximumAsciiStringLength is not zero, and Length is greater than \r
+ If PcdMaximumAsciiStringLength is not zero, and Length is greater than\r
PcdMaximumAsciiStringLength, then ASSERT().\r
If PcdMaximumAsciiStringLength is not zero, and FirstString contains more than\r
PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,\r
@param FirstString The pointer to a Null-terminated ASCII string.\r
@param SecondString The pointer to a Null-terminated ASCII string.\r
@param Length The maximum number of ASCII characters for compare.\r
- \r
+\r
@retval ==0 FirstString is identical to SecondString.\r
@retval !=0 FirstString is not identical to SecondString.\r
\r
/**\r
[ATTENTION] This function is deprecated for security reason.\r
\r
- Concatenates up to a specified length one Null-terminated ASCII string to \r
- the end of another Null-terminated ASCII string, and returns the \r
+ Concatenates up to a specified length one Null-terminated ASCII string to\r
+ the end of another Null-terminated ASCII string, and returns the\r
concatenated ASCII string.\r
\r
This function concatenates two Null-terminated ASCII strings. The contents\r
IN CONST CHAR8 *Source,\r
IN UINTN Length\r
);\r
-#endif\r
+#endif // !defined (DISABLE_NEW_DEPRECATED_INTERFACES)\r
\r
/**\r
Returns the first occurrence of a Null-terminated ASCII sub-string\r
OUT CHAR16 *Destination\r
);\r
\r
-#endif\r
+#endif // !defined (DISABLE_NEW_DEPRECATED_INTERFACES)\r
\r
/**\r
Convert one Null-terminated ASCII string to a Null-terminated\r
OUT UINTN *DestinationLength\r
);\r
\r
+/**\r
+ Convert a Unicode character to upper case only if\r
+ it maps to a valid small-case ASCII character.\r
+\r
+ This internal function only deal with Unicode character\r
+ which maps to a valid small-case ASCII character, i.e.\r
+ L'a' to L'z'. For other Unicode character, the input character\r
+ is returned directly.\r
+\r
+ @param Char The character to convert.\r
+\r
+ @retval LowerCharacter If the Char is with range L'a' to L'z'.\r
+ @retval Unchanged Otherwise.\r
+\r
+**/\r
+CHAR16\r
+EFIAPI\r
+CharToUpper (\r
+ IN CHAR16 Char\r
+ );\r
+\r
+/**\r
+ Converts a lowercase Ascii character to upper one.\r
+\r
+ If Chr is lowercase Ascii character, then converts it to upper one.\r
+\r
+ If Value >= 0xA0, then ASSERT().\r
+ If (Value & 0x0F) >= 0x0A, then ASSERT().\r
+\r
+ @param Chr one Ascii character\r
+\r
+ @return The uppercase value of Ascii character\r
+\r
+**/\r
+CHAR8\r
+EFIAPI\r
+AsciiCharToUpper (\r
+ IN CHAR8 Chr\r
+ );\r
+\r
+/**\r
+ Convert binary data to a Base64 encoded ascii string based on RFC4648.\r
+\r
+ Produce a Null-terminated Ascii string in the output buffer specified by Destination and DestinationSize.\r
+ The Ascii string is produced by converting the data string specified by Source and SourceLength.\r
+\r
+ @param Source Input UINT8 data\r
+ @param SourceLength Number of UINT8 bytes of data\r
+ @param Destination Pointer to output string buffer\r
+ @param DestinationSize Size of ascii buffer. Set to 0 to get the size needed.\r
+ Caller is responsible for passing in buffer of DestinationSize\r
+\r
+ @retval RETURN_SUCCESS When ascii buffer is filled in.\r
+ @retval RETURN_INVALID_PARAMETER If Source is NULL or DestinationSize is NULL.\r
+ @retval RETURN_INVALID_PARAMETER If SourceLength or DestinationSize is bigger than (MAX_ADDRESS - (UINTN)Destination).\r
+ @retval RETURN_BUFFER_TOO_SMALL If SourceLength is 0 and DestinationSize is <1.\r
+ @retval RETURN_BUFFER_TOO_SMALL If Destination is NULL or DestinationSize is smaller than required buffersize.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+Base64Encode (\r
+ IN CONST UINT8 *Source,\r
+ IN UINTN SourceLength,\r
+ OUT CHAR8 *Destination OPTIONAL,\r
+ IN OUT UINTN *DestinationSize\r
+ );\r
+\r
+/**\r
+ Convert Base64 ascii string to binary data based on RFC4648.\r
+\r
+ Produce Null-terminated binary data in the output buffer specified by Destination and DestinationSize.\r
+ The binary data is produced by converting the Base64 ascii string specified by Source and SourceLength.\r
+\r
+ @param Source Input ASCII characters\r
+ @param SourceLength Number of ASCII characters\r
+ @param Destination Pointer to output buffer\r
+ @param DestinationSize Caller is responsible for passing in buffer of at least DestinationSize.\r
+ Set 0 to get the size needed. Set to bytes stored on return.\r
+\r
+ @retval RETURN_SUCCESS When binary buffer is filled in.\r
+ @retval RETURN_INVALID_PARAMETER If Source is NULL or DestinationSize is NULL.\r
+ @retval RETURN_INVALID_PARAMETER If SourceLength or DestinationSize is bigger than (MAX_ADDRESS -(UINTN)Destination ).\r
+ @retval RETURN_INVALID_PARAMETER If there is any invalid character in input stream.\r
+ @retval RETURN_BUFFER_TOO_SMALL If buffer length is smaller than required buffer size.\r
+\r
+ **/\r
+RETURN_STATUS\r
+EFIAPI\r
+Base64Decode (\r
+ IN CONST CHAR8 *Source,\r
+ IN UINTN SourceLength,\r
+ OUT UINT8 *Destination OPTIONAL,\r
+ IN OUT UINTN *DestinationSize\r
+ );\r
+\r
/**\r
Converts an 8-bit value to an 8-bit BCD value.\r
\r
\r
If ListHead is NULL, then ASSERT().\r
If Entry is NULL, then ASSERT().\r
- If ListHead was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or \r
+ If ListHead was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or\r
InitializeListHead(), then ASSERT().\r
If PcdMaximumLinkedListLength is not zero, and prior to insertion the number\r
of nodes in ListHead, including the ListHead node, is greater than or\r
/**\r
Retrieves the first node of a doubly linked list.\r
\r
- Returns the first node of a doubly linked list. List must have been \r
+ Returns the first node of a doubly linked list. List must have been\r
initialized with INTIALIZE_LIST_HEAD_VARIABLE() or InitializeListHead().\r
If List is empty, then List is returned.\r
\r
If List is NULL, then ASSERT().\r
- If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or \r
+ If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or\r
InitializeListHead(), then ASSERT().\r
If PcdMaximumLinkedListLength is not zero, and the number of nodes\r
in List, including the List node, is greater than or equal to\r
/**\r
Retrieves the next node of a doubly linked list.\r
\r
- Returns the node of a doubly linked list that follows Node. \r
+ Returns the node of a doubly linked list that follows Node.\r
List must have been initialized with INTIALIZE_LIST_HEAD_VARIABLE()\r
or InitializeListHead(). If List is empty, then List is returned.\r
\r
If List is NULL, then ASSERT().\r
If Node is NULL, then ASSERT().\r
- If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or \r
+ If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or\r
InitializeListHead(), then ASSERT().\r
If PcdMaximumLinkedListLength is not zero, and List contains more than\r
PcdMaximumLinkedListLength nodes, then ASSERT().\r
IN CONST LIST_ENTRY *Node\r
);\r
\r
- \r
+\r
/**\r
Retrieves the previous node of a doubly linked list.\r
- \r
- Returns the node of a doubly linked list that precedes Node. \r
+\r
+ Returns the node of a doubly linked list that precedes Node.\r
List must have been initialized with INTIALIZE_LIST_HEAD_VARIABLE()\r
or InitializeListHead(). If List is empty, then List is returned.\r
- \r
+\r
If List is NULL, then ASSERT().\r
If Node is NULL, then ASSERT().\r
- If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or \r
+ If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or\r
InitializeListHead(), then ASSERT().\r
If PcdMaximumLinkedListLength is not zero, and List contains more than\r
PcdMaximumLinkedListLength nodes, then ASSERT().\r
If PcdVerifyNodeInList is TRUE and Node is not a node in List, then ASSERT().\r
- \r
+\r
@param List A pointer to the head node of a doubly linked list.\r
@param Node A pointer to a node in the doubly linked list.\r
- \r
+\r
@return The pointer to the previous node if one exists. Otherwise List is returned.\r
- \r
+\r
**/\r
LIST_ENTRY *\r
EFIAPI\r
IN CONST LIST_ENTRY *Node\r
);\r
\r
- \r
+\r
/**\r
Checks to see if a doubly linked list is empty or not.\r
\r
zero nodes, this function returns TRUE. Otherwise, it returns FALSE.\r
\r
If ListHead is NULL, then ASSERT().\r
- If ListHead was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or \r
+ If ListHead was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or\r
InitializeListHead(), then ASSERT().\r
If PcdMaximumLinkedListLength is not zero, and the number of nodes\r
in List, including the List node, is greater than or equal to\r
\r
If List is NULL, then ASSERT().\r
If Node is NULL, then ASSERT().\r
- If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or InitializeListHead(), \r
+ If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or InitializeListHead(),\r
then ASSERT().\r
If PcdMaximumLinkedListLength is not zero, and the number of nodes\r
in List, including the List node, is greater than or equal to\r
PcdMaximumLinkedListLength, then ASSERT().\r
- If PcdVerifyNodeInList is TRUE and Node is not a node in List the and Node is not equal \r
+ If PcdVerifyNodeInList is TRUE and Node is not a node in List the and Node is not equal\r
to List, then ASSERT().\r
\r
@param List A pointer to the head node of a doubly linked list.\r
Otherwise, the location of the FirstEntry node is swapped with the location\r
of the SecondEntry node in a doubly linked list. SecondEntry must be in the\r
same double linked list as FirstEntry and that double linked list must have\r
- been initialized with INTIALIZE_LIST_HEAD_VARIABLE() or InitializeListHead(). \r
+ been initialized with INTIALIZE_LIST_HEAD_VARIABLE() or InitializeListHead().\r
SecondEntry is returned after the nodes are swapped.\r
\r
If FirstEntry is NULL, then ASSERT().\r
If SecondEntry is NULL, then ASSERT().\r
- If PcdVerifyNodeInList is TRUE and SecondEntry and FirstEntry are not in the \r
+ If PcdVerifyNodeInList is TRUE and SecondEntry and FirstEntry are not in the\r
same linked list, then ASSERT().\r
If PcdMaximumLinkedListLength is not zero, and the number of nodes in the\r
linked list containing the FirstEntry and SecondEntry nodes, including\r
\r
@param FirstEntry A pointer to a node in a linked list.\r
@param SecondEntry A pointer to another node in the same linked list.\r
- \r
+\r
@return SecondEntry.\r
\r
**/\r
function returns the 64-bit signed quotient.\r
\r
It is the caller's responsibility to not call this function with a Divisor of 0.\r
- If Divisor is 0, then the quotient and remainder should be assumed to be \r
+ If Divisor is 0, then the quotient and remainder should be assumed to be\r
the largest negative integer.\r
\r
If Divisor is 0, then ASSERT().\r
bitwise OR, and returns the result.\r
\r
Performs a bitwise AND between the bit field specified by StartBit and EndBit\r
- in Operand and the value specified by AndData, followed by a bitwise \r
+ in Operand and the value specified by AndData, followed by a bitwise\r
OR with value specified by OrData. All other bits in Operand are\r
preserved. The new 8-bit value is returned.\r
\r
bitwise OR, and returns the result.\r
\r
Performs a bitwise AND between the bit field specified by StartBit and EndBit\r
- in Operand and the value specified by AndData, followed by a bitwise \r
+ in Operand and the value specified by AndData, followed by a bitwise\r
OR with value specified by OrData. All other bits in Operand are\r
preserved. The new 16-bit value is returned.\r
\r
bitwise OR, and returns the result.\r
\r
Performs a bitwise AND between the bit field specified by StartBit and EndBit\r
- in Operand and the value specified by AndData, followed by a bitwise \r
+ in Operand and the value specified by AndData, followed by a bitwise\r
OR with value specified by OrData. All other bits in Operand are\r
preserved. The new 32-bit value is returned.\r
\r
bitwise OR, and returns the result.\r
\r
Performs a bitwise AND between the bit field specified by StartBit and EndBit\r
- in Operand and the value specified by AndData, followed by a bitwise \r
+ in Operand and the value specified by AndData, followed by a bitwise\r
OR with value specified by OrData. All other bits in Operand are\r
preserved. The new 64-bit value is returned.\r
\r
IN UINT64 OrData\r
);\r
\r
+/**\r
+ Reads a bit field from a 32-bit value, counts and returns\r
+ the number of set bits.\r
+\r
+ Counts the number of set bits in the bit field specified by\r
+ StartBit and EndBit in Operand. The count is returned.\r
+\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+\r
+ @return The number of bits set between StartBit and EndBit.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+BitFieldCountOnes32 (\r
+ IN UINT32 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ );\r
+\r
+/**\r
+ Reads a bit field from a 64-bit value, counts and returns\r
+ the number of set bits.\r
+\r
+ Counts the number of set bits in the bit field specified by\r
+ StartBit and EndBit in Operand. The count is returned.\r
+\r
+ If StartBit is greater than 63, then ASSERT().\r
+ If EndBit is greater than 63, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..63.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..63.\r
+\r
+ @return The number of bits set between StartBit and EndBit.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+BitFieldCountOnes64 (\r
+ IN UINT64 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ );\r
+\r
//\r
// Base Library Checksum Functions\r
//\r
\r
If JumpBuffer is NULL, then ASSERT().\r
For Itanium processors, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().\r
- \r
+\r
NOTE: The structure BASE_LIBRARY_JUMP_BUFFER is CPU architecture specific.\r
The same structure must never be used for more than one CPU architecture context.\r
- For example, a BASE_LIBRARY_JUMP_BUFFER allocated by an IA-32 module must never be used from an x64 module. \r
- SetJump()/LongJump() is not currently supported for the EBC processor type. \r
+ For example, a BASE_LIBRARY_JUMP_BUFFER allocated by an IA-32 module must never be used from an x64 module.\r
+ SetJump()/LongJump() is not currently supported for the EBC processor type.\r
\r
@param JumpBuffer A pointer to CPU context buffer.\r
\r
@retval 0 Indicates a return from SetJump().\r
\r
**/\r
+RETURNS_TWICE\r
UINTN\r
EFIAPI\r
SetJump (\r
function.\r
@param NewStack A pointer to the new stack to use for the EntryPoint\r
function.\r
- @param ... This variable argument list is ignored for IA-32, x64, and \r
- EBC architectures. For Itanium processors, this variable \r
- argument list is expected to contain a single parameter of \r
+ @param ... This variable argument list is ignored for IA-32, x64, and\r
+ EBC architectures. For Itanium processors, this variable\r
+ argument list is expected to contain a single parameter of\r
type VOID * that specifies the new backing store pointer.\r
\r
\r
CpuDeadLoop (\r
VOID\r
);\r
- \r
-#if defined (MDE_CPU_IPF)\r
-\r
-/**\r
- Flush a range of cache lines in the cache coherency domain of the calling\r
- CPU.\r
-\r
- Flushes the cache lines specified by Address and Length. If Address is not aligned \r
- on a cache line boundary, then entire cache line containing Address is flushed. \r
- If Address + Length is not aligned on a cache line boundary, then the entire cache \r
- line containing Address + Length - 1 is flushed. This function may choose to flush \r
- the entire cache if that is more efficient than flushing the specified range. If \r
- Length is 0, the no cache lines are flushed. Address is returned. \r
- This function is only available on Itanium processors.\r
-\r
- If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
-\r
- @param Address The base address of the instruction lines to invalidate. If\r
- the CPU is in a physical addressing mode, then Address is a\r
- physical address. If the CPU is in a virtual addressing mode,\r
- then Address is a virtual address.\r
-\r
- @param Length The number of bytes to invalidate from the instruction cache.\r
-\r
- @return Address.\r
-\r
-**/\r
-VOID *\r
-EFIAPI\r
-AsmFlushCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
- );\r
-\r
-\r
-/**\r
- Executes an FC instruction.\r
- Executes an FC instruction on the cache line specified by Address.\r
- The cache line size affected is at least 32-bytes (aligned on a 32-byte boundary).\r
- An implementation may flush a larger region. This function is only available on Itanium processors.\r
-\r
- @param Address The Address of cache line to be flushed.\r
-\r
- @return The address of FC instruction executed.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmFc (\r
- IN UINT64 Address\r
- );\r
-\r
-\r
-/**\r
- Executes an FC.I instruction.\r
- Executes an FC.I instruction on the cache line specified by Address.\r
- The cache line size affected is at least 32-bytes (aligned on a 32-byte boundary).\r
- An implementation may flush a larger region. This function is only available on Itanium processors.\r
-\r
- @param Address The Address of cache line to be flushed.\r
-\r
- @return The address of the FC.I instruction executed.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmFci (\r
- IN UINT64 Address\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of a Processor Identifier Register (CPUID).\r
- \r
- Reads and returns the current value of Processor Identifier Register specified by Index. \r
- The Index of largest implemented CPUID (One less than the number of implemented CPUID\r
- registers) is determined by CPUID [3] bits {7:0}.\r
- No parameter checking is performed on Index. If the Index value is beyond the\r
- implemented CPUID register range, a Reserved Register/Field fault may occur. The caller\r
- must either guarantee that Index is valid, or the caller must set up fault handlers to\r
- catch the faults. This function is only available on Itanium processors.\r
-\r
- @param Index The 8-bit Processor Identifier Register index to read.\r
-\r
- @return The current value of Processor Identifier Register specified by Index.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadCpuid (\r
- IN UINT8 Index\r
- );\r
\r
\r
/**\r
- Reads the current value of 64-bit Processor Status Register (PSR).\r
- This function is only available on Itanium processors.\r
+ Uses as a barrier to stop speculative execution.\r
\r
- @return The current value of PSR.\r
+ Ensures that no later instruction will execute speculatively, until all prior\r
+ instructions have completed.\r
\r
**/\r
-UINT64\r
+VOID\r
EFIAPI\r
-AsmReadPsr (\r
+SpeculationBarrier (\r
VOID\r
);\r
\r
\r
-/**\r
- Writes the current value of 64-bit Processor Status Register (PSR).\r
-\r
- No parameter checking is performed on Value. All bits of Value corresponding to\r
- reserved fields of PSR must be 0 or a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Value is valid, or the caller must set up\r
- fault handlers to catch the faults. This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to PSR.\r
-\r
- @return The 64-bit value written to the PSR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWritePsr (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of 64-bit Kernel Register #0 (KR0).\r
- \r
- Reads and returns the current value of KR0. \r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of KR0.\r
+#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)\r
+///\r
+/// IA32 and x64 Specific Functions.\r
+/// Byte packed structure for 16-bit Real Mode EFLAGS.\r
+///\r
+typedef union {\r
+ struct {\r
+ UINT32 CF:1; ///< Carry Flag.\r
+ UINT32 Reserved_0:1; ///< Reserved.\r
+ UINT32 PF:1; ///< Parity Flag.\r
+ UINT32 Reserved_1:1; ///< Reserved.\r
+ UINT32 AF:1; ///< Auxiliary Carry Flag.\r
+ UINT32 Reserved_2:1; ///< Reserved.\r
+ UINT32 ZF:1; ///< Zero Flag.\r
+ UINT32 SF:1; ///< Sign Flag.\r
+ UINT32 TF:1; ///< Trap Flag.\r
+ UINT32 IF:1; ///< Interrupt Enable Flag.\r
+ UINT32 DF:1; ///< Direction Flag.\r
+ UINT32 OF:1; ///< Overflow Flag.\r
+ UINT32 IOPL:2; ///< I/O Privilege Level.\r
+ UINT32 NT:1; ///< Nested Task.\r
+ UINT32 Reserved_3:1; ///< Reserved.\r
+ } Bits;\r
+ UINT16 Uint16;\r
+} IA32_FLAGS16;\r
\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadKr0 (\r
- VOID\r
- );\r
+///\r
+/// Byte packed structure for EFLAGS/RFLAGS.\r
+/// 32-bits on IA-32.\r
+/// 64-bits on x64. The upper 32-bits on x64 are reserved.\r
+///\r
+typedef union {\r
+ struct {\r
+ UINT32 CF:1; ///< Carry Flag.\r
+ UINT32 Reserved_0:1; ///< Reserved.\r
+ UINT32 PF:1; ///< Parity Flag.\r
+ UINT32 Reserved_1:1; ///< Reserved.\r
+ UINT32 AF:1; ///< Auxiliary Carry Flag.\r
+ UINT32 Reserved_2:1; ///< Reserved.\r
+ UINT32 ZF:1; ///< Zero Flag.\r
+ UINT32 SF:1; ///< Sign Flag.\r
+ UINT32 TF:1; ///< Trap Flag.\r
+ UINT32 IF:1; ///< Interrupt Enable Flag.\r
+ UINT32 DF:1; ///< Direction Flag.\r
+ UINT32 OF:1; ///< Overflow Flag.\r
+ UINT32 IOPL:2; ///< I/O Privilege Level.\r
+ UINT32 NT:1; ///< Nested Task.\r
+ UINT32 Reserved_3:1; ///< Reserved.\r
+ UINT32 RF:1; ///< Resume Flag.\r
+ UINT32 VM:1; ///< Virtual 8086 Mode.\r
+ UINT32 AC:1; ///< Alignment Check.\r
+ UINT32 VIF:1; ///< Virtual Interrupt Flag.\r
+ UINT32 VIP:1; ///< Virtual Interrupt Pending.\r
+ UINT32 ID:1; ///< ID Flag.\r
+ UINT32 Reserved_4:10; ///< Reserved.\r
+ } Bits;\r
+ UINTN UintN;\r
+} IA32_EFLAGS32;\r
\r
-\r
-/**\r
- Reads the current value of 64-bit Kernel Register #1 (KR1).\r
-\r
- Reads and returns the current value of KR1. \r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of KR1.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadKr1 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of 64-bit Kernel Register #2 (KR2).\r
-\r
- Reads and returns the current value of KR2. \r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of KR2.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadKr2 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of 64-bit Kernel Register #3 (KR3).\r
-\r
- Reads and returns the current value of KR3. \r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of KR3.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadKr3 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of 64-bit Kernel Register #4 (KR4).\r
-\r
- Reads and returns the current value of KR4. \r
- This function is only available on Itanium processors.\r
- \r
- @return The current value of KR4.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadKr4 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of 64-bit Kernel Register #5 (KR5).\r
-\r
- Reads and returns the current value of KR5. \r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of KR5.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadKr5 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of 64-bit Kernel Register #6 (KR6).\r
-\r
- Reads and returns the current value of KR6. \r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of KR6.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadKr6 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of 64-bit Kernel Register #7 (KR7).\r
-\r
- Reads and returns the current value of KR7. \r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of KR7.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadKr7 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Write the current value of 64-bit Kernel Register #0 (KR0).\r
- \r
- Writes the current value of KR0. The 64-bit value written to \r
- the KR0 is returned. This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to KR0.\r
-\r
- @return The 64-bit value written to the KR0.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteKr0 (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Write the current value of 64-bit Kernel Register #1 (KR1).\r
-\r
- Writes the current value of KR1. The 64-bit value written to \r
- the KR1 is returned. This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to KR1.\r
-\r
- @return The 64-bit value written to the KR1.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteKr1 (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Write the current value of 64-bit Kernel Register #2 (KR2).\r
-\r
- Writes the current value of KR2. The 64-bit value written to \r
- the KR2 is returned. This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to KR2.\r
-\r
- @return The 64-bit value written to the KR2.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteKr2 (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Write the current value of 64-bit Kernel Register #3 (KR3).\r
-\r
- Writes the current value of KR3. The 64-bit value written to \r
- the KR3 is returned. This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to KR3.\r
-\r
- @return The 64-bit value written to the KR3.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteKr3 (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Write the current value of 64-bit Kernel Register #4 (KR4).\r
-\r
- Writes the current value of KR4. The 64-bit value written to \r
- the KR4 is returned. This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to KR4.\r
-\r
- @return The 64-bit value written to the KR4.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteKr4 (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Write the current value of 64-bit Kernel Register #5 (KR5).\r
-\r
- Writes the current value of KR5. The 64-bit value written to \r
- the KR5 is returned. This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to KR5.\r
-\r
- @return The 64-bit value written to the KR5.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteKr5 (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Write the current value of 64-bit Kernel Register #6 (KR6).\r
-\r
- Writes the current value of KR6. The 64-bit value written to \r
- the KR6 is returned. This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to KR6.\r
-\r
- @return The 64-bit value written to the KR6.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteKr6 (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Write the current value of 64-bit Kernel Register #7 (KR7).\r
-\r
- Writes the current value of KR7. The 64-bit value written to \r
- the KR7 is returned. This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to KR7.\r
-\r
- @return The 64-bit value written to the KR7.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteKr7 (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Interval Timer Counter Register (ITC).\r
- \r
- Reads and returns the current value of ITC.\r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of ITC.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadItc (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Interval Timer Vector Register (ITV).\r
- \r
- Reads and returns the current value of ITV. \r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of ITV.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadItv (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Interval Timer Match Register (ITM).\r
- \r
- Reads and returns the current value of ITM.\r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of ITM.\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadItm (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Interval Timer Counter Register (ITC).\r
- \r
- Writes the current value of ITC. The 64-bit value written to the ITC is returned. \r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to ITC.\r
-\r
- @return The 64-bit value written to the ITC.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteItc (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Interval Timer Match Register (ITM).\r
- \r
- Writes the current value of ITM. The 64-bit value written to the ITM is returned. \r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to ITM.\r
-\r
- @return The 64-bit value written to the ITM.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteItm (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Interval Timer Vector Register (ITV).\r
- \r
- Writes the current value of ITV. The 64-bit value written to the ITV is returned. \r
- No parameter checking is performed on Value. All bits of Value corresponding to\r
- reserved fields of ITV must be 0 or a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Value is valid, or the caller must set up\r
- fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to ITV.\r
-\r
- @return The 64-bit value written to the ITV.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteItv (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Default Control Register (DCR).\r
- \r
- Reads and returns the current value of DCR. This function is only available on Itanium processors.\r
-\r
- @return The current value of DCR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadDcr (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Interruption Vector Address Register (IVA).\r
- \r
- Reads and returns the current value of IVA. This function is only available on Itanium processors.\r
-\r
- @return The current value of IVA.\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadIva (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Page Table Address Register (PTA).\r
- \r
- Reads and returns the current value of PTA. This function is only available on Itanium processors.\r
-\r
- @return The current value of PTA.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadPta (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Default Control Register (DCR).\r
- \r
- Writes the current value of DCR. The 64-bit value written to the DCR is returned. \r
- No parameter checking is performed on Value. All bits of Value corresponding to\r
- reserved fields of DCR must be 0 or a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Value is valid, or the caller must set up\r
- fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to DCR.\r
-\r
- @return The 64-bit value written to the DCR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteDcr (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Interruption Vector Address Register (IVA).\r
- \r
- Writes the current value of IVA. The 64-bit value written to the IVA is returned. \r
- The size of vector table is 32 K bytes and is 32 K bytes aligned\r
- the low 15 bits of Value is ignored when written.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to IVA.\r
-\r
- @return The 64-bit value written to the IVA.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteIva (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Page Table Address Register (PTA).\r
- \r
- Writes the current value of PTA. The 64-bit value written to the PTA is returned. \r
- No parameter checking is performed on Value. All bits of Value corresponding to\r
- reserved fields of DCR must be 0 or a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Value is valid, or the caller must set up\r
- fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to PTA.\r
-\r
- @return The 64-bit value written to the PTA.\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWritePta (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Local Interrupt ID Register (LID).\r
- \r
- Reads and returns the current value of LID. This function is only available on Itanium processors.\r
-\r
- @return The current value of LID.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadLid (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of External Interrupt Vector Register (IVR).\r
- \r
- Reads and returns the current value of IVR. This function is only available on Itanium processors. \r
-\r
- @return The current value of IVR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadIvr (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Task Priority Register (TPR).\r
- \r
- Reads and returns the current value of TPR. This function is only available on Itanium processors. \r
-\r
- @return The current value of TPR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadTpr (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of External Interrupt Request Register #0 (IRR0).\r
- \r
- Reads and returns the current value of IRR0. This function is only available on Itanium processors. \r
-\r
- @return The current value of IRR0.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadIrr0 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of External Interrupt Request Register #1 (IRR1).\r
- \r
- Reads and returns the current value of IRR1. This function is only available on Itanium processors. \r
-\r
- @return The current value of IRR1.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadIrr1 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of External Interrupt Request Register #2 (IRR2).\r
- \r
- Reads and returns the current value of IRR2. This function is only available on Itanium processors.\r
-\r
- @return The current value of IRR2.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadIrr2 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of External Interrupt Request Register #3 (IRR3).\r
- \r
- Reads and returns the current value of IRR3. This function is only available on Itanium processors. \r
-\r
- @return The current value of IRR3.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadIrr3 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Performance Monitor Vector Register (PMV).\r
- \r
- Reads and returns the current value of PMV. This function is only available on Itanium processors. \r
-\r
- @return The current value of PMV.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadPmv (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Corrected Machine Check Vector Register (CMCV).\r
- \r
- Reads and returns the current value of CMCV. This function is only available on Itanium processors.\r
-\r
- @return The current value of CMCV.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadCmcv (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Local Redirection Register #0 (LRR0).\r
- \r
- Reads and returns the current value of LRR0. This function is only available on Itanium processors. \r
-\r
- @return The current value of LRR0.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadLrr0 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Local Redirection Register #1 (LRR1).\r
- \r
- Reads and returns the current value of LRR1. This function is only available on Itanium processors.\r
-\r
- @return The current value of LRR1.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadLrr1 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Page Local Interrupt ID Register (LID).\r
- \r
- Writes the current value of LID. The 64-bit value written to the LID is returned. \r
- No parameter checking is performed on Value. All bits of Value corresponding to\r
- reserved fields of LID must be 0 or a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Value is valid, or the caller must set up\r
- fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to LID.\r
-\r
- @return The 64-bit value written to the LID.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteLid (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Task Priority Register (TPR).\r
- \r
- Writes the current value of TPR. The 64-bit value written to the TPR is returned. \r
- No parameter checking is performed on Value. All bits of Value corresponding to\r
- reserved fields of TPR must be 0 or a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Value is valid, or the caller must set up\r
- fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to TPR.\r
-\r
- @return The 64-bit value written to the TPR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteTpr (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Performs a write operation on End OF External Interrupt Register (EOI).\r
- \r
- Writes a value of 0 to the EOI Register. This function is only available on Itanium processors.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-AsmWriteEoi (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Performance Monitor Vector Register (PMV).\r
- \r
- Writes the current value of PMV. The 64-bit value written to the PMV is returned. \r
- No parameter checking is performed on Value. All bits of Value corresponding\r
- to reserved fields of PMV must be 0 or a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Value is valid, or the caller must set up\r
- fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to PMV.\r
-\r
- @return The 64-bit value written to the PMV.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWritePmv (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Corrected Machine Check Vector Register (CMCV).\r
- \r
- Writes the current value of CMCV. The 64-bit value written to the CMCV is returned. \r
- No parameter checking is performed on Value. All bits of Value corresponding\r
- to reserved fields of CMCV must be 0 or a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Value is valid, or the caller must set up\r
- fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to CMCV.\r
-\r
- @return The 64-bit value written to the CMCV.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteCmcv (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Local Redirection Register #0 (LRR0).\r
- \r
- Writes the current value of LRR0. The 64-bit value written to the LRR0 is returned. \r
- No parameter checking is performed on Value. All bits of Value corresponding\r
- to reserved fields of LRR0 must be 0 or a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Value is valid, or the caller must set up\r
- fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to LRR0.\r
-\r
- @return The 64-bit value written to the LRR0.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteLrr0 (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Local Redirection Register #1 (LRR1).\r
- \r
- Writes the current value of LRR1. The 64-bit value written to the LRR1 is returned. \r
- No parameter checking is performed on Value. All bits of Value corresponding\r
- to reserved fields of LRR1 must be 0 or a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Value is valid, or the caller must\r
- set up fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to LRR1.\r
-\r
- @return The 64-bit value written to the LRR1.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteLrr1 (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Instruction Breakpoint Register (IBR).\r
- \r
- The Instruction Breakpoint Registers are used in pairs. The even numbered\r
- registers contain breakpoint addresses, and the odd numbered registers contain\r
- breakpoint mask conditions. At least four instruction registers pairs are implemented\r
- on all processor models. Implemented registers are contiguous starting with\r
- register 0. No parameter checking is performed on Index, and if the Index value\r
- is beyond the implemented IBR register range, a Reserved Register/Field fault may\r
- occur. The caller must either guarantee that Index is valid, or the caller must\r
- set up fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Index The 8-bit Instruction Breakpoint Register index to read.\r
-\r
- @return The current value of Instruction Breakpoint Register specified by Index.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadIbr (\r
- IN UINT8 Index\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Data Breakpoint Register (DBR).\r
-\r
- The Data Breakpoint Registers are used in pairs. The even numbered registers\r
- contain breakpoint addresses, and odd numbered registers contain breakpoint\r
- mask conditions. At least four data registers pairs are implemented on all processor\r
- models. Implemented registers are contiguous starting with register 0.\r
- No parameter checking is performed on Index. If the Index value is beyond\r
- the implemented DBR register range, a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Index is valid, or the caller must set up\r
- fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Index The 8-bit Data Breakpoint Register index to read.\r
-\r
- @return The current value of Data Breakpoint Register specified by Index.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadDbr (\r
- IN UINT8 Index\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Performance Monitor Configuration Register (PMC).\r
-\r
- All processor implementations provide at least four performance counters\r
- (PMC/PMD [4]...PMC/PMD [7] pairs), and four performance monitor counter overflow\r
- status registers (PMC [0]... PMC [3]). Processor implementations may provide\r
- additional implementation-dependent PMC and PMD to increase the number of\r
- 'generic' performance counters (PMC/PMD pairs). The remainder of PMC and PMD\r
- register set is implementation dependent. No parameter checking is performed\r
- on Index. If the Index value is beyond the implemented PMC register range,\r
- zero value will be returned.\r
- This function is only available on Itanium processors.\r
-\r
- @param Index The 8-bit Performance Monitor Configuration Register index to read.\r
-\r
- @return The current value of Performance Monitor Configuration Register\r
- specified by Index.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadPmc (\r
- IN UINT8 Index\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Performance Monitor Data Register (PMD).\r
-\r
- All processor implementations provide at least 4 performance counters\r
- (PMC/PMD [4]...PMC/PMD [7] pairs), and 4 performance monitor counter\r
- overflow status registers (PMC [0]... PMC [3]). Processor implementations may\r
- provide additional implementation-dependent PMC and PMD to increase the number\r
- of 'generic' performance counters (PMC/PMD pairs). The remainder of PMC and PMD\r
- register set is implementation dependent. No parameter checking is performed\r
- on Index. If the Index value is beyond the implemented PMD register range,\r
- zero value will be returned.\r
- This function is only available on Itanium processors.\r
-\r
- @param Index The 8-bit Performance Monitor Data Register index to read.\r
-\r
- @return The current value of Performance Monitor Data Register specified by Index.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadPmd (\r
- IN UINT8 Index\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Instruction Breakpoint Register (IBR).\r
-\r
- Writes current value of Instruction Breakpoint Register specified by Index.\r
- The Instruction Breakpoint Registers are used in pairs. The even numbered\r
- registers contain breakpoint addresses, and odd numbered registers contain\r
- breakpoint mask conditions. At least four instruction registers pairs are implemented\r
- on all processor models. Implemented registers are contiguous starting with\r
- register 0. No parameter checking is performed on Index. If the Index value\r
- is beyond the implemented IBR register range, a Reserved Register/Field fault may\r
- occur. The caller must either guarantee that Index is valid, or the caller must\r
- set up fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Index The 8-bit Instruction Breakpoint Register index to write.\r
- @param Value The 64-bit value to write to IBR.\r
-\r
- @return The 64-bit value written to the IBR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteIbr (\r
- IN UINT8 Index,\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Data Breakpoint Register (DBR).\r
-\r
- Writes current value of Data Breakpoint Register specified by Index.\r
- The Data Breakpoint Registers are used in pairs. The even numbered registers\r
- contain breakpoint addresses, and odd numbered registers contain breakpoint\r
- mask conditions. At least four data registers pairs are implemented on all processor\r
- models. Implemented registers are contiguous starting with register 0. No parameter\r
- checking is performed on Index. If the Index value is beyond the implemented\r
- DBR register range, a Reserved Register/Field fault may occur. The caller must\r
- either guarantee that Index is valid, or the caller must set up fault handlers to\r
- catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Index The 8-bit Data Breakpoint Register index to write.\r
- @param Value The 64-bit value to write to DBR.\r
-\r
- @return The 64-bit value written to the DBR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteDbr (\r
- IN UINT8 Index,\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Performance Monitor Configuration Register (PMC).\r
-\r
- Writes current value of Performance Monitor Configuration Register specified by Index.\r
- All processor implementations provide at least four performance counters\r
- (PMC/PMD [4]...PMC/PMD [7] pairs), and four performance monitor counter overflow status\r
- registers (PMC [0]... PMC [3]). Processor implementations may provide additional\r
- implementation-dependent PMC and PMD to increase the number of 'generic' performance\r
- counters (PMC/PMD pairs). The remainder of PMC and PMD register set is implementation\r
- dependent. No parameter checking is performed on Index. If the Index value is\r
- beyond the implemented PMC register range, the write is ignored.\r
- This function is only available on Itanium processors.\r
-\r
- @param Index The 8-bit Performance Monitor Configuration Register index to write.\r
- @param Value The 64-bit value to write to PMC.\r
-\r
- @return The 64-bit value written to the PMC.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWritePmc (\r
- IN UINT8 Index,\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Performance Monitor Data Register (PMD).\r
-\r
- Writes current value of Performance Monitor Data Register specified by Index.\r
- All processor implementations provide at least four performance counters\r
- (PMC/PMD [4]...PMC/PMD [7] pairs), and four performance monitor counter overflow\r
- status registers (PMC [0]... PMC [3]). Processor implementations may provide\r
- additional implementation-dependent PMC and PMD to increase the number of 'generic'\r
- performance counters (PMC/PMD pairs). The remainder of PMC and PMD register set\r
- is implementation dependent. No parameter checking is performed on Index. If the\r
- Index value is beyond the implemented PMD register range, the write is ignored.\r
- This function is only available on Itanium processors.\r
-\r
- @param Index The 8-bit Performance Monitor Data Register index to write.\r
- @param Value The 64-bit value to write to PMD.\r
-\r
- @return The 64-bit value written to the PMD.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWritePmd (\r
- IN UINT8 Index,\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of 64-bit Global Pointer (GP).\r
-\r
- Reads and returns the current value of GP.\r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of GP.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadGp (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Write the current value of 64-bit Global Pointer (GP).\r
-\r
- Writes the current value of GP. The 64-bit value written to the GP is returned.\r
- No parameter checking is performed on Value.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to GP.\r
-\r
- @return The 64-bit value written to the GP.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteGp (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of 64-bit Stack Pointer (SP).\r
-\r
- Reads and returns the current value of SP.\r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of SP.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadSp (\r
- VOID\r
- );\r
-\r
-\r
-///\r
-/// Valid Index value for AsmReadControlRegister().\r
-///\r
-#define IPF_CONTROL_REGISTER_DCR 0\r
-#define IPF_CONTROL_REGISTER_ITM 1\r
-#define IPF_CONTROL_REGISTER_IVA 2\r
-#define IPF_CONTROL_REGISTER_PTA 8\r
-#define IPF_CONTROL_REGISTER_IPSR 16\r
-#define IPF_CONTROL_REGISTER_ISR 17\r
-#define IPF_CONTROL_REGISTER_IIP 19\r
-#define IPF_CONTROL_REGISTER_IFA 20\r
-#define IPF_CONTROL_REGISTER_ITIR 21\r
-#define IPF_CONTROL_REGISTER_IIPA 22\r
-#define IPF_CONTROL_REGISTER_IFS 23\r
-#define IPF_CONTROL_REGISTER_IIM 24\r
-#define IPF_CONTROL_REGISTER_IHA 25\r
-#define IPF_CONTROL_REGISTER_LID 64\r
-#define IPF_CONTROL_REGISTER_IVR 65\r
-#define IPF_CONTROL_REGISTER_TPR 66\r
-#define IPF_CONTROL_REGISTER_EOI 67\r
-#define IPF_CONTROL_REGISTER_IRR0 68\r
-#define IPF_CONTROL_REGISTER_IRR1 69\r
-#define IPF_CONTROL_REGISTER_IRR2 70\r
-#define IPF_CONTROL_REGISTER_IRR3 71\r
-#define IPF_CONTROL_REGISTER_ITV 72\r
-#define IPF_CONTROL_REGISTER_PMV 73\r
-#define IPF_CONTROL_REGISTER_CMCV 74\r
-#define IPF_CONTROL_REGISTER_LRR0 80\r
-#define IPF_CONTROL_REGISTER_LRR1 81\r
-\r
-/**\r
- Reads a 64-bit control register.\r
-\r
- Reads and returns the control register specified by Index. The valid Index valued \r
- are defined above in "Related Definitions".\r
- If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned. This function is only \r
- available on Itanium processors.\r
-\r
- @param Index The index of the control register to read.\r
-\r
- @return The control register specified by Index.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadControlRegister (\r
- IN UINT64 Index\r
- );\r
-\r
-\r
-///\r
-/// Valid Index value for AsmReadApplicationRegister().\r
-///\r
-#define IPF_APPLICATION_REGISTER_K0 0\r
-#define IPF_APPLICATION_REGISTER_K1 1\r
-#define IPF_APPLICATION_REGISTER_K2 2\r
-#define IPF_APPLICATION_REGISTER_K3 3\r
-#define IPF_APPLICATION_REGISTER_K4 4\r
-#define IPF_APPLICATION_REGISTER_K5 5\r
-#define IPF_APPLICATION_REGISTER_K6 6\r
-#define IPF_APPLICATION_REGISTER_K7 7\r
-#define IPF_APPLICATION_REGISTER_RSC 16\r
-#define IPF_APPLICATION_REGISTER_BSP 17\r
-#define IPF_APPLICATION_REGISTER_BSPSTORE 18\r
-#define IPF_APPLICATION_REGISTER_RNAT 19\r
-#define IPF_APPLICATION_REGISTER_FCR 21\r
-#define IPF_APPLICATION_REGISTER_EFLAG 24\r
-#define IPF_APPLICATION_REGISTER_CSD 25\r
-#define IPF_APPLICATION_REGISTER_SSD 26\r
-#define IPF_APPLICATION_REGISTER_CFLG 27\r
-#define IPF_APPLICATION_REGISTER_FSR 28\r
-#define IPF_APPLICATION_REGISTER_FIR 29\r
-#define IPF_APPLICATION_REGISTER_FDR 30\r
-#define IPF_APPLICATION_REGISTER_CCV 32\r
-#define IPF_APPLICATION_REGISTER_UNAT 36\r
-#define IPF_APPLICATION_REGISTER_FPSR 40\r
-#define IPF_APPLICATION_REGISTER_ITC 44\r
-#define IPF_APPLICATION_REGISTER_PFS 64\r
-#define IPF_APPLICATION_REGISTER_LC 65\r
-#define IPF_APPLICATION_REGISTER_EC 66\r
-\r
-/**\r
- Reads a 64-bit application register.\r
-\r
- Reads and returns the application register specified by Index. The valid Index \r
- valued are defined above in "Related Definitions".\r
- If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned. This function is only \r
- available on Itanium processors.\r
-\r
- @param Index The index of the application register to read.\r
-\r
- @return The application register specified by Index.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadApplicationRegister (\r
- IN UINT64 Index\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of a Machine Specific Register (MSR).\r
-\r
- Reads and returns the current value of the Machine Specific Register specified by Index. No\r
- parameter checking is performed on Index, and if the Index value is beyond the implemented MSR\r
- register range, a Reserved Register/Field fault may occur. The caller must either guarantee that\r
- Index is valid, or the caller must set up fault handlers to catch the faults. This function is\r
- only available on Itanium processors.\r
-\r
- @param Index The 8-bit Machine Specific Register index to read.\r
-\r
- @return The current value of the Machine Specific Register specified by Index. \r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadMsr (\r
- IN UINT8 Index \r
- );\r
-\r
-\r
-/**\r
- Writes the current value of a Machine Specific Register (MSR).\r
-\r
- Writes Value to the Machine Specific Register specified by Index. Value is returned. No\r
- parameter checking is performed on Index, and if the Index value is beyond the implemented MSR\r
- register range, a Reserved Register/Field fault may occur. The caller must either guarantee that\r
- Index is valid, or the caller must set up fault handlers to catch the faults. This function is\r
- only available on Itanium processors.\r
-\r
- @param Index The 8-bit Machine Specific Register index to write.\r
- @param Value The 64-bit value to write to the Machine Specific Register.\r
-\r
- @return The 64-bit value to write to the Machine Specific Register. \r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteMsr (\r
- IN UINT8 Index, \r
- IN UINT64 Value \r
- );\r
-\r
-\r
-/**\r
- Determines if the CPU is currently executing in virtual, physical, or mixed mode.\r
-\r
- Determines the current execution mode of the CPU.\r
- If the CPU is in virtual mode(PSR.RT=1, PSR.DT=1, PSR.IT=1), then 1 is returned.\r
- If the CPU is in physical mode(PSR.RT=0, PSR.DT=0, PSR.IT=0), then 0 is returned.\r
- If the CPU is not in physical mode or virtual mode, then it is in mixed mode,\r
- and -1 is returned.\r
- This function is only available on Itanium processors.\r
-\r
- @retval 1 The CPU is in virtual mode.\r
- @retval 0 The CPU is in physical mode.\r
- @retval -1 The CPU is in mixed mode.\r
-\r
-**/\r
-INT64\r
-EFIAPI\r
-AsmCpuVirtual (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Makes a PAL procedure call.\r
-\r
- This is a wrapper function to make a PAL procedure call. Based on the Index\r
- value this API will make static or stacked PAL call. The following table\r
- describes the usage of PAL Procedure Index Assignment. Architected procedures\r
- may be designated as required or optional. If a PAL procedure is specified\r
- as optional, a unique return code of 0xFFFFFFFFFFFFFFFF is returned in the\r
- Status field of the PAL_CALL_RETURN structure.\r
- This indicates that the procedure is not present in this PAL implementation.\r
- It is the caller's responsibility to check for this return code after calling\r
- any optional PAL procedure.\r
- No parameter checking is performed on the 5 input parameters, but there are\r
- some common rules that the caller should follow when making a PAL call. Any\r
- address passed to PAL as buffers for return parameters must be 8-byte aligned.\r
- Unaligned addresses may cause undefined results. For those parameters defined\r
- as reserved or some fields defined as reserved must be zero filled or the invalid\r
- argument return value may be returned or undefined result may occur during the\r
- execution of the procedure. If the PalEntryPoint does not point to a valid\r
- PAL entry point then the system behavior is undefined. This function is only\r
- available on Itanium processors.\r
-\r
- @param PalEntryPoint The PAL procedure calls entry point.\r
- @param Index The PAL procedure Index number.\r
- @param Arg2 The 2nd parameter for PAL procedure calls.\r
- @param Arg3 The 3rd parameter for PAL procedure calls.\r
- @param Arg4 The 4th parameter for PAL procedure calls.\r
-\r
- @return structure returned from the PAL Call procedure, including the status and return value.\r
-\r
-**/\r
-PAL_CALL_RETURN\r
-EFIAPI\r
-AsmPalCall (\r
- IN UINT64 PalEntryPoint,\r
- IN UINT64 Index,\r
- IN UINT64 Arg2,\r
- IN UINT64 Arg3,\r
- IN UINT64 Arg4\r
- );\r
-#endif\r
-\r
-#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)\r
-///\r
-/// IA32 and x64 Specific Functions.\r
-/// Byte packed structure for 16-bit Real Mode EFLAGS.\r
-///\r
-typedef union {\r
- struct {\r
- UINT32 CF:1; ///< Carry Flag.\r
- UINT32 Reserved_0:1; ///< Reserved.\r
- UINT32 PF:1; ///< Parity Flag.\r
- UINT32 Reserved_1:1; ///< Reserved.\r
- UINT32 AF:1; ///< Auxiliary Carry Flag.\r
- UINT32 Reserved_2:1; ///< Reserved.\r
- UINT32 ZF:1; ///< Zero Flag.\r
- UINT32 SF:1; ///< Sign Flag.\r
- UINT32 TF:1; ///< Trap Flag.\r
- UINT32 IF:1; ///< Interrupt Enable Flag.\r
- UINT32 DF:1; ///< Direction Flag.\r
- UINT32 OF:1; ///< Overflow Flag.\r
- UINT32 IOPL:2; ///< I/O Privilege Level.\r
- UINT32 NT:1; ///< Nested Task.\r
- UINT32 Reserved_3:1; ///< Reserved.\r
- } Bits;\r
- UINT16 Uint16;\r
-} IA32_FLAGS16;\r
-\r
-///\r
-/// Byte packed structure for EFLAGS/RFLAGS.\r
-/// 32-bits on IA-32.\r
-/// 64-bits on x64. The upper 32-bits on x64 are reserved.\r
-///\r
-typedef union {\r
- struct {\r
- UINT32 CF:1; ///< Carry Flag.\r
- UINT32 Reserved_0:1; ///< Reserved.\r
- UINT32 PF:1; ///< Parity Flag.\r
- UINT32 Reserved_1:1; ///< Reserved.\r
- UINT32 AF:1; ///< Auxiliary Carry Flag.\r
- UINT32 Reserved_2:1; ///< Reserved.\r
- UINT32 ZF:1; ///< Zero Flag.\r
- UINT32 SF:1; ///< Sign Flag.\r
- UINT32 TF:1; ///< Trap Flag.\r
- UINT32 IF:1; ///< Interrupt Enable Flag.\r
- UINT32 DF:1; ///< Direction Flag.\r
- UINT32 OF:1; ///< Overflow Flag.\r
- UINT32 IOPL:2; ///< I/O Privilege Level.\r
- UINT32 NT:1; ///< Nested Task.\r
- UINT32 Reserved_3:1; ///< Reserved.\r
- UINT32 RF:1; ///< Resume Flag.\r
- UINT32 VM:1; ///< Virtual 8086 Mode.\r
- UINT32 AC:1; ///< Alignment Check.\r
- UINT32 VIF:1; ///< Virtual Interrupt Flag.\r
- UINT32 VIP:1; ///< Virtual Interrupt Pending.\r
- UINT32 ID:1; ///< ID Flag.\r
- UINT32 Reserved_4:10; ///< Reserved.\r
- } Bits;\r
- UINTN UintN;\r
-} IA32_EFLAGS32;\r
-\r
-///\r
-/// Byte packed structure for Control Register 0 (CR0).\r
-/// 32-bits on IA-32.\r
-/// 64-bits on x64. The upper 32-bits on x64 are reserved.\r
-///\r
-typedef union {\r
- struct {\r
- UINT32 PE:1; ///< Protection Enable.\r
- UINT32 MP:1; ///< Monitor Coprocessor.\r
- UINT32 EM:1; ///< Emulation.\r
- UINT32 TS:1; ///< Task Switched.\r
- UINT32 ET:1; ///< Extension Type.\r
- UINT32 NE:1; ///< Numeric Error.\r
- UINT32 Reserved_0:10; ///< Reserved.\r
- UINT32 WP:1; ///< Write Protect.\r
- UINT32 Reserved_1:1; ///< Reserved.\r
- UINT32 AM:1; ///< Alignment Mask.\r
- UINT32 Reserved_2:10; ///< Reserved.\r
- UINT32 NW:1; ///< Mot Write-through.\r
- UINT32 CD:1; ///< Cache Disable.\r
- UINT32 PG:1; ///< Paging.\r
- } Bits;\r
- UINTN UintN;\r
-} IA32_CR0;\r
+///\r
+/// Byte packed structure for Control Register 0 (CR0).\r
+/// 32-bits on IA-32.\r
+/// 64-bits on x64. The upper 32-bits on x64 are reserved.\r
+///\r
+typedef union {\r
+ struct {\r
+ UINT32 PE:1; ///< Protection Enable.\r
+ UINT32 MP:1; ///< Monitor Coprocessor.\r
+ UINT32 EM:1; ///< Emulation.\r
+ UINT32 TS:1; ///< Task Switched.\r
+ UINT32 ET:1; ///< Extension Type.\r
+ UINT32 NE:1; ///< Numeric Error.\r
+ UINT32 Reserved_0:10; ///< Reserved.\r
+ UINT32 WP:1; ///< Write Protect.\r
+ UINT32 Reserved_1:1; ///< Reserved.\r
+ UINT32 AM:1; ///< Alignment Mask.\r
+ UINT32 Reserved_2:10; ///< Reserved.\r
+ UINT32 NW:1; ///< Mot Write-through.\r
+ UINT32 CD:1; ///< Cache Disable.\r
+ UINT32 PG:1; ///< Paging.\r
+ } Bits;\r
+ UINTN UintN;\r
+} IA32_CR0;\r
\r
///\r
/// Byte packed structure for Control Register 4 (CR4).\r
UINT32 OSXMMEXCPT:1; ///< Operating System Support for\r
///< Unmasked SIMD Floating Point\r
///< Exceptions.\r
- UINT32 Reserved_0:2; ///< Reserved.\r
+ UINT32 Reserved_2:1; ///< Reserved.\r
+ UINT32 LA57:1; ///< Linear Address 57bit.\r
UINT32 VMXE:1; ///< VMX Enable\r
UINT32 Reserved_1:18; ///< Reserved.\r
} Bits;\r
typedef struct {\r
UINT16 PreviousTaskLink;\r
UINT16 Reserved_2;\r
- UINT32 Esp0;\r
- UINT16 Ss0;\r
+ UINT32 ESP0;\r
+ UINT16 SS0;\r
UINT16 Reserved_10;\r
- UINT32 Esp1;\r
- UINT16 Ss1;\r
+ UINT32 ESP1;\r
+ UINT16 SS1;\r
UINT16 Reserved_18;\r
- UINT32 Esp2;\r
- UINT16 Ss2;\r
+ UINT32 ESP2;\r
+ UINT16 SS2;\r
UINT16 Reserved_26;\r
- UINT32 Cr3;\r
- UINT32 Eip;\r
- UINT32 Eflags;\r
- UINT32 Eax;\r
- UINT32 Ecx;\r
- UINT32 Edx;\r
- UINT32 Ebx;\r
- UINT32 Esp;\r
- UINT32 Ebp;\r
- UINT32 Esi;\r
- UINT32 Edi;\r
- UINT16 Es;\r
+ UINT32 CR3;\r
+ UINT32 EIP;\r
+ UINT32 EFLAGS;\r
+ UINT32 EAX;\r
+ UINT32 ECX;\r
+ UINT32 EDX;\r
+ UINT32 EBX;\r
+ UINT32 ESP;\r
+ UINT32 EBP;\r
+ UINT32 ESI;\r
+ UINT32 EDI;\r
+ UINT16 ES;\r
UINT16 Reserved_74;\r
- UINT16 Cs;\r
+ UINT16 CS;\r
UINT16 Reserved_78;\r
- UINT16 Ss;\r
+ UINT16 SS;\r
UINT16 Reserved_82;\r
- UINT16 Ds;\r
+ UINT16 DS;\r
UINT16 Reserved_86;\r
- UINT16 Fs;\r
+ UINT16 FS;\r
UINT16 Reserved_90;\r
- UINT16 Gs;\r
+ UINT16 GS;\r
UINT16 Reserved_94;\r
UINT16 LDTSegmentSelector;\r
UINT16 Reserved_98;\r
- UINT16 Tflag;\r
+ UINT16 T;\r
UINT16 IOMapBaseAddress;\r
} IA32_TASK_STATE_SEGMENT;\r
\r
UINT32 BaseMid:8; ///< Base Address 23..16\r
UINT32 Type:4; ///< Type (1 0 B 1)\r
UINT32 Reserved_43:1; ///< 0\r
- UINT32 Dpl:2; ///< Descriptor Privilege Level\r
- UINT32 Present:1; ///< Segment Present\r
+ UINT32 DPL:2; ///< Descriptor Privilege Level\r
+ UINT32 P:1; ///< Segment Present\r
UINT32 LimitHigh:4; ///< Segment Limit 19..16\r
- UINT32 Avl:1; ///< Available for use by system software\r
+ UINT32 AVL:1; ///< Available for use by system software\r
UINT32 Reserved_52:2; ///< 0 0\r
- UINT32 Granularity:1; ///< Granularity\r
+ UINT32 G:1; ///< Granularity\r
UINT32 BaseHigh:8; ///< Base Address 31..24\r
} Bits;\r
UINT64 Uint64;\r
} IA32_TSS_DESCRIPTOR;\r
#pragma pack ()\r
\r
-#endif\r
+#endif // defined (MDE_CPU_IA32)\r
\r
#if defined (MDE_CPU_X64)\r
///\r
struct {\r
UINT64 Uint64;\r
UINT64 Uint64_1;\r
- } Uint128; \r
+ } Uint128;\r
} IA32_IDT_GATE_DESCRIPTOR;\r
\r
#pragma pack (1)\r
//\r
typedef struct {\r
UINT32 Reserved_0;\r
- UINT64 Rsp0;\r
- UINT64 Rsp1;\r
- UINT64 Rsp2;\r
+ UINT64 RSP0;\r
+ UINT64 RSP1;\r
+ UINT64 RSP2;\r
UINT64 Reserved_28;\r
- UINT64 Ist[7];\r
+ UINT64 IST[7];\r
UINT64 Reserved_92;\r
UINT16 Reserved_100;\r
UINT16 IOMapBaseAddress;\r
UINT32 BaseMidl:8; ///< Base Address 23..16\r
UINT32 Type:4; ///< Type (1 0 B 1)\r
UINT32 Reserved_43:1; ///< 0\r
- UINT32 Dpl:2; ///< Descriptor Privilege Level\r
- UINT32 Present:1; ///< Segment Present\r
+ UINT32 DPL:2; ///< Descriptor Privilege Level\r
+ UINT32 P:1; ///< Segment Present\r
UINT32 LimitHigh:4; ///< Segment Limit 19..16\r
- UINT32 Avl:1; ///< Available for use by system software\r
+ UINT32 AVL:1; ///< Available for use by system software\r
UINT32 Reserved_52:2; ///< 0 0\r
- UINT32 Granularity:1; ///< Granularity\r
+ UINT32 G:1; ///< Granularity\r
UINT32 BaseMidh:8; ///< Base Address 31..24\r
UINT32 BaseHigh:32; ///< Base Address 63..32\r
UINT32 Reserved_96:32; ///< Reserved\r
} IA32_TSS_DESCRIPTOR;\r
#pragma pack ()\r
\r
-#endif\r
+#endif // defined (MDE_CPU_X64)\r
\r
///\r
/// Byte packed structure for an FP/SSE/SSE2 context.\r
#define THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 0x00000002\r
#define THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL 0x00000004\r
\r
+///\r
+/// Type definition for representing labels in NASM source code that allow for\r
+/// the patching of immediate operands of IA32 and X64 instructions.\r
+///\r
+/// While the type is technically defined as a function type (note: not a\r
+/// pointer-to-function type), such labels in NASM source code never stand for\r
+/// actual functions, and identifiers declared with this function type should\r
+/// never be called. This is also why the EFIAPI calling convention specifier\r
+/// is missing from the typedef, and why the typedef does not follow the usual\r
+/// edk2 coding style for function (or pointer-to-function) typedefs. The VOID\r
+/// return type and the VOID argument list are merely artifacts.\r
+///\r
+typedef VOID (X86_ASSEMBLY_PATCH_LABEL) (VOID);\r
+\r
/**\r
Retrieves CPUID information.\r
\r
Writes Value to a bit field in the lower 32-bits of a 64-bit MSR. The bit\r
field is specified by the StartBit and the EndBit. All other bits in the\r
destination MSR are preserved. The lower 32-bits of the MSR written is\r
- returned. The caller must either guarantee that Index and the data written \r
- is valid, or the caller must set up exception handlers to catch the exceptions. \r
+ returned. The caller must either guarantee that Index and the data written\r
+ is valid, or the caller must set up exception handlers to catch the exceptions.\r
This function is only available on IA-32 and x64.\r
\r
If StartBit is greater than 31, then ASSERT().\r
\r
\r
/**\r
- Reads a 64-bit MSR, performs a bitwise AND followed by a bitwise \r
+ Reads a 64-bit MSR, performs a bitwise AND followed by a bitwise\r
OR, and writes the result back to the 64-bit MSR.\r
\r
Reads the 64-bit MSR specified by Index, performs a bitwise AND between read\r
\r
Writes Value to a bit field in a 64-bit MSR. The bit field is specified by\r
the StartBit and the EndBit. All other bits in the destination MSR are\r
- preserved. The MSR written is returned. The caller must either guarantee \r
- that Index and the data written is valid, or the caller must set up exception \r
+ preserved. The MSR written is returned. The caller must either guarantee\r
+ that Index and the data written is valid, or the caller must set up exception\r
handlers to catch the exceptions. This function is only available on IA-32 and x64.\r
\r
If StartBit is greater than 63, then ASSERT().\r
in ExtraStackSize. If parameters are passed to the 16-bit real mode code,\r
then the actual minimum stack size is ExtraStackSize plus the maximum number\r
of bytes that need to be passed to the 16-bit real mode code.\r
- \r
+\r
If RealModeBufferSize is NULL, then ASSERT().\r
If ExtraStackSize is NULL, then ASSERT().\r
\r
Prepares all structures a code required to use AsmThunk16().\r
\r
Prepares all structures and code required to use AsmThunk16().\r
- \r
+\r
This interface is limited to be used in either physical mode or virtual modes with paging enabled where the\r
virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.\r
\r
AsmPrepareThunk16() must be called with ThunkContext before this function is used.\r
This function must be called with interrupts disabled.\r
\r
- The register state from the RealModeState field of ThunkContext is restored just prior \r
- to calling the 16-bit real mode entry point. This includes the EFLAGS field of RealModeState, \r
+ The register state from the RealModeState field of ThunkContext is restored just prior\r
+ to calling the 16-bit real mode entry point. This includes the EFLAGS field of RealModeState,\r
which is used to set the interrupt state when a 16-bit real mode entry point is called.\r
Control is transferred to the 16-bit real mode entry point specified by the CS and Eip fields of RealModeState.\r
- The stack is initialized to the SS and ESP fields of RealModeState. Any parameters passed to \r
- the 16-bit real mode code must be populated by the caller at SS:ESP prior to calling this function. \r
+ The stack is initialized to the SS and ESP fields of RealModeState. Any parameters passed to\r
+ the 16-bit real mode code must be populated by the caller at SS:ESP prior to calling this function.\r
The 16-bit real mode entry point is invoked with a 16-bit CALL FAR instruction,\r
- so when accessing stack contents, the 16-bit real mode code must account for the 16-bit segment \r
- and 16-bit offset of the return address that were pushed onto the stack. The 16-bit real mode entry \r
- point must exit with a RETF instruction. The register state is captured into RealModeState immediately \r
+ so when accessing stack contents, the 16-bit real mode code must account for the 16-bit segment\r
+ and 16-bit offset of the return address that were pushed onto the stack. The 16-bit real mode entry\r
+ point must exit with a RETF instruction. The register state is captured into RealModeState immediately\r
after the RETF instruction is executed.\r
- \r
- If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts, \r
- or any of the 16-bit real mode code makes a SW interrupt, then the caller is responsible for making sure \r
- the IDT at address 0 is initialized to handle any HW or SW interrupts that may occur while in 16-bit real mode. \r
- \r
- If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts, \r
- then the caller is responsible for making sure the 8259 PIC is in a state compatible with 16-bit real mode. \r
+\r
+ If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,\r
+ or any of the 16-bit real mode code makes a SW interrupt, then the caller is responsible for making sure\r
+ the IDT at address 0 is initialized to handle any HW or SW interrupts that may occur while in 16-bit real mode.\r
+\r
+ If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,\r
+ then the caller is responsible for making sure the 8259 PIC is in a state compatible with 16-bit real mode.\r
This includes the base vectors, the interrupt masks, and the edge/level trigger mode.\r
- \r
- If THUNK_ATTRIBUTE_BIG_REAL_MODE is set in the ThunkAttributes field of ThunkContext, then the user code \r
+\r
+ If THUNK_ATTRIBUTE_BIG_REAL_MODE is set in the ThunkAttributes field of ThunkContext, then the user code\r
is invoked in big real mode. Otherwise, the user code is invoked in 16-bit real mode with 64KB segment limits.\r
- \r
- If neither THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 nor THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in \r
- ThunkAttributes, then it is assumed that the user code did not enable the A20 mask, and no attempt is made to \r
+\r
+ If neither THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 nor THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in\r
+ ThunkAttributes, then it is assumed that the user code did not enable the A20 mask, and no attempt is made to\r
disable the A20 mask.\r
- \r
- If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is set and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is clear in \r
- ThunkAttributes, then attempt to use the INT 15 service to disable the A20 mask. If this INT 15 call fails, \r
+\r
+ If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is set and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is clear in\r
+ ThunkAttributes, then attempt to use the INT 15 service to disable the A20 mask. If this INT 15 call fails,\r
then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.\r
- \r
- If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is clear and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is set in \r
+\r
+ If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is clear and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is set in\r
ThunkAttributes, then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.\r
- \r
+\r
If ThunkContext is NULL, then ASSERT().\r
If AsmPrepareThunk16() was not previously called with ThunkContext, then ASSERT().\r
- If both THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in \r
+ If both THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in\r
ThunkAttributes, then ASSERT().\r
\r
This interface is limited to be used in either physical mode or virtual modes with paging enabled where the\r
IN UINT16 Selector\r
);\r
\r
-#endif\r
-#endif\r
+/**\r
+ Performs a serializing operation on all load-from-memory instructions that\r
+ were issued prior the AsmLfence function.\r
+\r
+ Executes a LFENCE instruction. This function is only available on IA-32 and x64.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmLfence (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ Patch the immediate operand of an IA32 or X64 instruction such that the byte,\r
+ word, dword or qword operand is encoded at the end of the instruction's\r
+ binary representation.\r
+\r
+ This function should be used to update object code that was compiled with\r
+ NASM from assembly source code. Example:\r
+\r
+ NASM source code:\r
+\r
+ mov eax, strict dword 0 ; the imm32 zero operand will be patched\r
+ ASM_PFX(gPatchCr3):\r
+ mov cr3, eax\r
\r
+ C source code:\r
+\r
+ X86_ASSEMBLY_PATCH_LABEL gPatchCr3;\r
+ PatchInstructionX86 (gPatchCr3, AsmReadCr3 (), 4);\r
+\r
+ @param[out] InstructionEnd Pointer right past the instruction to patch. The\r
+ immediate operand to patch is expected to\r
+ comprise the trailing bytes of the instruction.\r
+ If InstructionEnd is closer to address 0 than\r
+ ValueSize permits, then ASSERT().\r
+\r
+ @param[in] PatchValue The constant to write to the immediate operand.\r
+ The caller is responsible for ensuring that\r
+ PatchValue can be represented in the byte, word,\r
+ dword or qword operand (as indicated through\r
+ ValueSize); otherwise ASSERT().\r
+\r
+ @param[in] ValueSize The size of the operand in bytes; must be 1, 2,\r
+ 4, or 8. ASSERT() otherwise.\r
+**/\r
+VOID\r
+EFIAPI\r
+PatchInstructionX86 (\r
+ OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,\r
+ IN UINT64 PatchValue,\r
+ IN UINTN ValueSize\r
+ );\r
\r
+#endif // defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)\r
+#endif // !defined (__BASE_LIB__)\r