UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm

[mirror_edk2.git] / MdePkg / Include / Library / CacheMaintenanceLib.h

diff --git a/MdePkg/Include/Library/CacheMaintenanceLib.h b/MdePkg/Include/Library/CacheMaintenanceLib.h
index a5c690f80440a152c8688d94dc798af9dfb637ed..9afb0a787de431ea8c5180ea336dc53fac49fa7b 100644 (file)
--- a/MdePkg/Include/Library/CacheMaintenanceLib.h
+++ b/MdePkg/Include/Library/CacheMaintenanceLib.h
@@ -1,17 +1,11 @@
 /** @file\r
   Provides services to maintain instruction and data caches.\r
-  \r
+\r
   The Cache Maintenance Library provides abstractions for basic processor cache operations.\r
   It removes the need to use assembly in C code.\r
-    \r
-Copyright (c) 2006 - 2008, Intel Corporation\r
-All rights reserved. This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution.  The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
 \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
 \r
@@ -22,9 +16,6 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   Invalidates the entire instruction cache in cache coherency domain of the\r
   calling CPU.\r
 \r
-  Invalidates the entire instruction cache in cache coherency domain of the\r
-  calling CPU.\r
-\r
 **/\r
 VOID\r
 EFIAPI\r
@@ -42,7 +33,7 @@ InvalidateInstructionCache (
   aligned on a cache line boundary, then the entire instruction cache line\r
   containing Address + Length -1 is invalidated. This function may choose to\r
   invalidate the entire instruction cache if that is more efficient than\r
-  invalidating the specified range. If Length is 0, the no instruction cache\r
+  invalidating the specified range. If Length is 0, then no instruction cache\r
   lines are invalidated. Address is returned.\r
 \r
   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
@@ -54,14 +45,14 @@ InvalidateInstructionCache (
 \r
   @param  Length  The number of bytes to invalidate from the instruction cache.\r
 \r
-  @return Address\r
+  @return Address.\r
 \r
 **/\r
 VOID *\r
 EFIAPI\r
 InvalidateInstructionCacheRange (\r
-  IN      VOID                      *Address,\r
-  IN      UINTN                     Length\r
+  IN      VOID   *Address,\r
+  IN      UINTN  Length\r
   );\r
 \r
 /**\r
@@ -91,7 +82,7 @@ WriteBackInvalidateDataCache (
   line containing Address + Length -1 is written back and invalidated. This\r
   function may choose to write back and invalidate the entire data cache if\r
   that is more efficient than writing back and invalidating the specified\r
-  range. If Length is 0, the no data cache lines are written back and\r
+  range. If Length is 0, then no data cache lines are written back and\r
   invalidated. Address is returned.\r
 \r
   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
@@ -103,14 +94,14 @@ WriteBackInvalidateDataCache (
   @param  Length  The number of bytes to write back and invalidate from the\r
                   data cache.\r
 \r
-  @return Address\r
+  @return Address of cache invalidation.\r
 \r
 **/\r
 VOID *\r
 EFIAPI\r
 WriteBackInvalidateDataCacheRange (\r
-  IN      VOID                      *Address,\r
-  IN      UINTN                     Length\r
+  IN      VOID   *Address,\r
+  IN      UINTN  Length\r
   );\r
 \r
 /**\r
@@ -139,7 +130,7 @@ WriteBackDataCache (
   cache line boundary, then the entire data cache line containing Address +\r
   Length -1 is written back. This function may choose to write back the entire\r
   data cache if that is more efficient than writing back the specified range.\r
-  If Length is 0, the no data cache lines are written back. This function may\r
+  If Length is 0, then no data cache lines are written back. This function may\r
   also invalidate all the data cache lines in the specified range of the cache\r
   coherency domain of the calling CPU. Address is returned.\r
 \r
@@ -151,14 +142,14 @@ WriteBackDataCache (
                   mode, then Address is a virtual address.\r
   @param  Length  The number of bytes to write back from the data cache.\r
 \r
-  @return Address\r
+  @return Address of cache written in main memory.\r
 \r
 **/\r
 VOID *\r
 EFIAPI\r
 WriteBackDataCacheRange (\r
-  IN      VOID                      *Address,\r
-  IN      UINTN                     Length\r
+  IN      VOID   *Address,\r
+  IN      UINTN  Length\r
   );\r
 \r
 /**\r
@@ -202,14 +193,14 @@ InvalidateDataCache (
                   then Address is a virtual address.\r
   @param  Length  The number of bytes to invalidate from the data cache.\r
 \r
-  @return Address\r
+  @return Address.\r
 \r
 **/\r
 VOID *\r
 EFIAPI\r
 InvalidateDataCacheRange (\r
-  IN      VOID                      *Address,\r
-  IN      UINTN                     Length\r
+  IN      VOID   *Address,\r
+  IN      UINTN  Length\r
   );\r
 \r
 #endif\r