/** @file\r
Provides services to access PCI Configuration Space using the MMIO PCI Express window.\r
+ \r
+ This library is identical to the PCI Library, except the access method for performing PCI \r
+ configuration cycles must be though the 256 MB PCI Express MMIO window whose base address\r
+ is defined by PcdPciExpressBaseAddress.\r
\r
-Copyright (c) 2006 - 2008, Intel Corporation\r
+Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) \\r
(((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\r
\r
+/**\r
+ Register a PCI device so PCI configuration registers may be accessed after \r
+ SetVirtualAddressMap().\r
+ \r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+\r
+ @param Address Address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+ \r
+ @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r
+ @retval RETURN_UNSUPPORTED An attempt was made to call this function \r
+ after ExitBootServices().\r
+ @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r
+ at runtime could not be mapped.\r
+ @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r
+ complete the registration.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+PciExpressRegisterForRuntimeAccess (\r
+ IN UINTN Address\r
+ );\r
+\r
/**\r
Reads an 8-bit PCI configuration register.\r
\r
@param Size Size in bytes of the transfer.\r
@param Buffer Pointer to a buffer receiving the data read.\r
\r
- @return Size read daata from StartAddress.\r
+ @return Size read data from StartAddress.\r
\r
**/\r
UINTN\r