/** @file\r
- PCI Library Services for PCI Segment #0\r
-\r
- Copyright (c) 2006, Intel Corporation\r
- All rights reserved. This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ Provides services to access PCI Configuration Space.\r
+ \r
+ These functions perform PCI configuration cycles using the default PCI configuration \r
+ access method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, \r
+ or it may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some \r
+ alternate access method. Modules will typically use the PCI Library for its PCI configuration \r
+ accesses. However, if a module requires a mix of PCI access methods, the PCI CF8 Library or \r
+ PCI Express Library may be used in conjunction with the PCI Library. The functionality of \r
+ these three libraries is identical. The PCI CF8 Library and PCI Express Library simply use \r
+ explicit access methods.\r
+\r
+Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#define PCI_LIB_ADDRESS(Bus,Device,Function,Offset) \\r
(((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\r
\r
+/**\r
+ Register a PCI device so PCI configuration registers may be accessed after \r
+ SetVirtualAddressMap().\r
+ \r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+\r
+ @param Address Address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+ \r
+ @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r
+ @retval RETURN_UNSUPPORTED An attempt was made to call this function \r
+ after ExitBootServices().\r
+ @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r
+ at runtime could not be mapped.\r
+ @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r
+ complete the registration.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+PciRegisterForRuntimeAccess (\r
+ IN UINTN Address\r
+ );\r
+\r
/**\r
Reads an 8-bit PCI configuration register.\r
\r
EFIAPI\r
PciWrite8 (\r
IN UINTN Address,\r
- IN UINT8 Data\r
+ IN UINT8 Value\r
);\r
\r
/**\r
EFIAPI\r
PciWrite16 (\r
IN UINTN Address,\r
- IN UINT16 Data\r
+ IN UINT16 Value\r
);\r
\r
/**\r
EFIAPI\r
PciWrite32 (\r
IN UINTN Address,\r
- IN UINT32 Data\r
+ IN UINT32 Value\r
);\r
\r
/**\r
@param Size Size in bytes of the transfer.\r
@param Buffer Pointer to a buffer containing the data to write.\r
\r
- @return Size\r
+ @return Size written to StartAddress.\r
\r
**/\r
UINTN\r