WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
@par Revision Reference:\r
- This PPI is defined in PI\r
- Version 1.00.\r
+ This PPI is introduced in PI Version 1.0.\r
\r
**/\r
\r
/// EFI_PEI_PCI_CFG_PPI_WIDTH\r
///\r
typedef enum {\r
+ ///\r
+ /// 8-bit access\r
+ ///\r
EfiPeiPciCfgWidthUint8 = 0,\r
+ ///\r
+ /// 16-bit access\r
+ ///\r
EfiPeiPciCfgWidthUint16 = 1,\r
+ ///\r
+ /// 32-bit access\r
+ ///\r
EfiPeiPciCfgWidthUint32 = 2,\r
+ ///\r
+ /// 64-bit access\r
+ ///\r
EfiPeiPciCfgWidthUint64 = 3,\r
EfiPeiPciCfgWidthMaximum\r
} EFI_PEI_PCI_CFG_PPI_WIDTH;\r
IN VOID *ClearBits\r
);\r
\r
-/**\r
- @par Ppi Description:\r
- The EFI_PEI_PCI_CFG_PPI interfaces are used to abstract accesses to PCI\r
- controllers behind a PCI root bridge controller.\r
-\r
- @param Read PCI read services. See the Read() function description.\r
-\r
- @param Write PCI write services. See the Write() function description.\r
-\r
- @param Modify PCI read-modify-write services. See the Modify() function description.\r
-\r
- @param Segment The PCI bus segment which the specified functions will access.\r
-\r
-**/\r
+///\r
+/// The EFI_PEI_PCI_CFG_PPI interfaces are used to abstract accesses to PCI\r
+/// controllers behind a PCI root bridge controller.\r
+///\r
struct _EFI_PEI_PCI_CFG2_PPI {\r
EFI_PEI_PCI_CFG2_PPI_IO Read;\r
EFI_PEI_PCI_CFG2_PPI_IO Write;\r
EFI_PEI_PCI_CFG2_PPI_RW Modify;\r
+ ///\r
+ /// The PCI bus segment which the specified functions will access.\r
+ ///\r
UINT16 Segment;\r
};\r
\r