#define EFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (10 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO 0x0020 ///< I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7 (10 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO 0x0040 ///< I/O cycles 0x170-0x177, 0x376, 0x377 (10 bit decode)\r
-#define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080 ///< Map a memory range so write are combined\r
+#define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080 ///< Map a memory range so writes are combined\r
#define EFI_PCI_IO_ATTRIBUTE_IO 0x0100 ///< Enable the I/O decode bit in the PCI Config Header\r
#define EFI_PCI_IO_ATTRIBUTE_MEMORY 0x0200 ///< Enable the Memory decode bit in the PCI Config Header\r
#define EFI_PCI_IO_ATTRIBUTE_BUS_MASTER 0x0400 ///< Enable the DMA bit in the PCI Config Header\r
EfiPciIoOperationBusMasterWrite,\r
///\r
/// Provides both read and write access to system memory by both the processor and a\r
- /// bus master. The buffer is coherent from both the processor¡¯s and the bus master's point of view.\r
+ /// bus master. The buffer is coherent from both the processor's and the bus master's point of view.\r
///\r
EfiPciIoOperationBusMasterCommonBuffer,\r
EfiPciIoOperationMaximum\r
///\r
typedef enum {\r
///\r
- /// Retrieve the PCI controller¡¯s current attributes, and return them in Result.\r
+ /// Retrieve the PCI controller's current attributes, and return them in Result.\r
///\r
EfiPciIoAttributeOperationGet,\r
///\r
- /// Set the PCI controller¡¯s current attributes to Attributes.\r
+ /// Set the PCI controller's current attributes to Attributes.\r
///\r
EfiPciIoAttributeOperationSet,\r
///\r
} EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION;\r
\r
/** \r
- Reads from the memory space of a PCI controller. Returns when either the polling exit criteria is\r
+ Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is\r
satisfied or after a defined duration. \r
\r
@param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
);\r
\r
/** \r
- Provides the PCI controller-Cspecific addresses needed to access system memory.\r
+ Provides the PCI controller-specific addresses needed to access system memory.\r
\r
@param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param Operation Indicates if the bus master is going to read or write to system memory.\r
\r
///\r
/// The EFI_PCI_IO_PROTOCOL provides the basic Memory, I/O, PCI configuration, \r
-/// and DMA interfaces that are used to abstract accesses to PCI controllers. \r
+/// and DMA interfaces used to abstract accesses to PCI controllers. \r
/// There is one EFI_PCI_IO_PROTOCOL instance for each PCI controller on a PCI bus. \r
/// A device driver that wishes to manage a PCI controller in a system will have to \r
/// retrieve the EFI_PCI_IO_PROTOCOL instance that is associated with the PCI controller. \r