Fix the comments in the core interface to follow the UEFI Spec regarding how to check...

[mirror_edk2.git] / MdePkg / Include / Protocol / PciRootBridgeIo.h

diff --git a/MdePkg/Include/Protocol/PciRootBridgeIo.h b/MdePkg/Include/Protocol/PciRootBridgeIo.h
index a563f94aefdf6e524177f456a09affe3a2d08994..449dcba67a8ab225c48a3b5a4a923c99c85d05d2 100644 (file)
--- a/MdePkg/Include/Protocol/PciRootBridgeIo.h
+++ b/MdePkg/Include/Protocol/PciRootBridgeIo.h
@@ -3,10 +3,10 @@
 \r
   PCI Root Bridge I/O protocol is used by PCI Bus Driver to perform PCI Memory, PCI I/O, \r
   and PCI Configuration cycles on a PCI Root Bridge. It also provides services to perform \r
-  defferent types of bus mastering DMA\r
+  defferent types of bus mastering DMA.\r
 \r
-  Copyright (c) 2006 - 2008, Intel Corporation                                                         \r
-  All rights reserved. This program and the accompanying materials                          \r
+  Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials                          \r
   are licensed and made available under the terms and conditions of the BSD License         \r
   which accompanies this distribution.  The full text of the license may be found at        \r
   http://opensource.org/licenses/bsd-license.php                                            \r
@@ -19,6 +19,8 @@
 #ifndef __PCI_ROOT_BRIDGE_IO_H__\r
 #define __PCI_ROOT_BRIDGE_IO_H__\r
 \r
+#include <Library/BaseLib.h>\r
+\r
 #define EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID \\r
   { \\r
     0x2f707ebb, 0x4a1a, 0x11d4, {0x9a, 0x38, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \\r
@@ -97,13 +99,20 @@ typedef enum {
 #define EFI_PCI_ATTRIBUTE_MEMORY_CACHED               0x0800\r
 #define EFI_PCI_ATTRIBUTE_MEMORY_DISABLE              0x1000\r
 #define EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE          0x8000\r
+#define EFI_PCI_ATTRIBUTE_ISA_IO_16                   0x10000\r
+#define EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16           0x20000\r
+#define EFI_PCI_ATTRIBUTE_VGA_IO_16                   0x40000\r
 \r
 #define EFI_PCI_ATTRIBUTE_VALID_FOR_ALLOCATE_BUFFER   (EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE | EFI_PCI_ATTRIBUTE_MEMORY_CACHED | EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE)\r
 \r
 #define EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER (~EFI_PCI_ATTRIBUTE_VALID_FOR_ALLOCATE_BUFFER)\r
 \r
 #define EFI_PCI_ADDRESS(bus, dev, func, reg) \\r
-    ((UINT64) ((((UINTN) bus) << 24) + (((UINTN) dev) << 16) + (((UINTN) func) << 8) + ((UINTN) reg)))\r
+  (UINT64) ( \\r
+  (((UINTN) bus) << 24) | \\r
+  (((UINTN) dev) << 16) | \\r
+  (((UINTN) func) << 8) | \\r
+  (((UINTN) (reg)) < 256 ? ((UINTN) (reg)) : (UINT64) (LShiftU64 ((UINT64) (reg), 32))))\r
 \r
 typedef struct {\r
   UINT8   Register;\r
@@ -169,7 +178,13 @@ EFI_STATUS
   );\r
 \r
 typedef struct {\r
+  ///\r
+  /// Read PCI controller registers in the PCI root bridge memory space.\r
+  ///\r
   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM  Read;\r
+  ///\r
+  /// Write PCI controller registers in the PCI root bridge memory space.\r
+  ///\r
   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM  Write;\r
 } EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS;\r
 \r
@@ -199,7 +214,7 @@ EFI_STATUS
   );\r
 \r
 /**                                                                 \r
-  Provides the PCI controller-Cspecific addresses required to access system memory from a\r
+  Provides the PCI controller-specific addresses required to access system memory from a\r
   DMA bus master.                                                                        \r
             \r
   @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r