According to the latest UEFI 2.3 errata B, the following changes are made:

[mirror_edk2.git] / MdePkg / Include / Protocol / PciRootBridgeIo.h

diff --git a/MdePkg/Include/Protocol/PciRootBridgeIo.h b/MdePkg/Include/Protocol/PciRootBridgeIo.h
index 6554cd3324706062432be730ad8bc99c7920a5c5..56999e0ef0b8a6d3f456ee9a7ce69366d29a86ed 100644 (file)
--- a/MdePkg/Include/Protocol/PciRootBridgeIo.h
+++ b/MdePkg/Include/Protocol/PciRootBridgeIo.h
@@ -3,7 +3,7 @@
 \r
   PCI Root Bridge I/O protocol is used by PCI Bus Driver to perform PCI Memory, PCI I/O, \r
   and PCI Configuration cycles on a PCI Root Bridge. It also provides services to perform \r
-  defferent types of bus mastering DMA\r
+  defferent types of bus mastering DMA.\r
 \r
   Copyright (c) 2006 - 2008, Intel Corporation                                                         \r
   All rights reserved. This program and the accompanying materials                          \r
@@ -26,6 +26,11 @@
 \r
 typedef struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL;\r
 \r
+///\r
+/// *******************************************************\r
+/// EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH\r
+/// *******************************************************\r
+///\r
 typedef enum {\r
   EfiPciWidthUint8,\r
   EfiPciWidthUint16,\r
@@ -42,12 +47,41 @@ typedef enum {
   EfiPciWidthMaximum\r
 } EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH;\r
 \r
+///\r
+/// *******************************************************\r
+/// EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION\r
+/// *******************************************************\r
+///\r
 typedef enum {\r
+  ///\r
+  /// A read operation from system memory by a bus master that is not capable of producing\r
+  /// PCI dual address cycles.\r
+  ///\r
   EfiPciOperationBusMasterRead,\r
+  ///\r
+  /// A write operation from system memory by a bus master that is not capable of producing\r
+  /// PCI dual address cycles.\r
+  ///\r
   EfiPciOperationBusMasterWrite,\r
+  ///\r
+  /// Provides both read and write access to system memory by both the processor and a bus\r
+  /// master that is not capable of producing PCI dual address cycles.\r
+  ///\r
   EfiPciOperationBusMasterCommonBuffer,\r
+  ///\r
+  /// A read operation from system memory by a bus master that is capable of producing PCI\r
+  /// dual address cycles.\r
+  ///\r
   EfiPciOperationBusMasterRead64,\r
+  ///\r
+  /// A write operation to system memory by a bus master that is capable of producing PCI\r
+  /// dual address cycles.\r
+  ///\r
   EfiPciOperationBusMasterWrite64,\r
+  ///\r
+  /// Provides both read and write access to system memory by both the processor and a bus\r
+  /// master that is capable of producing PCI dual address cycles.\r
+  ///\r
   EfiPciOperationBusMasterCommonBuffer64,\r
   EfiPciOperationMaximum\r
 } EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION;\r
@@ -135,7 +169,13 @@ EFI_STATUS
   );\r
 \r
 typedef struct {\r
+  ///\r
+  /// Read PCI controller registers in the PCI root bridge memory space.\r
+  ///\r
   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM  Read;\r
+  ///\r
+  /// Write PCI controller registers in the PCI root bridge memory space.\r
+  ///\r
   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM  Write;\r
 } EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS;\r
 \r
@@ -165,7 +205,7 @@ EFI_STATUS
   );\r
 \r
 /**                                                                 \r
-  Provides the PCI controller-Cspecific addresses required to access system memory from a\r
+  Provides the PCI controller-specific addresses required to access system memory from a\r
   DMA bus master.                                                                        \r
             \r
   @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
@@ -358,11 +398,10 @@ EFI_STATUS
   OUT VOID                                     **Resources\r
   );\r
 \r
-/**  \r
-  @par Protocol Description:\r
-  Provides the basic Memory, I/O, PCI configuration, and DMA interfaces that are \r
-  used to abstract accesses to PCI controllers behind a PCI Root Bridge Controller. \r
-**/\r
+///\r
+/// Provides the basic Memory, I/O, PCI configuration, and DMA interfaces that are \r
+/// used to abstract accesses to PCI controllers behind a PCI Root Bridge Controller. \r
+///\r
 struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL {\r
   ///\r
   /// The EFI_HANDLE of the PCI Host Bridge of which this PCI Root Bridge is a member.\r