@endcode\r
@note MSR_XEON_D_PPIN_CTL is defined as MSR_PPIN_CTL in SDM.\r
**/\r
-#define MSR_XEON_D_PPIN_CTL 0x0000004E\r
+#define MSR_XEON_D_PPIN_CTL 0x0000004E\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_D_PPIN_CTL\r
///\r
/// [Bit 0] LockOut (R/WO) See Table 2-25.\r
///\r
- UINT32 LockOut:1;\r
+ UINT32 LockOut : 1;\r
///\r
/// [Bit 1] Enable_PPIN (R/W) See Table 2-25.\r
///\r
- UINT32 Enable_PPIN:1;\r
- UINT32 Reserved1:30;\r
- UINT32 Reserved2:32;\r
+ UINT32 Enable_PPIN : 1;\r
+ UINT32 Reserved1 : 30;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_PPIN_CTL_REGISTER;\r
\r
-\r
/**\r
Package. Protected Processor Inventory Number (R/O). Protected Processor\r
Inventory Number (R/O) See Table 2-25.\r
@endcode\r
@note MSR_XEON_D_PPIN is defined as MSR_PPIN in SDM.\r
**/\r
-#define MSR_XEON_D_PPIN 0x0000004F\r
-\r
+#define MSR_XEON_D_PPIN 0x0000004F\r
\r
/**\r
Package. See http://biosbits.org.\r
@endcode\r
@note MSR_XEON_D_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
**/\r
-#define MSR_XEON_D_PLATFORM_INFO 0x000000CE\r
+#define MSR_XEON_D_PLATFORM_INFO 0x000000CE\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_D_PLATFORM_INFO\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:8;\r
+ UINT32 Reserved1 : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25.\r
///\r
- UINT32 MaximumNonTurboRatio:8;\r
- UINT32 Reserved2:7;\r
+ UINT32 MaximumNonTurboRatio : 8;\r
+ UINT32 Reserved2 : 7;\r
///\r
/// [Bit 23] Package. PPIN_CAP (R/O) See Table 2-25.\r
///\r
- UINT32 PPIN_CAP:1;\r
- UINT32 Reserved3:4;\r
+ UINT32 PPIN_CAP : 1;\r
+ UINT32 Reserved3 : 4;\r
///\r
/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See\r
/// Table 2-25.\r
///\r
- UINT32 RatioLimit:1;\r
+ UINT32 RatioLimit : 1;\r
///\r
/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See\r
/// Table 2-25.\r
///\r
- UINT32 TDPLimit:1;\r
+ UINT32 TDPLimit : 1;\r
///\r
/// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25.\r
///\r
- UINT32 TJOFFSET:1;\r
- UINT32 Reserved4:1;\r
- UINT32 Reserved5:8;\r
+ UINT32 TJOFFSET : 1;\r
+ UINT32 Reserved4 : 1;\r
+ UINT32 Reserved5 : 8;\r
///\r
/// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25.\r
///\r
- UINT32 MaximumEfficiencyRatio:8;\r
- UINT32 Reserved6:16;\r
+ UINT32 MaximumEfficiencyRatio : 8;\r
+ UINT32 Reserved6 : 16;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_PLATFORM_INFO_REGISTER;\r
\r
-\r
/**\r
Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
specific C-state code names, unrelated to MWAIT extension C-state parameters\r
@endcode\r
@note MSR_XEON_D_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
**/\r
-#define MSR_XEON_D_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+#define MSR_XEON_D_PKG_CST_CONFIG_CONTROL 0x000000E2\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_D_PKG_CST_CONFIG_CONTROL\r
/// 011b: C6 (retention) 111b: No Package C state limits. All C states\r
/// supported by the processor are available.\r
///\r
- UINT32 Limit:3;\r
- UINT32 Reserved1:7;\r
+ UINT32 Limit : 3;\r
+ UINT32 Reserved1 : 7;\r
///\r
/// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
///\r
- UINT32 IO_MWAIT:1;\r
- UINT32 Reserved2:4;\r
+ UINT32 IO_MWAIT : 1;\r
+ UINT32 Reserved2 : 4;\r
///\r
/// [Bit 15] CFG Lock (R/WO).\r
///\r
- UINT32 CFGLock:1;\r
+ UINT32 CFGLock : 1;\r
///\r
/// [Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor\r
/// will convert HALT or MWAT(C1) to MWAIT(C6).\r
///\r
- UINT32 CStateConversion:1;\r
- UINT32 Reserved3:8;\r
+ UINT32 CStateConversion : 1;\r
+ UINT32 Reserved3 : 8;\r
///\r
/// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
///\r
- UINT32 C3AutoDemotion:1;\r
+ UINT32 C3AutoDemotion : 1;\r
///\r
/// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
///\r
- UINT32 C1AutoDemotion:1;\r
+ UINT32 C1AutoDemotion : 1;\r
///\r
/// [Bit 27] Enable C3 Undemotion (R/W).\r
///\r
- UINT32 C3Undemotion:1;\r
+ UINT32 C3Undemotion : 1;\r
///\r
/// [Bit 28] Enable C1 Undemotion (R/W).\r
///\r
- UINT32 C1Undemotion:1;\r
+ UINT32 C1Undemotion : 1;\r
///\r
/// [Bit 29] Package C State Demotion Enable (R/W).\r
///\r
- UINT32 CStateDemotion:1;\r
+ UINT32 CStateDemotion : 1;\r
///\r
/// [Bit 30] Package C State UnDemotion Enable (R/W).\r
///\r
- UINT32 CStateUndemotion:1;\r
- UINT32 Reserved4:1;\r
- UINT32 Reserved5:32;\r
+ UINT32 CStateUndemotion : 1;\r
+ UINT32 Reserved4 : 1;\r
+ UINT32 Reserved5 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER;\r
\r
-\r
/**\r
Thread. Global Machine Check Capability (R/O).\r
\r
@endcode\r
@note MSR_XEON_D_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.\r
**/\r
-#define MSR_XEON_D_IA32_MCG_CAP 0x00000179\r
+#define MSR_XEON_D_IA32_MCG_CAP 0x00000179\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_D_IA32_MCG_CAP\r
///\r
/// [Bits 7:0] Count.\r
///\r
- UINT32 Count:8;\r
+ UINT32 Count : 8;\r
///\r
/// [Bit 8] MCG_CTL_P.\r
///\r
- UINT32 MCG_CTL_P:1;\r
+ UINT32 MCG_CTL_P : 1;\r
///\r
/// [Bit 9] MCG_EXT_P.\r
///\r
- UINT32 MCG_EXT_P:1;\r
+ UINT32 MCG_EXT_P : 1;\r
///\r
/// [Bit 10] MCP_CMCI_P.\r
///\r
- UINT32 MCP_CMCI_P:1;\r
+ UINT32 MCP_CMCI_P : 1;\r
///\r
/// [Bit 11] MCG_TES_P.\r
///\r
- UINT32 MCG_TES_P:1;\r
- UINT32 Reserved1:4;\r
+ UINT32 MCG_TES_P : 1;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bits 23:16] MCG_EXT_CNT.\r
///\r
- UINT32 MCG_EXT_CNT:8;\r
+ UINT32 MCG_EXT_CNT : 8;\r
///\r
/// [Bit 24] MCG_SER_P.\r
///\r
- UINT32 MCG_SER_P:1;\r
+ UINT32 MCG_SER_P : 1;\r
///\r
/// [Bit 25] MCG_EM_P.\r
///\r
- UINT32 MCG_EM_P:1;\r
+ UINT32 MCG_EM_P : 1;\r
///\r
/// [Bit 26] MCG_ELOG_P.\r
///\r
- UINT32 MCG_ELOG_P:1;\r
- UINT32 Reserved2:5;\r
- UINT32 Reserved3:32;\r
+ UINT32 MCG_ELOG_P : 1;\r
+ UINT32 Reserved2 : 5;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_IA32_MCG_CAP_REGISTER;\r
\r
-\r
/**\r
THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r
Enhancement. Accessible only while in SMM.\r
@endcode\r
@note MSR_XEON_D_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r
**/\r
-#define MSR_XEON_D_SMM_MCA_CAP 0x0000017D\r
+#define MSR_XEON_D_SMM_MCA_CAP 0x0000017D\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_D_SMM_MCA_CAP\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:32;\r
- UINT32 Reserved2:26;\r
+ UINT32 Reserved1 : 32;\r
+ UINT32 Reserved2 : 26;\r
///\r
/// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
/// SMM code access restriction is supported and a host-space interface\r
/// available to SMM handler.\r
///\r
- UINT32 SMM_Code_Access_Chk:1;\r
+ UINT32 SMM_Code_Access_Chk : 1;\r
///\r
/// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
/// SMM long flow indicator is supported and a host-space interface\r
/// available to SMM handler.\r
///\r
- UINT32 Long_Flow_Indication:1;\r
- UINT32 Reserved3:4;\r
+ UINT32 Long_Flow_Indication : 1;\r
+ UINT32 Reserved3 : 4;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_SMM_MCA_CAP_REGISTER;\r
\r
-\r
/**\r
Package.\r
\r
@endcode\r
@note MSR_XEON_D_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
**/\r
-#define MSR_XEON_D_TEMPERATURE_TARGET 0x000001A2\r
+#define MSR_XEON_D_TEMPERATURE_TARGET 0x000001A2\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_D_TEMPERATURE_TARGET\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:16;\r
+ UINT32 Reserved1 : 16;\r
///\r
/// [Bits 23:16] Temperature Target (RO) See Table 2-25.\r
///\r
- UINT32 TemperatureTarget:8;\r
+ UINT32 TemperatureTarget : 8;\r
///\r
/// [Bits 27:24] TCC Activation Offset (R/W) See Table 2-25.\r
///\r
- UINT32 TCCActivationOffset:4;\r
- UINT32 Reserved2:4;\r
- UINT32 Reserved3:32;\r
+ UINT32 TCCActivationOffset : 4;\r
+ UINT32 Reserved2 : 4;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_TEMPERATURE_TARGET_REGISTER;\r
\r
-\r
/**\r
Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
RW if MSR_PLATFORM_INFO.[28] = 1.\r
@endcode\r
@note MSR_XEON_D_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
-#define MSR_XEON_D_TURBO_RATIO_LIMIT 0x000001AD\r
+#define MSR_XEON_D_TURBO_RATIO_LIMIT 0x000001AD\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT\r
///\r
/// [Bits 7:0] Package. Maximum Ratio Limit for 1C.\r
///\r
- UINT32 Maximum1C:8;\r
+ UINT32 Maximum1C : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Ratio Limit for 2C.\r
///\r
- UINT32 Maximum2C:8;\r
+ UINT32 Maximum2C : 8;\r
///\r
/// [Bits 23:16] Package. Maximum Ratio Limit for 3C.\r
///\r
- UINT32 Maximum3C:8;\r
+ UINT32 Maximum3C : 8;\r
///\r
/// [Bits 31:24] Package. Maximum Ratio Limit for 4C.\r
///\r
- UINT32 Maximum4C:8;\r
+ UINT32 Maximum4C : 8;\r
///\r
/// [Bits 39:32] Package. Maximum Ratio Limit for 5C.\r
///\r
- UINT32 Maximum5C:8;\r
+ UINT32 Maximum5C : 8;\r
///\r
/// [Bits 47:40] Package. Maximum Ratio Limit for 6C.\r
///\r
- UINT32 Maximum6C:8;\r
+ UINT32 Maximum6C : 8;\r
///\r
/// [Bits 55:48] Package. Maximum Ratio Limit for 7C.\r
///\r
- UINT32 Maximum7C:8;\r
+ UINT32 Maximum7C : 8;\r
///\r
/// [Bits 63:56] Package. Maximum Ratio Limit for 8C.\r
///\r
- UINT32 Maximum8C:8;\r
+ UINT32 Maximum8C : 8;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER;\r
\r
-\r
/**\r
Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
RW if MSR_PLATFORM_INFO.[28] = 1.\r
@endcode\r
@note MSR_XEON_D_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.\r
**/\r
-#define MSR_XEON_D_TURBO_RATIO_LIMIT1 0x000001AE\r
+#define MSR_XEON_D_TURBO_RATIO_LIMIT1 0x000001AE\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT1\r
///\r
/// [Bits 7:0] Package. Maximum Ratio Limit for 9C.\r
///\r
- UINT32 Maximum9C:8;\r
+ UINT32 Maximum9C : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Ratio Limit for 10C.\r
///\r
- UINT32 Maximum10C:8;\r
+ UINT32 Maximum10C : 8;\r
///\r
/// [Bits 23:16] Package. Maximum Ratio Limit for 11C.\r
///\r
- UINT32 Maximum11C:8;\r
+ UINT32 Maximum11C : 8;\r
///\r
/// [Bits 31:24] Package. Maximum Ratio Limit for 12C.\r
///\r
- UINT32 Maximum12C:8;\r
+ UINT32 Maximum12C : 8;\r
///\r
/// [Bits 39:32] Package. Maximum Ratio Limit for 13C.\r
///\r
- UINT32 Maximum13C:8;\r
+ UINT32 Maximum13C : 8;\r
///\r
/// [Bits 47:40] Package. Maximum Ratio Limit for 14C.\r
///\r
- UINT32 Maximum14C:8;\r
+ UINT32 Maximum14C : 8;\r
///\r
/// [Bits 55:48] Package. Maximum Ratio Limit for 15C.\r
///\r
- UINT32 Maximum15C:8;\r
+ UINT32 Maximum15C : 8;\r
///\r
/// [Bits 63:56] Package. Maximum Ratio Limit for 16C.\r
///\r
- UINT32 Maximum16C:8;\r
+ UINT32 Maximum16C : 8;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER;\r
\r
-\r
/**\r
Package. Unit Multipliers used in RAPL Interfaces (R/O).\r
\r
@endcode\r
@note MSR_XEON_D_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
**/\r
-#define MSR_XEON_D_RAPL_POWER_UNIT 0x00000606\r
+#define MSR_XEON_D_RAPL_POWER_UNIT 0x00000606\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_D_RAPL_POWER_UNIT\r
///\r
/// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r
///\r
- UINT32 PowerUnits:4;\r
- UINT32 Reserved1:4;\r
+ UINT32 PowerUnits : 4;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bits 12:8] Package. Energy Status Units Energy related information\r
/// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r
/// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r
/// micro-joules).\r
///\r
- UINT32 EnergyStatusUnits:5;\r
- UINT32 Reserved2:3;\r
+ UINT32 EnergyStatusUnits : 5;\r
+ UINT32 Reserved2 : 3;\r
///\r
/// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r
/// Interfaces.".\r
///\r
- UINT32 TimeUnits:4;\r
- UINT32 Reserved3:12;\r
- UINT32 Reserved4:32;\r
+ UINT32 TimeUnits : 4;\r
+ UINT32 Reserved3 : 12;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_RAPL_POWER_UNIT_REGISTER;\r
\r
-\r
/**\r
Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
Domain.".\r
@endcode\r
@note MSR_XEON_D_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
**/\r
-#define MSR_XEON_D_DRAM_POWER_LIMIT 0x00000618\r
-\r
+#define MSR_XEON_D_DRAM_POWER_LIMIT 0x00000618\r
\r
/**\r
Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices.\r
@endcode\r
@note MSR_XEON_D_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_XEON_D_DRAM_ENERGY_STATUS 0x00000619\r
+#define MSR_XEON_D_DRAM_ENERGY_STATUS 0x00000619\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_D_DRAM_ENERGY_STATUS\r
/// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration\r
/// to enable DRAM RAPL mode 0 (Direct VR).\r
///\r
- UINT32 Energy:32;\r
- UINT32 Reserved:32;\r
+ UINT32 Energy : 32;\r
+ UINT32 Reserved : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER;\r
\r
-\r
/**\r
Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
RAPL Domain.".\r
@endcode\r
@note MSR_XEON_D_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
**/\r
-#define MSR_XEON_D_DRAM_PERF_STATUS 0x0000061B\r
-\r
+#define MSR_XEON_D_DRAM_PERF_STATUS 0x0000061B\r
\r
/**\r
Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
@endcode\r
@note MSR_XEON_D_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
**/\r
-#define MSR_XEON_D_DRAM_POWER_INFO 0x0000061C\r
-\r
+#define MSR_XEON_D_DRAM_POWER_INFO 0x0000061C\r
\r
/**\r
Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r
AsmWriteMsr64 (MSR_XEON_D_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_XEON_D_MSRUNCORE_RATIO_LIMIT 0x00000620\r
+#define MSR_XEON_D_MSRUNCORE_RATIO_LIMIT 0x00000620\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_D_MSRUNCORE_RATIO_LIMIT\r
/// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r
/// LLC/Ring.\r
///\r
- UINT32 MAX_RATIO:7;\r
- UINT32 Reserved1:1;\r
+ UINT32 MAX_RATIO : 7;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r
/// possible ratio of the LLC/Ring.\r
///\r
- UINT32 MIN_RATIO:7;\r
- UINT32 Reserved2:17;\r
- UINT32 Reserved3:32;\r
+ UINT32 MIN_RATIO : 7;\r
+ UINT32 Reserved2 : 17;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER;\r
\r
/**\r
@endcode\r
@note MSR_XEON_D_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_XEON_D_PP0_ENERGY_STATUS 0x00000639\r
-\r
+#define MSR_XEON_D_PP0_ENERGY_STATUS 0x00000639\r
\r
/**\r
Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
@endcode\r
@note MSR_XEON_D_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
**/\r
-#define MSR_XEON_D_CORE_PERF_LIMIT_REASONS 0x00000690\r
+#define MSR_XEON_D_CORE_PERF_LIMIT_REASONS 0x00000690\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_D_CORE_PERF_LIMIT_REASONS\r
/// reduced below the operating system request due to assertion of\r
/// external PROCHOT.\r
///\r
- UINT32 PROCHOT_Status:1;\r
+ UINT32 PROCHOT_Status : 1;\r
///\r
/// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
/// operating system request due to a thermal event.\r
///\r
- UINT32 ThermalStatus:1;\r
+ UINT32 ThermalStatus : 1;\r
///\r
/// [Bit 2] Power Budget Management Status (R0) When set, frequency is\r
/// reduced below the operating system request due to PBM limit.\r
///\r
- UINT32 PowerBudgetManagementStatus:1;\r
+ UINT32 PowerBudgetManagementStatus : 1;\r
///\r
/// [Bit 3] Platform Configuration Services Status (R0) When set,\r
/// frequency is reduced below the operating system request due to PCS\r
/// limit.\r
///\r
- UINT32 PlatformConfigurationServicesStatus:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 PlatformConfigurationServicesStatus : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)\r
/// When set, frequency is reduced below the operating system request\r
/// because the processor has detected that utilization is low.\r
///\r
- UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;\r
+ UINT32 AutonomousUtilizationBasedFrequencyControlStatus : 1;\r
///\r
/// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
/// below the operating system request due to a thermal alert from the\r
/// Voltage Regulator.\r
///\r
- UINT32 VRThermAlertStatus:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 VRThermAlertStatus : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r
/// reduced below the operating system request due to electrical design\r
/// point constraints (e.g. maximum electrical current consumption).\r
///\r
- UINT32 ElectricalDesignPointStatus:1;\r
- UINT32 Reserved3:1;\r
+ UINT32 ElectricalDesignPointStatus : 1;\r
+ UINT32 Reserved3 : 1;\r
///\r
/// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced\r
/// below the operating system request due to Multi-Core Turbo limits.\r
///\r
- UINT32 MultiCoreTurboStatus:1;\r
- UINT32 Reserved4:2;\r
+ UINT32 MultiCoreTurboStatus : 1;\r
+ UINT32 Reserved4 : 2;\r
///\r
/// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced\r
/// below max non-turbo P1.\r
///\r
- UINT32 FrequencyP1Status:1;\r
+ UINT32 FrequencyP1Status : 1;\r
///\r
/// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When\r
/// set, frequency is reduced below max n-core turbo frequency.\r
///\r
- UINT32 TurboFrequencyLimitingStatus:1;\r
+ UINT32 TurboFrequencyLimitingStatus : 1;\r
///\r
/// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is\r
/// reduced below the operating system request.\r
///\r
- UINT32 FrequencyLimitingStatus:1;\r
+ UINT32 FrequencyLimitingStatus : 1;\r
///\r
/// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 PROCHOT_Log:1;\r
+ UINT32 PROCHOT_Log : 1;\r
///\r
/// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 ThermalLog:1;\r
+ UINT32 ThermalLog : 1;\r
///\r
/// [Bit 18] Power Budget Management Log When set, indicates that the PBM\r
/// Status bit has asserted since the log bit was last cleared. This log\r
/// bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 PowerBudgetManagementLog:1;\r
+ UINT32 PowerBudgetManagementLog : 1;\r
///\r
/// [Bit 19] Platform Configuration Services Log When set, indicates that\r
/// the PCS Status bit has asserted since the log bit was last cleared.\r
/// This log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 PlatformConfigurationServicesLog:1;\r
- UINT32 Reserved5:1;\r
+ UINT32 PlatformConfigurationServicesLog : 1;\r
+ UINT32 Reserved5 : 1;\r
///\r
/// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r
/// indicates that the AUBFC Status bit has asserted since the log bit was\r
/// last cleared. This log bit will remain set until cleared by software\r
/// writing 0.\r
///\r
- UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r
+ UINT32 AutonomousUtilizationBasedFrequencyControlLog : 1;\r
///\r
/// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
/// Alert Status bit has asserted since the log bit was last cleared. This\r
/// log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 VRThermAlertLog:1;\r
- UINT32 Reserved6:1;\r
+ UINT32 VRThermAlertLog : 1;\r
+ UINT32 Reserved6 : 1;\r
///\r
/// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r
/// Status bit has asserted since the log bit was last cleared. This log\r
/// bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 ElectricalDesignPointLog:1;\r
- UINT32 Reserved7:1;\r
+ UINT32 ElectricalDesignPointLog : 1;\r
+ UINT32 Reserved7 : 1;\r
///\r
/// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core\r
/// Turbo Status bit has asserted since the log bit was last cleared. This\r
/// log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 MultiCoreTurboLog:1;\r
- UINT32 Reserved8:2;\r
+ UINT32 MultiCoreTurboLog : 1;\r
+ UINT32 Reserved8 : 2;\r
///\r
/// [Bit 29] Core Frequency P1 Log When set, indicates that the Core\r
/// Frequency P1 Status bit has asserted since the log bit was last\r
/// cleared. This log bit will remain set until cleared by software\r
/// writing 0.\r
///\r
- UINT32 CoreFrequencyP1Log:1;\r
+ UINT32 CoreFrequencyP1Log : 1;\r
///\r
/// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,\r
/// indicates that the Core Max n-core Turbo Frequency Limiting Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 TurboFrequencyLimitingLog:1;\r
+ UINT32 TurboFrequencyLimitingLog : 1;\r
///\r
/// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core\r
/// Frequency Limiting Status bit has asserted since the log bit was last\r
/// cleared. This log bit will remain set until cleared by software\r
/// writing 0.\r
///\r
- UINT32 CoreFrequencyLimitingLog:1;\r
- UINT32 Reserved9:32;\r
+ UINT32 CoreFrequencyLimitingLog : 1;\r
+ UINT32 Reserved9 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER;\r
\r
-\r
/**\r
THREAD. Monitoring Event Select Register (R/W) if CPUID.(EAX=07H,\r
ECX=0):EBX.RDT-M[bit 12] = 1.\r
@endcode\r
@note MSR_XEON_D_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.\r
**/\r
-#define MSR_XEON_D_IA32_QM_EVTSEL 0x00000C8D\r
+#define MSR_XEON_D_IA32_QM_EVTSEL 0x00000C8D\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_D_IA32_QM_EVTSEL\r
/// occupancy monitoring 0x02: Total memory bandwidth monitoring 0x03:\r
/// Local memory bandwidth monitoring All other encoding reserved.\r
///\r
- UINT32 EventID:8;\r
- UINT32 Reserved1:24;\r
+ UINT32 EventID : 8;\r
+ UINT32 Reserved1 : 24;\r
///\r
/// [Bits 41:32] RMID (RW).\r
///\r
- UINT32 RMID:10;\r
- UINT32 Reserved2:22;\r
+ UINT32 RMID : 10;\r
+ UINT32 Reserved2 : 22;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_IA32_QM_EVTSEL_REGISTER;\r
\r
-\r
/**\r
THREAD. Resource Association Register (R/W).\r
\r
@endcode\r
@note MSR_XEON_D_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.\r
**/\r
-#define MSR_XEON_D_IA32_PQR_ASSOC 0x00000C8F\r
+#define MSR_XEON_D_IA32_PQR_ASSOC 0x00000C8F\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_D_IA32_PQR_ASSOC\r
///\r
/// [Bits 9:0] RMID.\r
///\r
- UINT32 RMID:10;\r
- UINT32 Reserved1:22;\r
+ UINT32 RMID : 10;\r
+ UINT32 Reserved1 : 22;\r
///\r
/// [Bits 51:32] COS (R/W).\r
///\r
- UINT32 COS:20;\r
- UINT32 Reserved2:12;\r
+ UINT32 COS : 20;\r
+ UINT32 Reserved2 : 12;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_IA32_PQR_ASSOC_REGISTER;\r
\r
-\r
/**\r
Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H,\r
ECX=1):EDX.COS_MAX[15:0] >= n.\r
MSR_XEON_D_IA32_L3_QOS_MASK_15 is defined as IA32_L3_QOS_MASK_15 in SDM.\r
@{\r
**/\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_0 0x00000C90\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_1 0x00000C91\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_2 0x00000C92\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_3 0x00000C93\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_4 0x00000C94\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_5 0x00000C95\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_6 0x00000C96\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_7 0x00000C97\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_8 0x00000C98\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_9 0x00000C99\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_10 0x00000C9A\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_11 0x00000C9B\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_12 0x00000C9C\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_13 0x00000C9D\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_14 0x00000C9E\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_15 0x00000C9F\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_0 0x00000C90\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_1 0x00000C91\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_2 0x00000C92\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_3 0x00000C93\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_4 0x00000C94\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_5 0x00000C95\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_6 0x00000C96\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_7 0x00000C97\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_8 0x00000C98\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_9 0x00000C99\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_10 0x00000C9A\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_11 0x00000C9B\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_12 0x00000C9C\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_13 0x00000C9D\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_14 0x00000C9E\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_15 0x00000C9F\r
/// @}\r
\r
/**\r
///\r
/// [Bits 19:0] CBM: Bit vector of available L3 ways for COS 0 enforcement.\r
///\r
- UINT32 CBM:20;\r
- UINT32 Reserved2:12;\r
- UINT32 Reserved3:32;\r
+ UINT32 CBM : 20;\r
+ UINT32 Reserved2 : 12;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER;\r
\r
-\r
/**\r
Package. Config Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
RW if MSR_PLATFORM_INFO.[28] = 1.\r
@endcode\r
@note MSR_XEON_D_TURBO_RATIO_LIMIT3 is defined as MSR_TURBO_RATIO_LIMIT3 in SDM.\r
**/\r
-#define MSR_XEON_D_TURBO_RATIO_LIMIT3 0x000001AC\r
+#define MSR_XEON_D_TURBO_RATIO_LIMIT3 0x000001AC\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT3\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:32;\r
- UINT32 Reserved2:31;\r
+ UINT32 Reserved1 : 32;\r
+ UINT32 Reserved2 : 31;\r
///\r
/// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,\r
/// the processor uses override configuration specified in\r
/// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1. If 0, the processor\r
/// uses factory-set configuration (Default).\r
///\r
- UINT32 TurboRatioLimitConfigurationSemaphore:1;\r
+ UINT32 TurboRatioLimitConfigurationSemaphore : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER;\r
\r
-\r
/**\r
Package. Cache Allocation Technology Configuration (R/W).\r
\r
@endcode\r
@note MSR_XEON_D_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.\r
**/\r
-#define MSR_XEON_D_IA32_L3_QOS_CFG 0x00000C81\r
+#define MSR_XEON_D_IA32_L3_QOS_CFG 0x00000C81\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_D_IA32_L3_QOS_CFG\r
///\r
/// [Bit 0] CAT Enable. Set 1 to enable Cache Allocation Technology.\r
///\r
- UINT32 CAT:1;\r
- UINT32 Reserved1:31;\r
- UINT32 Reserved2:32;\r
+ UINT32 CAT : 1;\r
+ UINT32 Reserved1 : 31;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER;\r
\r
#endif\r
projects / mirror_edk2.git / blobdiff