Update the comment for RegisterForRunimeAccess() functions to match the Spec.

[mirror_edk2.git] / MdePkg / Library / BaseCacheMaintenanceLib / IpfCache.c

diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
index 1007b4448f0237af05432b4180d0c8d4e30bf64f..9b940fc3f76d49ed208a3759b268141b6d48d27b 100644 (file)
--- a/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
@@ -1,7 +1,7 @@
 /** @file\r
   Cache Maintenance Functions.\r
 \r
-  Copyright (c) 2006, Intel Corporation<BR>\r
+  Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
   All rights reserved. This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -12,15 +12,11 @@
 \r
 **/\r
 \r
-\r
-//\r
-// Include common header file for this module.\r
-//\r
 #include <Base.h>\r
 #include <Library/CacheMaintenanceLib.h>\r
 #include <Library/BaseLib.h>\r
 #include <Library/DebugLib.h>\r
-#include <Library/PalCallLib.h>\r
+#include <Library/PalLib.h>\r
 \r
 /**\r
   Invalidates the entire instruction cache in cache coherency domain of the\r
@@ -36,7 +32,7 @@ InvalidateInstructionCache (
   VOID\r
   )\r
 {\r
-  PalCall (1, 1, 1, 0);\r
+  PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_INSTRUCTION_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);\r
 }\r
 \r
 /**\r
@@ -61,7 +57,7 @@ InvalidateInstructionCache (
 \r
   @param  Length  The number of bytes to invalidate from the instruction cache.\r
 \r
-  @return Address\r
+  @return Address.\r
 \r
 **/\r
 VOID *\r
@@ -71,7 +67,8 @@ InvalidateInstructionCacheRange (
   IN      UINTN                     Length\r
   )\r
 {\r
-  return IpfFlushCacheRange (Address, Length);\r
+  ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
+  return AsmFlushCacheRange (Address, Length);\r
 }\r
 \r
 /**\r
@@ -90,7 +87,7 @@ WriteBackInvalidateDataCache (
   VOID\r
   )\r
 {\r
-  PalCall (1, 2, 1, 0);\r
+  PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_DATA_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);\r
 }\r
 \r
 /**\r
@@ -116,7 +113,7 @@ WriteBackInvalidateDataCache (
   @param  Length  The number of bytes to write back and invalidate from the\r
                   data cache.\r
 \r
-  @return Address\r
+  @return Address of cache invalidation.\r
 \r
 **/\r
 VOID *\r
@@ -128,7 +125,7 @@ WriteBackInvalidateDataCacheRange (
 {\r
   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
 \r
-  return IpfFlushCacheRange (Address, Length);\r
+  return AsmFlushCacheRange (Address, Length);\r
 }\r
 \r
 /**\r
@@ -147,7 +144,7 @@ WriteBackDataCache (
   VOID\r
   )\r
 {\r
-  PalCall (1, 2, 0, 0);\r
+  PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_DATA_ALL, PAL_CACHE_FLUSH_NO_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);\r
 }\r
 \r
 /**\r
@@ -172,7 +169,7 @@ WriteBackDataCache (
                   mode, then Address is a virtual address.\r
   @param  Length  The number of bytes to write back from the data cache.\r
 \r
-  @return Address\r
+  @return Address of cache written in main memory.\r
 \r
 **/\r
 VOID *\r
@@ -184,7 +181,7 @@ WriteBackDataCacheRange (
 {\r
   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
 \r
-  return IpfFlushCacheRange (Address, Length);\r
+  return AsmFlushCacheRange (Address, Length);\r
 }\r
 \r
 /**\r
@@ -204,6 +201,10 @@ InvalidateDataCache (
   VOID\r
   )\r
 {\r
+  //\r
+  // Invalidation of entire data cache without writing back is not supported on\r
+  // IPF architecture, so write back and invalidate operation is performed.\r
+  //\r
   WriteBackInvalidateDataCache ();\r
 }\r
 \r
@@ -231,7 +232,7 @@ InvalidateDataCache (
                   then Address is a virtual address.\r
   @param  Length  The number of bytes to invalidate from the data cache.\r
 \r
-  @return Address\r
+  @return Address.\r
 \r
 **/\r
 VOID *\r
@@ -241,5 +242,10 @@ InvalidateDataCacheRange (
   IN      UINTN                     Length\r
   )\r
 {\r
-  return IpfFlushCacheRange (Address, Length);\r
+  ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
+  //\r
+  // Invalidation of a data cache range without writing back is not supported on\r
+  // IPF architecture, so write back and invalidate operation is performed.\r
+  //\r
+  return AsmFlushCacheRange (Address, Length);\r
 }\r